JPS6033634A - Data processing device - Google Patents

Abstract

PURPOSE:To reduce the number of connecting terminals to a memory part of a central processing part without decreasing a data processing speed by switching as to whether a transfer destination is program storage or data storage, in accordance with the kind of an executing instruction. CONSTITUTION:In case when it is shown to be processing data access by a DATA signal, the first AND gate groups A1-An are opened, the second AND gate groups B1-Bn are closed, and address information DA1-DAn of a data memory part is outputted to terminals P1-Pn. Also, in case when it is shown that no processing data access exists by the DATA signal, an output of an inverting circuit I to which its signal is inputted becomes effective, the first AND gate groups A1-An are closed, the second AND gate groups B1-Bn are opened, and address information PA1-PAn of a program memory part is outputted to the terminals P1-Pn. This output is connected to an address information transfer line 31 to both the program and data memory parts 2, 3 from a central processing part 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to program controlled data processing devices, and more particularly to single integrated circuit chip data processing devices.

In general, program-controlled data processing devices are classified into three main parts: a central processing section, a memory section, and an input/output section.Based on a counter that specifies the program sequence in the central processing section,
Addressing the memory section and reading out an instruction word that is a unit element of a program (hereinafter referred to as instruction fetch), decoding the instruction word to generate address information of the data to be processed, and reading out the data stored in the memory section at that address. Read out,
Performs processing such as operation of calculation judgment and writing of the result to the memory section (hereinafter referred to as processing data access).

Further, depending on the command, processing data is fetched to the outside of the data processing device via an input/output section, and processing results are output. (Since the present invention does not involve the input/output section, it will be omitted from the following explanation.) Data processing devices are capable of processing various arithmetic decisions using programs that are combinations of instruction words. It is used as a control device with intellectual functions such as In recent years, as the field of use has expanded, it has become desirable to improve the processing performance of data processing equipment. Attempts are being made to speed it up.

One of these is a structure that focuses on data transfer between the central processing unit and the memory unit, and separates the memory unit into program storage and processing data storage, allowing instruction fetch and processing data access to be performed in parallel. There is something. In other words, in a typical structure, in order to execute a single instruction word, it is necessary to transfer data to and from the memory unit multiple times during instruction fetch and processing data access, and the processing speed is determined by the data transfer time. are doing. However, in the structure described above, since the memory section is separated, it is possible to simultaneously access the processing data for executing a certain instruction and simultaneously execute the 7 fetches for the next instruction to be executed, and the processing speed is faster than the instruction fetch or Processing data access is determined by whichever memory-to-memory data transfer time is longer. Therefore, compared to a device with a general structure, a device with the above structure that transfers data between memories in parallel can process data at high speed.

FIG. 1 is a block diagram for explaining such a conventional data processing device, which includes a central processing unit l for processing data, a program memory unit 2 for storing programs, and a data memory unit for storing processed data. Consists of 3. In a conventional data processing device, a central processing unit 1 transfers information indicating a program sequence to a program memory unit 2 via a transfer line 11, generates a signal on a read control line 12, and issues a command via a transfer line 13. read.

The instruction word fetched in the instruction fetch operation is decoded by the central processing unit l, and predetermined data processing is performed. When the instruction is to process information stored in the data memory section 3, the central processing section l transfers addressing information to the data memory section 3 via the transfer line 14, and sends it to the read control signal line 15 or write control signal line 15. A control signal is generated on the first signal line 16, and processing data is transferred via the transfer line 17. Furthermore, transfer #i! In data transfer in xr, the direction of information transfer changes: in the case of reading, the information is transferred to the central processing unit l, and in the case of writing, it is transferred to the data memory unit 3.

The processing data access operation for this data memory is completely separated from the instruction fetch operation, so it is not necessary to read the instruction word to be executed next while accessing the processing data in the execution of a certain instruction. This enables high-speed processing by parallelizing inter-memory transfers.

Although a device having a structure in which instruction fetching and processing data access are performed in parallel has the advantage of high speed, the data transfer line between the central processing section and the memory section is disadvantageous due to the separation of the memory section. There are increasing drawbacks. In other words, in addition to the address information and instruction word transfer line for instruction fetch, the structure described above requires address information and processing data transfer line for processing data access, which is typical for transferring address information and data in a memory section. Approximately twice as many signal lines are required compared to a device consisting of lines.

This increase in signal lines has been a fatal hindrance in data processing devices such as microcomputers that are integrated on a single semiconductor chip. In other words, integrated circuits are miniaturized by integrating a large number of circuits onto a chip, the dimensions of the chip and package are small, and there is a limit to the number of terminals for inputting and outputting information to and from the outside of the chip.

Therefore, those requiring a large number of information transfer lines are not suitable for integrated circuits.

Conventionally, in order to reduce the number of connection terminals with the memory section, a method has been adopted in which address information and memory data are transferred in a time-division manner through the same terminal. A block diagram of the block diagram is shown in FIG. Central processing section 1 in Figure 2. Program memory section 2.
The data memory section 3 and transfer lines 11-17 operate in the same manner as the conventional device shown in FIG. 1 and transfer the same information.

Since address information is transferred in a time-sharing manner, there is a program address register 4 that stores the address information of the program memory section 2, a data address register 5 that stores the address information of the data memory section 3, and a data address register 5 that stores the address information of the program memory section 2. Identification signal indicating address information transfer timing, 121.
24, a transfer line 22 to 25 through which address information and data are transferred in a time-division multiplex manner, and transfer of address information which is not multiplexed with data; 1. J723, 26 are added.

Central processing unit I and each memory unit 2 of the data processing device shown in Fig. 2
, 3 are similar, so the transfer operation with the data memory section 3 will be described below as an example. The transfer operation is to store the information of the transfer lines 25 and 26 in the transfer line 25 where the address information is multiplexed and the transfer #1126 which is not multiplexed, and output the stored value to the transfer line 14 as the address information to the memory section 3. do. Thereafter, data transfer is performed via the transfer line 16 and the multiplexed transfer line 25 based on the read control signal 15 or the write control signal 16 as in FIG.

As mentioned above, the data processing device shown in FIG. 2 reduces the number of connection terminals between the central processing section l and the memory section 2.3 by time-division multiplexing transfer. Since there is a difference in the amount of information between 8 bits of data and 8 bits of data, it is not possible to multiplex all information, and the effect of reducing the number of terminals is small.

Furthermore, with multiplexed transfer, it is necessary to transfer two types of information in one memory-to-memory transfer, and considering the switching speed of the transfer signal line, etc., the time for memory-to-memory transfer increases, which reduces the processing speed of the data processing device. This may lead to a decline.

Furthermore, since the direction of information transfer changes, the multiplexed terminal circuit requires a complex circuit capable of both input and output.

The present invention focuses on the operation of information transfer with the memory unit related to instruction execution, and multiplexes the address information that is always transferred from the central processing unit to the memory unit, so that the transfer destination is programmed according to the type of execution instruction. By switching between storage and data storage, there is no problem with the switching speed of the transfer signal line, and the memory connection terminal circuit in the central processing section can be a simple output-only circuit, creating a data processing device with fewer connection terminals. It provides:

Generally speaking, if we look at the types of instructions that execute the operations of a data processing device, in the case of a branch instruction that modifies a program sequence, the address information of the branch destination is written to the sequence counter, and processing data access to the memory section does not occur. .

In the case of an instruction that manipulates data stored in the memory section, the predetermined processing data is accessed to the memory section, and at the same time, the sequence counter V is incremented by a predetermined amount and the instruction word address to be executed next is accessed from the memory section of the modified step. This is the command word reading.

The present invention has been made by focusing on the fact that instruction address modification by branching and processing data access are exclusive, and that there is regularity in address changes during normal instruction fetch.

According to the present invention, the invention comprises a central processing unit that processes data, a program memory unit that stores programs, and a data memory unit that stores processed data, and reads instruction information from the program memory unit and transfers processed data to and from the data memory unit in parallel. A data processing apparatus comprising: an instruction information transfer means, a processing data transfer means, and an address transfer means for transferring instruction address information from a central processing section to a program memory section or processing address information from a central processing section to a data memory section; There is obtained a data processing device characterized in that the transfer information of the address transfer means is selectively switched and transferred to a predetermined memory section in response to an execution command of a processing section.

The data processing device of the present invention transfers address information to both memory units for storing single address information, and transfers the address information to sequence information for program storage or processing data in response to an instruction executed by the central processing unit. In other words, in the case of an instruction that accesses processing data, address information for processing data storage is transferred to the address transfer means, and in the case of an instruction that does not access processing data, program sequence information is transferred to the address transfer means. is transferred.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a data processing device according to an embodiment of the present invention, which includes a central processing unit l for processing data, a program memory unit 2 for storing programs, a data memory unit 3 for storing processed data, and It consists of an address register 6 that stores address designation values for the program memory section.

In the device of the embodiment shown in FIG. 3, the addressing information transfer line 11 . Read control signal line 12.
Data transfer of program memory unit 2 li3. Read control signal line 15 of data memory section 3. Write control signal line 16. In addition to the processing data transfer line 17 of the data memory section 3, an address information transfer line 31 for both program and data memory sections 2 and 3, and a signal transfer line 32 for identifying the destination of the address information are connected to the center. Information is transferred between the processing section 1 and the memory section 2.3. Note that signal lines 11 to 17 are for transmitting information similar to that of the conventional device shown in FIG.

In the data processing device of the embodiment shown in FIG. 3, the type of information output to the address information transfer line 31 is switched according to the type of instruction executed by the central processing unit l, and the type of address information is identified in conjunction with the switching. A signal for this purpose is output to the signal line 32.

In the case of an instruction that does not process data stored in the data memory section 3, program sequence information is output to the transfer line 31,
An identification signal indicating that the transfer is to the program memory section 2 is sent to the signal line 32, and the output is stored in the address register 6 and simultaneously outputted to the transfer line 11 as address information of the program memory section 2. Therefore, the program sequence information is transferred from the central processing unit 1 through the transfer line 31, address register 6, and transfer line 11, and the read 9 control signal 1
2, the instruction word is read out and transferred to the central processing unit l via the transfer line 13. Note that processing data access is not generated and the data memory section 3 is not affected at all at this time.When executing an instruction to process data stored in the data memory section 3, the address information of the processing data is output to the transfer line 31, An identification signal indicating that processing data is being accessed is output to the signal line 32. The central processing unit l is connected via this line 13.
Transfer to.

When this is known, the stored sequence value is incremented by a predetermined value, and then the instruction word is modified to the sequence value to be read. As a result, address information for reading command words from the program memory section 2 is always generated on the transfer line 11. Therefore, even if processing data access continues and address information to the data memory section is transferred to the transfer line 31 and no program sequence information is transferred, the command word can be read from the program memory section 2. , instruction word fetch and processing data access are performed in parallel.

When executing a branch instruction in which the program sequence is changed, the processing in the central processing unit 1 is to write the sequence information to be branched into the sequence counter.
xLl There is no access to Igo-AJ Ko 11 Jawa. Therefore, at this time, the address information of the branch destination is taken into the transfer line register register.

The data processing apparatus shown in FIG. 3 requires a circuit for switching the type of address information to be transferred to the central processing section, and an example of the logic circuit is shown in FIG.

The address information switching circuit in FIG.
l) is a signal indicating access to processing data by executing an instruction (based on DATAIC, zllo eye toge-1 (A
I-A n and B l-B n ) and the terminal (P
s-pn). In addition, the terminals (PI to PIl) F
i It is connected to the address information transfer line 31 in FIG.

When the IJATA signal indicates processing data access, the first AND gate group (Al to An) is opened, and the second AND gate group (Bl-B,) is closed to access the address information of the data memory section. The f-report (DAt~DA,) is the terminal (
Pl-P-). When the DATA signal indicates that there is no processing data access, the output of the inverting circuit (I) to which that signal is input becomes valid, the first AND gate group (A1 to An) closes, and the first The two AND gate groups (Bz-B,) are opened and the address information (PAt-PA,) of the program memory section is output to the terminals (Pi-P,).

The circuit shown in FIG. 5 is generally called a data selector, and in the case of an integrated circuit device, it is a simple circuit that can be constructed of several transistors each with one terminal. □ Therefore, according to the device of the embodiment shown in FIG. 3, since the switching signal is transferred in one direction from the central processing unit l to the memory units 2 and 3, the connection terminal circuit is a simple circuit dedicated to output. This requires less circuitry than the time-division multiplexed bidirectional transfer shown in FIG.

As described above, in the device of the embodiment shown in FIG. 3, by switching the type of address information to be transferred depending on the type of instruction, connection with the memory section can be achieved without impairing the high speed of parallel memory-to-memory transfer. This has the effect of reducing the number of terminals and simplifying the circuit of the connecting terminals.

When the present invention is applied to the apparatus 1 for multiplexing address information and data shown in FIG. 2, it is possible to further reduce the number of terminals. A block diagram of this embodiment is shown in FIG.

The apparatus shown in FIG. 4 includes a central processing section 1, a program memory section 2.
Data memory section 3. Program address register 7. It consists of a data address register 8, an addressing information transfer line 11 of the program memory section 2, a read control signal line 12. Command data transfer line 13. Addressing information transfer line 14 of data memory section 3. Read control signal line 15. Saving control signal line 16. In addition to the processing data transfer line 17, there are identification signal lines 43, 44 indicating the timing of transferring address information to each memory section, and transfer lines 41, 41, 44, 44, 44, 44, 44, 44, 43, 44, 44, 44, 44, 44, 44, 44, 43, 44, 43, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 50, 44 types or different or different or different or different or different, type or type form type order form type and types type form type form form. Address information and processing are multiplexed and transferred in the same way as the conventional device shown in Figure 2.

In the conventional device shown in FIG. 2, there is a multiplexed transfer line corresponding to each memory section 2 and 3, and there is a difference between the number of bits of memory address information and the number of bits of data. The effect of reducing the number of connection terminals was small because there were transfer lines that could not be completely multiplexed and were used only for address information transfer, but in the device of the embodiment shown in FIG. On the other hand, address information can be transferred using a single address transfer line, and the address information transfer line is divided into two groups of transfer lines 41 and 42, and each group transfers command words or processing data. be multiplexed and used.

Therefore, in the device shown in FIG. 4, the number of connection terminals with the memory section excluding the control signal line is the greater of the sum of the number of instruction word bits and the number of processing data bits, or the number of bits of address information of the program and data memory. In the embodiment, the upper 8 bits of 16-bit address information, 8-bit command information, and 8-bit processing data are transferred to the transfer line 41, and all transfer terminals are used for multiplexed transfer of address and memory data. ing. In this case, with the configuration shown in FIG. 1, the number of connection terminals required to transfer address information and data to the memory section could be reduced to one-third in the device shown in FIG. 4.

As explained above, according to the present invention, the number of connection terminals to the memory section of the central processing section can be effectively increased without reducing the processing speed of a data processing device in which the memory section is divided into program storage and data storage. This is particularly effective in integrated circuit data processing devices where the number of connection terminals is limited to 6.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional data processing device 41, FIGS. 3 and 4 are block diagrams of an embodiment of the present invention, and FIG. 5 is a logic diagram of the address information switching circuit in FIG. 3. It is a circuit diagram. 1...Central processing section, 2...Program memory section, 3...Data memory section, 4-8...
... Address information register, 11 ... Address information transfer line of program memory section, 12 ...
・Read control signal line of program memory section, 13...
...Instruction word transfer line of program memory section, 14...
...Address information transfer line of data memory section, 15.
... Read control signal line of data memory section, 16
...Write control signal line of data memory section, 1
7... Processing data transfer line of data memory section, 2
1... Identification signal line for address information transfer of program memory section, 22... Multiplexed information transfer line of program memory section, 23... Non-multiplexed program memory section Address information transfer line, 24...
・Identification signal line for address information transfer of data memory section,
25...Multiplexed information transfer line of data memory section,
26...Non-multiplexed address information transfer line of data memory section, 31...Address information transfer line, 32...Address type identification signal line, 41.
42... Multiplexed information transfer line, 43...
Identification signal line for address information transfer to the program memory section, 44...--Identification signal line for address information transfer to the data memory section, At~An, B1~lJn・River...AND gate, 01~ On......OR gate, ■...Inversion circuit, Pi~Pn...
Connection terminals, PAt~PAn... Address information to program memory section, 1) Al~D An...
・Address information to data memory section + Id, DATA・
...Signal indicating processing data access. Attached conspiracy Z121 u 3 autopsy 4 times

Claims (1)

[Claims] (],) Consists of a central processing unit that processes data, a program memory unit that stores programs, and a data memory unit that stores final processing data, and reads instruction information from the program memory unit and functions as a data memory unit. In a data processing device in which processing data transfer is performed in parallel, an instruction information transfer means, a processing data transfer means, and a central processing section transfer instruction address information from a central processing section to a program memory section or processing address information from a data memory section. 1. A data processing device comprising an address transfer means, and selectively switches and transfers transfer information of the address transfer means to a predetermined memory section in response to an execution command from a central processing section. (2) In the data processing device according to claim U, the information transfer terminals of the central processing unit are divided into two groups for multiplex transfer in a short period of time, and the first group of information transfer terminals is instructed. A data processing device characterized in that an information transfer means and an address information transfer means use the second group of information transfer terminals, and the processing data transfer means and the address information transfer means use a second group of information transfer terminals.