KR100810262B1 - Memory sharing apparatus using split logic circuit - Google Patents

Abstract

The present invention relates to a method of efficiently sharing memory using separation logic that can programmatically divide and use two memories having different capacities. The present invention performs a unique function and requires different memory capacities. An integrated memory shared by the first and second functional blocks, the first and second functional blocks and having self-diagnostic logic, and a write / write for causing the first and second functional blocks to use the integrated memory; First and second memory control logics for generating a read address signal and a write / read enable signal, respectively, and separating the entire memory area of the integrated memory into a first memory area and a second memory area, respectively; And a separate logic for providing the integrated memory with a write / read address signal converted to be suitable for the area. As a result, the present invention can make the memory device more efficient, smaller, and more integrated, and can minimize operational processing delays.

Memory Sharing, Separation Logic

Description

Memory sharing device using separate logic {MEMORY SHARING APPARATUS USING SPLIT LOGIC CIRCUIT}             

1 is a diagram illustrating a bidirectional synchronous random access memory (DPSRAM) used in a typical modem chip.

2 is a block diagram showing an apparatus using different sizes of memory of the same type according to the prior art;

3 is a block diagram illustrating a device using an integrated memory in the prior art.

4 is a block diagram showing the configuration of a memory sharing apparatus using separate logic in accordance with the present invention;

5 is a view showing a detailed configuration and connection of the separation logic shown in FIG.

6 is a flowchart illustrating an operation of simultaneously writing / reading the unified memory according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a method of efficiently sharing memory by using separation logic that can programmatically divide and write two memories having different capacities.

In general, communication hardware logics constituting a modem chip in a cellular phone or a multimedia communication related terminal have a relatively larger gate count of memory used to implement a communication function than other logic blocks. As the needs of users are diversified and communication technologies are developed, this ratio is increasing. Therefore, if the memory is not used efficiently, the number of gates of the entire chip is unnecessarily large and the size of the chip is large.

The modem chip consists of blocks that perform a number of unique communication functions (encoding, puncturing, interleaving, symbol repetition, modulation, serial / parallel conversion, etc.). After processing, it needs various capacities of memory.

FIG. 1 is a diagram illustrating a dual port synchronous random access memory (DPSRAM) used in a general modem chip. As illustrated, the bidirectional SRAM 100 may simultaneously perform write and read operations, simultaneously perform different write operations, or simultaneously perform different read operations. The bidirectional SRAM 100 is typically used for the purpose of simultaneously performing write / read or read / write.

Referring to FIG. 1, when the write enable input port WEN1 (or WEN2) is low and the read enable input port CSN1 (or CSN2) is low, the clock CK1 ( Alternatively, data is input through the data input port DI1 (or DI2) at the rising edge of CK2 (clock). In addition, when the read operation is described, data is output through DOUT1 (or DOUT2) at the rise of CK1 when WEN1 is high and CSN1 is low.

The memory operating as described above requires additional logics, such as logic for controlling the memory and self-diagnostic logic for self-testing the memory, in addition to a repository for storing actual data. Thus, the larger the number of memory required, the larger the number of additional logics for the memory than the logic that performs the unique communication functions of the actual modem chip.

2 is a block diagram illustrating a structure using different types of memories of the same type according to the related art. This is a memory structure that assumes that two hardware blocks that perform different functions perform functions with different sizes of memory, and as illustrated, function logic (210) (410) and memory. Hardware block 200, 400, including the control logic (220, 420), memory block (310, 510) and a memory block including the self test logic (Self Test Logic) (320, 520) 300).

Referring to FIG. 2, the memory block 300 includes a memory A 310 having a 1000 × 8 capacity (1000 bytes), and the memory block 500 includes a memory B 510 having a 100 × 8 capacity (100 bytes). . The hardware functional block 200 connected to the memory block 300 includes a functional logic 210 and control signals for the memory A 310, that is, WRITE_POINTER 221, READ_POINTER 222, and WRITE_EN 223. And a memory control logic A 220 for generating a READ_EN 224 and the like, wherein the memory block 300 is implemented as a chip and then self-diagnostic logic 320 to self-diagnose the memory A 310 in the chip. ).

Similarly, the hardware functional block 400 connected to the memory block 500 includes a functional logic 410, control signals for the memory B 310, that is, a write address signal WRITE_POINTER 421 and a read address signal READ_POINTER ( 422), a memory control logic B 420 that generates a write enable signal WRITE_EN 423, a read enable signal READ_EN 424, and the like, and wherein the memory block 500 is implemented as a chip and then Self-diagnostic logic 520 for self-diagnosing memory B 510.

In this case, as shown in FIG. 2, the two memory blocks 300 and 500 used for different functions are spaced apart from each other when laid out in one chip. Therefore, the memory control logic 220 and 420 and the self-diagnostic logic 320 and 520 for controlling the memories 310 and 510 were required, respectively.

3 illustrates a memory structure for reducing the number of self-diagnosis logic by using an integrated memory to solve this problem.

Referring to FIG. 3, the memory block 700 is shared by two functional logics 610 and 630, and thus requires only one integrated memory 710 and a self-diagnostic logic 720. In order to perform such memory consolidation, multiplexing logic 650 is required in order for the memory control logics 620 and 640 to share the unified memory 710. The multiplexing logic 650 connects the memory control logic A 620 to the integrated memory 710 when the function logic A 610 operates, and conversely, the memory control logic B when the function logic B 630 operates. 640 is connected to the unified memory 710.

In this structure, after the functional logic B 630 connects the signals of the memory control logic B 620 to the unified memory 710 using the multiplexing logic 650 to use the unified memory 710, the functional logic. In order for the A 610 to use the integrated memory 710, wait until the data processing of the function logic B 630 is completely completed, and then use the multiplexing logic 650 to output the signals of the memory control logic B 620 to the integrated memory 710. 710).

However, if the function logic A 610 needs a very small memory capacity and the function logic B 630 requires a very large memory capacity, while the function logic A 610 is operating, a small memory capacity is actually used. Despite the need for only the entire integrated memory 710 is connected to the memory control logic A (620) wasted a waste of memory capacity. In addition, since the function logic B 630 processes a very large amount of data, if the function logic A 610 wishes to use the unified memory 710 while the function logic B 630 is operating, the function logic B 630 is processed. ) Had to wait a lot of time until the data processing was completed. Therefore, there is a problem that a delay occurs in the operation processing due to the use of the integrated memory when several operations occur at the same time.

Accordingly, an object of the present invention, which was devised to solve the problems of the prior art operating as described above, is to provide a memory sharing apparatus that enables the use of the same type of integrated memory at the same time.

Another object of the present invention is to provide a memory sharing device that uses the same type of integrated memory at the same time using programmable separation logic.

Embodiment of the present invention created to achieve the object as described above,

First and second functional blocks that perform unique functions and require different memory capacities;

An integrated memory shared by the first and second functional blocks and having self-diagnostic logic;

First and second memory control logics respectively generating a write / read address signal and a write / read enable signal for causing the first and second functional blocks to use the integrated memory;

And a separate logic that separates the entire memory area of the integrated memory into a first memory area and a second memory area and provides the integrated memory with a write / read address signal converted to be suitable for each of the separated memory areas.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the preferred embodiment of the present invention. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

The present invention described below discloses a memory sharing apparatus that is an effective method for reducing the gate count of an entire chip in a structure using an integrated memory. The present invention includes one integrated memory having a larger memory capacity among different memory capacities required by two functional logics, and memory control logics having a memory separation function. The memory control logics recognize the integrated memory by area by the memory separating function and convert read / write addresses.

4 illustrates a configuration of a memory sharing apparatus using a separate logic according to the present invention. The function block 800 includes a function logic A 810, a function logic B 820, a memory control logic A 830, and a memory control logic B 840, and a memory connected to the function block 800. Apparatus 900 includes integrated memory 910 and self-diagnostic logic 940. The integrated memory 910 is a bidirectional dual port synchronous random access (SRAM) having a larger memory capacity among the memory capacity required by the functional logic A 310 and the memory capacity required by the functional logic B 820. Memory control logic A 830 of the functional logic A 820, which requires a smaller memory capacity, stores the entire memory area of the integrated memory 910 in the first memory area 920 and the second memory area. And a separate logic 835 for separating the address generated by the memory control logic A (830).

The functional logic A 810 requires a memory capacity of 100 x 8 and the functional logic B 820 requires a memory capacity of 1000 x 8, the integrated memory 910 is a total of 1000 x 8 It has a memory capacity. The total memory capacity of the unified memory 910 is separated by a logical pointer called a split pointer. In FIG. 4, a separation pointer 901 that logically divides the entire memory area of the integrated memory 910 into a 100 × 8 first memory area 920 and a 900 × 8 second memory area 930 is illustrated. The memory capacity of the 100 × 8 920 is a portion used in the operation of the function logic A 810. The separator pointer 901 may be changed programmatically according to whether the function logic A 810 operates or the function logic B 820 operates.

The memory control logic A 830 generates a write or read address as in the prior art when a memory access request of the function logic A 810 is performed. The separation logic 835 then converts the generated write or read address to be suitable for accessing the first memory area 920 using the separation pointer 901.

Hereinafter, the operation of the separation logic 835 will be described in detail.

Detailed configuration of the separation logic 835 and its connection is as shown in FIG. 5 illustrates a configuration of an address conversion unit 1200 for converting a write address generated by the address decoding logic 1100 of the memory control logic A 830 in the separation logic 835. Although not shown, an address conversion unit having the same configuration exists in the separation logic A 835 to convert a read address. In addition, in FIG. 5, the processor 100 is a controller that manages the operation of the entire function block 800 of FIG. 4 and controls memory access between the function logics 810 and 820 and the integrated memory 900.

Referring to FIG. 5, the address conversion unit 1200 includes a plurality of multiplexers 1107 through 1110, a plurality of separation registers 1101 through 1104, first and second adders 1105, 1106, and an n-bit counter. 1107. The split registers 1101 to 1104 store split values for splitting the integrated memory 910 into two memory regions 920 and 930 for each bit. Although four isolation registers 1101 to 1104 are shown in FIG. 5, the number will be determined according to the total memory capacity of the integrated memory 910.

When the address decoding logic 110 enables the multiplexers 1107-1110, PWDATA representing the separator pointer value specified by the processor 1000 is stored in the separator registers 1101-1104. In the non-enabled state, multiplexers 1107-1110 maintain the separator pointer values stored in registers 1101-1104. The separator pointer values stored in the registers 1101 to 1104 are added to the write pointer 831 by '1' by the adders 1105 and 1106 and the counter 1107 in every write operation.

Hereinafter, an operation procedure for the functional logic A 810 and the functional logic B 820 to use the integrated memory 910 will be described with reference to FIGS. 4 and 5.                     

When the functional logic B 820 operates, the address decoding logic 1100 outputs an enable signal of the separation register multiplexers 1107 through 1110. When the multiplexer enable signal is output, the split pointer value PWDATA designated by the processor 1000 is recorded in the split registers 1101 to 1104. This split pointer value is for splitting the unified memory 910. Initially, the WRITE_POINTER B 841 and READ_POINTER B 842 of the functional logic B 820 are the bottom address of the integrated memory 910, the WRITE_POINTER A 831 of the functional logic A 810, READ_POINTER A 832 is the "start address + separator pointer value".

When the separation pointer value for separating the integrated memory 910 is stored as described above, the function logic B 820 starts to operate under the control of the processor 1000, and the memory control logic B 840 performs a write operation. . Each time a write operation by the memory control logic B 840 occurs, the WRITE_POINTER B 841 is incremented by "1" starting from the "start address". This increase in WRITE_POINTER B 841 is made by adders 1105 and 1106 and counter 1107. The memory control logic B 840 also reads data from the unified memory 910 by performing a read operation. In this case, the first address port A1 port of the integrated memory 910 is connected to the WRITE_POINTER B 841, and the second address port A2 port is connected to the READ_POINTER B 842.

When a write operation of the function logic A 810 is required while the write operation and the read operation for the function logic B 820 are performed as described above, the required memory capacity of the function logic A 810 is the function logic B 820. And the operation priority of the function logic A 810 is higher than the function logic B 820, so that the processor 1000 pauses the write operation of the memory control logic B 840 and Start a write operation for logic A 810. The reason why the write operation is interrupted first is to give time for reading the contents of the second memory area 930 to the maximum.

To this end, the separate logic 835 of the memory control logic A 830 activates the internal control signal MUTUAL_CON that requires the memory control logic B 840 to write disable under the control of the processor 100. Then, the first address port of the integrated memory 910 is connected to the WRITE_POINTER A 831 instead of disconnected from the WRITE_POINTER B 841.

When data is input to the first memory area 920 of the integrated memory 910, the memory control logic A 830 performs a read operation. In this case, the READ_POINTER A 832 is connected to the second address port of the integrated memory 910 to perform a read operation of the function logic A 810. Since functional logic A 810 processes a small amount of data, the read operation of functional logic A 810 will end relatively quickly.

When the read operation of the function logic A 810 is terminated, under the control of the processor 1000, the WRITE_POINTER B 841 is connected to the first address port A1 port of the integrated memory 910 so that the function logic B 820 may be connected. The recording operation is restarted.

The read operation in the second memory area 930 is performed by the internal control signal 801 provided from the separation logic 835 after the read operation of the first memory area 920 is terminated. READ_POINTER B 842 is connected to the second address port of the unified memory 910.

6 is a flowchart illustrating an operation of simultaneously writing and reading an integrated memory according to an embodiment of the present invention.

Referring to FIG. 6, while the functional logic B 820 performs a write operation using the first address port of the integrated memory 910 and performs a read operation using the second address port (S10), If a write operation of the integrated memory 910 by the functional logic A 810 is required (S20), under the control of the memory control logic A 830, the WRITE_POINTER B 841 and the first address port of the functional logic B 820 are controlled. Instead of being disconnected (S30), the READ_POINTER A 832 of the function logic A 810 is connected to the second address port. (S40) Afterwards, the function logic A 810 performs a write operation through the second address port. (S50) When the recording operation of the function logic A 810 is completed (S60), the WRITE_POINTER B 810 is connected to the first address port again to continue the function of the function logic B 820 and the read operation. (S70)

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

In the present invention operating as described in detail above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.                     

The present invention divides the unified memory into a plurality of memory regions so that functional blocks requiring different memory capacities of the same type can share a single unified memory. Accordingly, by reducing the number of required self-diagnosis logics, the use of the memory can be made efficient, and the memory device can be miniaturized and integrated.

In addition, since the separate memory area of the integrated memory can be changed programmatically by the processor, the entire memory area can be allocated to one functional logic if necessary, and the priority of the functional logic in the case of memory access requests by multiple functional logics can be assigned. Therefore, the processing processing delay due to the use of integrated memory can be minimized by processing the request that can be processed quickly.

Claims (4)

First and second functional blocks that perform unique functions and require different memory capacities; An integrated memory shared by the first and second functional blocks and having a unique self diagnostic logic; First and second memory control logics respectively generating a write / read address signal and a write / read enable signal for causing the first and second functional blocks to use the integrated memory; A total memory area of the integrated memory divided into a first memory area usable by the first functional block and a second memory area usable by the second functional block and converted to fit into the separated memory area And a separate logic to provide a read / write address signal to the integrated memory. The memory sharing apparatus of claim 1, wherein the integrated memory has a larger memory capacity among memory capacities required by the first and second functional blocks. The method of claim 1 or 2, wherein the separation logic, A plurality of registers for storing a separation pointer value for indicating a position at which the entire memory area of the integrated memory is separated; And an adder and a counter for generating the converted write / read address signal by increasing the split pointer value by 1 each time a write / read request occurs. 4. The apparatus of claim 3, wherein the split pointer value is programmable.

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