JPS6479850A - Effective using method for bus - Google Patents

Effective using method for bus

Info

Publication number
JPS6479850A
JPS6479850A JP62236714A JP23671487A JPS6479850A JP S6479850 A JPS6479850 A JP S6479850A JP 62236714 A JP62236714 A JP 62236714A JP 23671487 A JP23671487 A JP 23671487A JP S6479850 A JPS6479850 A JP S6479850A
Authority
JP
Japan
Prior art keywords
bus
address
data
slaves
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62236714A
Other languages
Japanese (ja)
Inventor
Shunichi Nakayama
Shuji Kimura
Koichi Nara
Akira Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62236714A priority Critical patent/JPS6479850A/en
Publication of JPS6479850A publication Critical patent/JPS6479850A/en
Pending legal-status Critical Current

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE:To use plural address bus masters and slaves and the output sides of plural data buses in common time-dividedly through plural common use buses and to reduce the size of hardware by applying a control signal to output control circuits for address bus masters, address bus slaves and data buses and a bidirectional bus driver/receiver circuit. CONSTITUTION:Whether a bus practically connected between circuits is to be used as an address bus master or slave or used as a data bus can be controlled by executing the three-state control of an output control circuits 8-1, 8-2, bidirectional output control circuit 9, and the gate output of a bidirectional bus driver/receiver circuit 10 based on the value of control signals 12-15 outputted from a control circuit 11. One of the address bus masters and slaves and the data buses is selected, connected to the circuit 10 through an address/ data bus 5' and transmitted to the receiving side through an address/data bus 5. Consequently, the size of hardware can be reduced and the system can be operated only low power consumption.
JP62236714A 1987-09-21 1987-09-21 Effective using method for bus Pending JPS6479850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236714A JPS6479850A (en) 1987-09-21 1987-09-21 Effective using method for bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236714A JPS6479850A (en) 1987-09-21 1987-09-21 Effective using method for bus

Publications (1)

Publication Number Publication Date
JPS6479850A true JPS6479850A (en) 1989-03-24

Family

ID=17004682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236714A Pending JPS6479850A (en) 1987-09-21 1987-09-21 Effective using method for bus

Country Status (1)

Country Link
JP (1) JPS6479850A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287744A (en) * 1989-04-28 1990-11-27 Yokogawa Electric Corp Bus master device
JPH02311942A (en) * 1989-05-26 1990-12-27 Nec Corp Cpu external access bus system
US5582544A (en) * 1995-01-13 1996-12-10 Ely; Robert S. Adjustable air distribution apparatus
US6434646B1 (en) 1998-04-07 2002-08-13 Nec Corporation Signal distribution system and method based on bus arrangement
JP2008176790A (en) * 2007-01-18 2008-07-31 Xerox Corp Time multiplexed bidirectional bus
JP2010003040A (en) * 2008-06-19 2010-01-07 Koyo Electronics Ind Co Ltd Bus system having multiplex bus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196334A (en) * 1981-05-26 1982-12-02 Toshiba Corp Memory interface

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196334A (en) * 1981-05-26 1982-12-02 Toshiba Corp Memory interface

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287744A (en) * 1989-04-28 1990-11-27 Yokogawa Electric Corp Bus master device
JPH02311942A (en) * 1989-05-26 1990-12-27 Nec Corp Cpu external access bus system
US5582544A (en) * 1995-01-13 1996-12-10 Ely; Robert S. Adjustable air distribution apparatus
US6434646B1 (en) 1998-04-07 2002-08-13 Nec Corporation Signal distribution system and method based on bus arrangement
JP2008176790A (en) * 2007-01-18 2008-07-31 Xerox Corp Time multiplexed bidirectional bus
JP2010003040A (en) * 2008-06-19 2010-01-07 Koyo Electronics Ind Co Ltd Bus system having multiplex bus

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