JPS5759221A - Dma transfer controlling system - Google Patents

Dma transfer controlling system

Info

Publication number
JPS5759221A
JPS5759221A JP13408180A JP13408180A JPS5759221A JP S5759221 A JPS5759221 A JP S5759221A JP 13408180 A JP13408180 A JP 13408180A JP 13408180 A JP13408180 A JP 13408180A JP S5759221 A JPS5759221 A JP S5759221A
Authority
JP
Japan
Prior art keywords
bus
signal
data transfer
buses
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13408180A
Other languages
Japanese (ja)
Inventor
Shigeru Satake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13408180A priority Critical patent/JPS5759221A/en
Publication of JPS5759221A publication Critical patent/JPS5759221A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To perform data transfer with different systems smoothly by providing a signal for switching buses between processing systems A and B having independent buses. CONSTITUTION:For processing systems A and B having independent system buses 42 and 52, an input-output equipment 61 on the bus 52 uses a signal, generated by a DMA module 60, as effective one when a bus switching signal BUSCHNG is a ''1'', thereby performing data transfer with the system B to which it belongs. When the said bus switching signal is a ''0'', the signal on the bus 52 is made ineffective and an inverter 73, a bus-A-controlling circuit 72, and a driver/receiver circuit 71 operate to send the signal that the module 60 generates to the bus 42 of the system A side, so that the input-output equipment 61 performs data transfer with the processing system A. Thus the data transfer with difference systems is performed smoothly by the bus switching signal.
JP13408180A 1980-09-26 1980-09-26 Dma transfer controlling system Pending JPS5759221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13408180A JPS5759221A (en) 1980-09-26 1980-09-26 Dma transfer controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13408180A JPS5759221A (en) 1980-09-26 1980-09-26 Dma transfer controlling system

Publications (1)

Publication Number Publication Date
JPS5759221A true JPS5759221A (en) 1982-04-09

Family

ID=15119948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13408180A Pending JPS5759221A (en) 1980-09-26 1980-09-26 Dma transfer controlling system

Country Status (1)

Country Link
JP (1) JPS5759221A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151769A (en) * 1984-01-19 1985-08-09 Fujitsu Ltd Bus controlling system
JPS61110250A (en) * 1984-11-02 1986-05-28 Hitachi Ltd Data processing system provided with plural bus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151769A (en) * 1984-01-19 1985-08-09 Fujitsu Ltd Bus controlling system
JPS61110250A (en) * 1984-11-02 1986-05-28 Hitachi Ltd Data processing system provided with plural bus

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