JPS55159265A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55159265A
JPS55159265A JP6915679A JP6915679A JPS55159265A JP S55159265 A JPS55159265 A JP S55159265A JP 6915679 A JP6915679 A JP 6915679A JP 6915679 A JP6915679 A JP 6915679A JP S55159265 A JPS55159265 A JP S55159265A
Authority
JP
Japan
Prior art keywords
data processing
bus
switching
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6915679A
Other languages
Japanese (ja)
Inventor
Takashi Yura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6915679A priority Critical patent/JPS55159265A/en
Publication of JPS55159265A publication Critical patent/JPS55159265A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To reduce the switching time from the spare system to the existing system, by the paralel running of the same data processing for the spare and existing systems with the data processing circuit.
CONSTITUTION: Input circuits 1-1W1-n, output circuits 5-1W5-m are connected to the bus 1a for data reception and transmission. The bus 1a is connected to the switching circuit 6, which is connected to the data processing circuits 7-1, 7-2 and monitor circuits 4-1, 4-2 for switching control and data transfer control. When the data processing circuit 7-1 is present in the spare system and the data processing circuit 7-2 is in the existing system, 7-1 does not make output processing outputting the data to the bus 1a via the switching circuit 6, but executes the same internal processing and input processing as 7-2, and when it receives the switching signal, the switching circuit 6 switch the connection of the bus 1a to the data processing circuit 7-1.
COPYRIGHT: (C)1980,JPO&Japio
JP6915679A 1979-05-30 1979-05-30 Information processor Pending JPS55159265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6915679A JPS55159265A (en) 1979-05-30 1979-05-30 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6915679A JPS55159265A (en) 1979-05-30 1979-05-30 Information processor

Publications (1)

Publication Number Publication Date
JPS55159265A true JPS55159265A (en) 1980-12-11

Family

ID=13394526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6915679A Pending JPS55159265A (en) 1979-05-30 1979-05-30 Information processor

Country Status (1)

Country Link
JP (1) JPS55159265A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63159945A (en) * 1986-12-24 1988-07-02 Hitachi Ltd Duplex computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63159945A (en) * 1986-12-24 1988-07-02 Hitachi Ltd Duplex computer system

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