JPS54114939A - Bus scramble circuit - Google Patents

Bus scramble circuit

Info

Publication number
JPS54114939A
JPS54114939A JP2164378A JP2164378A JPS54114939A JP S54114939 A JPS54114939 A JP S54114939A JP 2164378 A JP2164378 A JP 2164378A JP 2164378 A JP2164378 A JP 2164378A JP S54114939 A JPS54114939 A JP S54114939A
Authority
JP
Japan
Prior art keywords
bus
unit
gate
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2164378A
Other languages
Japanese (ja)
Inventor
Tokumitsu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2164378A priority Critical patent/JPS54114939A/en
Publication of JPS54114939A publication Critical patent/JPS54114939A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the timing control without the timing control circuit.
CONSTITUTION: In the information processing system in which each unit is commonly connected to CPU via the bus line, the circuit provides the first FF61 set at interruption request, second FF66 set during the bus usage by the unit, first gate 63 inhibiting the output of FF61 with the signal representing that the unit itself uses the bus, delay circuit 64 compensating the output of the gate 63 for the time until the interrupt reception signal from the unit having the lowest priority among each unit connected to the bus is off, and second gate 65 inputting the output of the circuit 64, interruption reception signal from other units, and further, the signal representing the usage condition of bus, and controlling the second FF66.
COPYRIGHT: (C)1979,JPO&Japio
JP2164378A 1978-02-28 1978-02-28 Bus scramble circuit Pending JPS54114939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2164378A JPS54114939A (en) 1978-02-28 1978-02-28 Bus scramble circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2164378A JPS54114939A (en) 1978-02-28 1978-02-28 Bus scramble circuit

Publications (1)

Publication Number Publication Date
JPS54114939A true JPS54114939A (en) 1979-09-07

Family

ID=12060731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2164378A Pending JPS54114939A (en) 1978-02-28 1978-02-28 Bus scramble circuit

Country Status (1)

Country Link
JP (1) JPS54114939A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50150332A (en) * 1974-05-22 1975-12-02
JPS5195748A (en) * 1975-01-08 1976-08-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50150332A (en) * 1974-05-22 1975-12-02
JPS5195748A (en) * 1975-01-08 1976-08-21

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