JPS54114937A - Bus scramble circuit - Google Patents

Bus scramble circuit

Info

Publication number
JPS54114937A
JPS54114937A JP2164178A JP2164178A JPS54114937A JP S54114937 A JPS54114937 A JP S54114937A JP 2164178 A JP2164178 A JP 2164178A JP 2164178 A JP2164178 A JP 2164178A JP S54114937 A JPS54114937 A JP S54114937A
Authority
JP
Japan
Prior art keywords
bus
unit
gate
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2164178A
Other languages
Japanese (ja)
Inventor
Tokumitsu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2164178A priority Critical patent/JPS54114937A/en
Publication of JPS54114937A publication Critical patent/JPS54114937A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To ensure the timing control without the timing control circuit.
CONSTITUTION: In the information processing system in which each unit is commonly connected to the bus line, the circuit provides the first FF61 set at interrupt request, second FF66 set when the unit uses the bus, first gate 63 inhibiting the output of FF61 with the signal representing that the bus for other units including the said unit is used, delay circuit 64 compensating the output of the gate 63 for the time until the interruption enable signal from the unit having the lowest priority among each unit connected to the bus is off, and second gate 65 inputting the output of the delay circuit 64, interrupt enable signal from other units, and further the signal representing the usage condition of the bus, and controlling the second FF66.
COPYRIGHT: (C)1979,JPO&Japio
JP2164178A 1978-02-28 1978-02-28 Bus scramble circuit Pending JPS54114937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2164178A JPS54114937A (en) 1978-02-28 1978-02-28 Bus scramble circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2164178A JPS54114937A (en) 1978-02-28 1978-02-28 Bus scramble circuit

Publications (1)

Publication Number Publication Date
JPS54114937A true JPS54114937A (en) 1979-09-07

Family

ID=12060681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2164178A Pending JPS54114937A (en) 1978-02-28 1978-02-28 Bus scramble circuit

Country Status (1)

Country Link
JP (1) JPS54114937A (en)

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