JPS5450246A - Overrun prevention system in interrupt processing - Google Patents

Overrun prevention system in interrupt processing

Info

Publication number
JPS5450246A
JPS5450246A JP11550577A JP11550577A JPS5450246A JP S5450246 A JPS5450246 A JP S5450246A JP 11550577 A JP11550577 A JP 11550577A JP 11550577 A JP11550577 A JP 11550577A JP S5450246 A JPS5450246 A JP S5450246A
Authority
JP
Japan
Prior art keywords
interrupt
processor
signal line
overrun
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11550577A
Other languages
Japanese (ja)
Other versions
JPS5721728B2 (en
Inventor
Hiroshi Iguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11550577A priority Critical patent/JPS5450246A/en
Publication of JPS5450246A publication Critical patent/JPS5450246A/en
Publication of JPS5721728B2 publication Critical patent/JPS5721728B2/ja
Granted legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To reduce the load required for controlling a processor and prevent the overrun dependent upon interrupt by transmitting interrupt inhibition signals from higher-priority devices to lower priority devices when one processor performs in formation processing from plural devices concurrently.
CONSTITUTION: In the computer system where microprocessor 10 performs information processing from plural devices 12 and 14 whose interrupt priority levels are defined, device 12 and processor 10 are connected by interrupt signal line 20a and processing completion signal line 20b, and device 14 and processor 10 are connected by interrupt signal line 22a and processing completion signal 22b. Further, this system is so constituted that interrupt inhibition signals may be transmitted from device 12 to device 14 through signal line 24 by providing control circuit 16 in device 12, and inhibition signals are connected to signal line 22a through AND circuit 18 to inhibit the interuupt dependent upon device 14, thereby preventing the overrun of processor 10
COPYRIGHT: (C)1979,JPO&Japio
JP11550577A 1977-09-28 1977-09-28 Overrun prevention system in interrupt processing Granted JPS5450246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11550577A JPS5450246A (en) 1977-09-28 1977-09-28 Overrun prevention system in interrupt processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11550577A JPS5450246A (en) 1977-09-28 1977-09-28 Overrun prevention system in interrupt processing

Publications (2)

Publication Number Publication Date
JPS5450246A true JPS5450246A (en) 1979-04-20
JPS5721728B2 JPS5721728B2 (en) 1982-05-10

Family

ID=14664171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11550577A Granted JPS5450246A (en) 1977-09-28 1977-09-28 Overrun prevention system in interrupt processing

Country Status (1)

Country Link
JP (1) JPS5450246A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619127A (en) * 1979-07-25 1981-02-23 Fujitsu Ltd Input and output control system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0389835U (en) * 1989-12-27 1991-09-12

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50150332A (en) * 1974-05-22 1975-12-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50150332A (en) * 1974-05-22 1975-12-02

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619127A (en) * 1979-07-25 1981-02-23 Fujitsu Ltd Input and output control system

Also Published As

Publication number Publication date
JPS5721728B2 (en) 1982-05-10

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