JPS6488815A - Reset system for cpu - Google Patents

Reset system for cpu

Info

Publication number
JPS6488815A
JPS6488815A JP62246192A JP24619287A JPS6488815A JP S6488815 A JPS6488815 A JP S6488815A JP 62246192 A JP62246192 A JP 62246192A JP 24619287 A JP24619287 A JP 24619287A JP S6488815 A JPS6488815 A JP S6488815A
Authority
JP
Japan
Prior art keywords
cpu
reset
delay
keyboard
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62246192A
Other languages
Japanese (ja)
Inventor
Kazuhisa Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Intelligent Technology Co Ltd
Original Assignee
Toshiba Corp
Toshiba Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Intelligent Technology Co Ltd filed Critical Toshiba Corp
Priority to JP62246192A priority Critical patent/JPS6488815A/en
Publication of JPS6488815A publication Critical patent/JPS6488815A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reset a CPU to the initial state from an input means like a keyboard by delaying an interruption signal based on information input, and activating a delay output signal at the time of not resetting the interruption signal within the delay time. CONSTITUTION:The interruption signal is outputted from a keyboard interface 4 of a CPU main body 1 based on information input due to the operation on a keyboard 2 and is delayed in a delay circuit 7 like a monostable multivibrator by a prescribed time. When a reset signal is outputted from a CPU 3 within this delay time, the delay output of the circuit 7 is prevented from being activated. Meanwhile, when the reset signal is not outputted within the delay time, it is decided that the CPU 3 is run away, and the CPU 3 is reset to the initial state by the delay output from the circuit 7. Consequently, the CPU can be reset through the keyboard 2, and the CPU which is run away is not reset by the CPU but is reset from the external.
JP62246192A 1987-09-30 1987-09-30 Reset system for cpu Pending JPS6488815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246192A JPS6488815A (en) 1987-09-30 1987-09-30 Reset system for cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246192A JPS6488815A (en) 1987-09-30 1987-09-30 Reset system for cpu

Publications (1)

Publication Number Publication Date
JPS6488815A true JPS6488815A (en) 1989-04-03

Family

ID=17144884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246192A Pending JPS6488815A (en) 1987-09-30 1987-09-30 Reset system for cpu

Country Status (1)

Country Link
JP (1) JPS6488815A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016012199A (en) * 2014-06-27 2016-01-21 日本無線株式会社 Electronic apparatus with reset function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016012199A (en) * 2014-06-27 2016-01-21 日本無線株式会社 Electronic apparatus with reset function

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