JP2016012199A - Electronic apparatus with reset function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus with a reset function capable of easily, reliably, and safely resetting and reactivating a CPU of the electronic apparatus through simple operation.SOLUTION: An FPGA 3 comprising a key scan circuit 31 and a reset circuit 32 is externally mounted on an electronic apparatus 1, and a key panel 2 and a CPU 4 are communicatively connected. When the CPU 4 is normally operating, the FPGA 3 and the CPU 4 transmit and receive key scan information through key operation. On the other hand, if communication with the CPU 4 is not performed after the elapse of a certain time after depressing a key 21, a reset signal is transmitted from the FPGA 3 to the CPU 4 and the CPU 4 is reset by depressing a prescribed key 21A which is set in the CPU 4 in advance and stored in the FPGA 3.

Description

  The present invention relates to an electronic device with a reset function, which has a function for resetting and restarting a CPU when the electronic device freezes during operation.

  Electronic devices such as personal computers, mobile phones, and smartphones are sometimes referred to as “freezing” (“hang-up”, “stall”, “runaway”, “harden”, etc.) due to various causes. “Freeze” and so on.), It may become unresponsive to external operations and normal operations may not be possible.

  Here, in order to reset the frozen electronic device, release it from the frozen state, and return it to the normal state, for example, by turning off the power of the electronic device or removing the battery, There is a method in which the electronic device is stopped and then restarted by connecting the power source and reattaching the battery. There is also a method in which the operation state of the program is periodically monitored by a watchdog timer (WDT) of the CPU, and the reset is automatically performed when a freeze occurs.

  Further, there is a method of resetting a user by pressing a specific push button type switch such as a power key or a reset switch for a predetermined time (see, for example, Patent Documents 1 to 3).

JP 2010-267188 A JP 2008-3768 A JP 2004-140457 A

  By the way, the above conventional reset method, for example, the method of disconnecting and connecting the power source is inconvenient when the power outlet is in a place where it is difficult to remove (for example, the back of office equipment). There is a risk of losing or destroying the battery during work. In the latter case, in particular, in the case of a portable terminal equipped with a waterproof mechanism, the structure is such that the battery is difficult to be attached and detached, which further inconveniences and causes a reduction in the work efficiency of the user.

  On the other hand, with regard to the reset method using WDT, if multiple tasks such as browser, mailer, wireless control, user interface, etc. are running at the same time and freeze occurs in a task that WDT cannot monitor, WDT will function normally. Without being able to get out of the frozen state.

  Furthermore, as described above, the prior arts described in Patent Documents 1 to 3 are reset by the user pressing and holding a specific key for a certain period of time. Because it depends on the senses, it may cause malfunction. In addition, when a reset is performed using a dedicated reset key instead of an existing key, the key prevents the user from accidentally pressing the shape or installation location. Since it is necessary, it is not convenient for the user, and the installation of the key may be difficult in the first place due to the structure.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device with a reset function that can easily and reliably and safely reset and restart a CPU by a simple operation.

  In order to solve the above problems, the invention of claim 1 is an electronic device with a reset function, and relates to an operation state of the key panel by scanning the key panel in which a plurality of keys are arranged, and the key panel. An external circuit that obtains key scan information; and a CPU that operates independently of the external circuit and is connected to the external circuit so as to be able to transmit and receive, and the external circuit interrupts when the key is pressed When the CPU receives the interrupt signal, the CPU transmits a request signal for requesting acquisition of the key scan information to the external circuit, and the external circuit receives a predetermined key being pressed. A reset means is provided for resetting the CPU when the request signal is not received within a predetermined time after the interrupt signal is transmitted to the CPU.

  According to the present invention, when the electronic device is operating normally, the external circuit and the CPU transmit / receive key scan information by pressing the key. On the other hand, when the communication between the CPU and the external circuit is not performed for a predetermined time or more, the external circuit determines that the CPU is frozen. When the CPU is frozen and the pressed key is a predetermined key, the external circuit resets the CPU by reset means.

  A second aspect of the invention is the electronic device with a reset function according to the first aspect, wherein any key can be set as the predetermined key.

  According to the present invention, any existing key is preset as the reset key.

  According to the first aspect of the present invention, the CPU is reset only when communication between the external circuit and the CPU is not performed after the predetermined key as the reset key is pressed, that is, when the CPU is frozen. The On the other hand, in the normal operation state, the CPU and external circuit start communicating key scan information and the CPU is not reset, so there is no risk of malfunction due to incorrect pressing or excessive or insufficient pressing time. A reset can be performed.

  In addition, since the external circuit is physically and functionally independent from the CPU and other hardware and software, the external circuit continues to operate normally even if the CPU freezes. The CPU can be surely reset.

  Furthermore, since resetting is performed regardless of WDT, even when a large number of tasks are activated at the same time, even if a freeze occurs in a task that is not monitored by WDT, it is possible to reliably reset.

  Furthermore, since it is not necessary to turn off the power supply or remove the battery, it is possible to easily and safely perform the reset without being influenced by the installation location or the structural features of the electronic device.

  According to the second aspect of the present invention, since an existing key set in advance by the CPU during normal operation is used as a reset key, structural difficulties that are problems when using a dedicated reset key are included. And inconvenience in use is eliminated. In addition, since any key can be set as a predetermined key, the convenience is enhanced, and the user is set not to accidentally press the predetermined key, or the predetermined key is not accidentally pressed from the outside. It becomes possible to do.

It is a schematic block diagram of the periphery of the external circuit for reset of the electronic device according to the embodiment of the present invention. FIG. 2 is a task flow diagram of an external circuit in the electronic device of FIG. 1. It is a flowchart of communication operation between an external circuit and a CPU when the CPU is operating normally. It is a flowchart of the reset operation | movement of an external circuit when CPU is frozen.

  The present invention will be described below based on the illustrated embodiments.

  FIG. 1 is a block diagram of a schematic configuration around an external circuit for reset of the electronic device 1 with a reset function. The electronic device 1 with a reset function includes a key panel 2 on which a plurality of keys are arranged, an FPGA (Field Programmable Gate Array) 3 as an external circuit, and a CPU 4. The key panel 2, FPGA 3, FPGA 3, CPU 4, Are connected so that transmission and reception and data transmission are possible.

  The key panel 2 is a panel in which a plurality of keys 21 are arranged, and the pressed state of the keys 21 is scanned by the FPGA 3.

  The FPGA 3 is an integrated circuit / device on which a predetermined program is mounted, and includes a key scan circuit 31 and a reset circuit 32. The key scan circuit 31 is a circuit that scans the key panel 2 and obtains key scan information related to the pressed state of the key 21, and has the same configuration as an existing key scan circuit. That is, by scanning the key panel 2 for each column and sequentially acquiring key column data, key scan information indicating which key 21 is pressed is acquired. Such key scan information is sequentially transmitted to the CPU 4 as key string data in a key scan operation described later.

  The reset circuit 32 is a circuit that generates a reset signal (reset means) and transmits it to the CPU 4. As will be described later, when the specific key (predetermined key) 21A is pressed during the freeze state, the reset signal 32 Generate and send.

  The FPGA 3 includes a memory / circuit for storing the specific key 21A transmitted from the CPU 4. That is, the information of the reset specific key 21A sent from the CPU 4 is stored in the memory. Here, as the specific key 21A, any key 21 can be set as the specific key 21A. That is, when the electronic device with reset function 1 is operated to select and set an arbitrary key 21 as the specific key 21A for resetting, the key 21 is transmitted from the CPU 4 to the FPGA 3 as the specific key 21A. Here, in the present embodiment, the specific key 21A is a combination of a plurality of keys, and in order to transmit a reset signal, these keys are pressed simultaneously.

  The FPGA 3 has an automatic scan mode and a manual scan mode, and is normally in an automatic scan mode. When any key 21 is pressed during the automatic scan mode in a state where the CPU 4 is not frozen (normal scan operation), an interrupt signal is transmitted to the CPU 4. When the manual scan setting signal is transmitted from the CPU 4 to the FPGA 3, the FPGA 3 shifts to the manual scan mode. Thereafter, each time a request signal (key n-th column setting, n is a positive integer) is transmitted, key scan information is sequentially transmitted from the FPGA 3 to the CPU 4 to the CPU 4.

  On the other hand, when any key 21 is pressed and a request signal is not transmitted from the CPU 4 to the FPGA 3 within a predetermined time, the FPGA 3 determines that the CPU 4 is in a frozen state. When the specific key 21A is pressed simultaneously in this state, the reset circuit 32 inside the FPGA 3 transmits a reset signal to the CPU 4 to reset the CPU 4.

  The FPGA 3 automatically shifts to the automatic scan mode and transmits a reset signal when communication with the CPU 4 is not performed for a certain period of time while the key 21 is operated in the manual scan mode. The specific key 21A for scanning is scanned.

  The CPU 4 is a circuit that performs predetermined processing based on the key scan information received from the FPGA 3, that is, based on which key 21 is pressed, and is a circuit that operates independently of the FPGA 3. . Accordingly, the FPGA 3 may be activated even when the CPU 4 is not activated, and conversely, the CPU 4 may be activated even when the FPGA 3 is not activated.

  Further, the CPU 4 normally executes not only the key scan information sent from the FPGA 3 but also various tasks at the same time. However, since task processing cannot be performed in the frozen state, there is only a method for recovering from the freeze by means of restarting by a hard reset signal sent from the FPGA 3.

  Next, the operation of the electronic device 1 with a reset function, which is this configuration, will be described.

  FIG. 2 is a reset task flow of the FPGA 3.

  First, when any key 21 of the key panel 2 is pressed (step S1), the FPGA 3 receives a key scan information request signal from the CPU 4 within a predetermined time in a normal state. On the other hand, when communication is not started, it is determined that the CPU 4 is frozen (step S2).

  Next, the FPGA 3 determines whether or not the key 21 pressed in step S1 is the specific key 21A (step S3). If it is the specific key 21A, the FPGA 3 issues a reset signal to the CPU 4 to reset the CPU 4 (step S4). On the other hand, when the pressed key 21 is not the specific key 21A, the CPU 4 is not reset.

  Next, as shown in FIG. 3, when the CPU 4 is operating normally, the FPGA 3 is in the automatic scan mode when no key 21 of the key panel 2 is pressed, and the CPU 4 If no key 21 is pressed, the FPGA 3 causes the CPU 4 to generate an interrupt (interrupt signal) to another task being executed (step S5). The CPU 4 receiving the interrupt performs manual scan setting for the FPGA 3 (step S6). The FPGA 3 shifts from the automatic scan mode to the manual scan mode, performs key scan according to the read timing from the CPU 4, and transmits key scan information to the CPU 4.

  In the key scan in the manual scan mode, the CPU 4 first sets the first column of the array of the key panel 2, and transmits a request signal for the key scan information of the first column to the FPGA 3 (step S7). The set key 21 in the first column transmits / receives data to / from the CPU 4 (steps S8 and S9), and the same communication is sequentially performed up to the nth column (n is a positive integer) on the key panel 2. Repeat (Steps S10 to S12). Then, in accordance with the type / identification of the pressed key 21 based on the key scan information, predetermined processing (key pressing processing) is performed in the CPU 4. When the key panel 2 is released and the key scan information is not sent from the FPGA 3, the CPU 4 stops transmitting the key scan information request signal and sets the automatic scan mode for the FPGA 3 (step S13). Alternatively, the FPGA 3 automatically returns to the automatic scan mode when a predetermined time elapses after the CPU 4 stops transmitting the key scan information request signal.

  Next, as shown in FIG. 4, when the CPU 4 is frozen, the CPU 4 does not respond to the operation of the key 21. Therefore, even if the CPU 21 presses the key 21 and tries to interrupt (step S5), the CPU 4 No request signal is issued. On the other hand, when the pressed key 21 is the specific key 21A (step S14), the FPGA 3 performs a reset operation of transmitting a reset signal to the CPU 4 (step S15), and resets the CPU 4 (step S4).

  As described above, according to the electronic device 1 with a reset function, the CPU 4 is reset only when communication between the FPGA 3 and the CPU 4 is not performed after the predetermined key 21A is pressed. On the other hand, in the normal operation state, the FPGA 3 and the CPU 4 start transmitting / receiving the key scan information, and the CPU 4 is not reset. Therefore, there is no risk of malfunction due to wrong pressing or excessive or insufficient pressing time. A reset can be performed.

  In addition, since the FPGA 3 is physically and functionally independent from the CPU 4 and other hardware and software, the FPGA 3 continues to operate normally even if the CPU 4 freezes. The CPU 4 can be reset.

  Furthermore, since resetting is performed regardless of WDT, even when a large number of tasks are activated at the same time, even if a freeze occurs in a task that is not monitored by WDT, it is possible to reliably reset.

  Furthermore, since it is not necessary to turn off the power supply or remove the battery, it is possible to easily and safely perform the reset without being influenced by the installation location or the structural features of the electronic device.

  Also, since the existing key 21 set in advance by the CPU 4 during normal operation is used as the specific key 21A, the structural difficulties and inconveniences that were problems when using the dedicated reset key are eliminated. Is done. In addition, since the arbitrary key 21 can be set as the predetermined key 21A, the convenience is improved, and the user can set the predetermined key 21A so that the user does not press the wrong key 21A by mistake, or the predetermined key 21A is accidentally pressed from the outside. It is possible to set so as not to be performed.

  Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above embodiment, and even if there is a design change or the like without departing from the gist of the present invention, Included in the invention. For example, in the present embodiment, the external circuit is FPGA 3, but the external circuit is not limited to this, and other integrated circuits such as ASIC (Application Specific Integrated Circuit) and CSSP (Customer Specific Products) are registered trademarks. Also good.

  The key panel 2 is not necessarily limited to a mechanically pressed type such as a personal computer keyboard, a mobile phone operation button, or a power button, but may be a touch panel type key such as a tablet PC or smartphone. Of course, a combination of both may be used.

  Furthermore, the time for pressing the specific key 21A may be long as in the prior art, or may be short as in the case of normal key operation. The specific key 21A is not necessarily limited to the combination of the plurality of keys 21, and may be one. Further, even when the plurality of keys 21 are the specific keys 21A, the operation for executing the reset operation is not limited to the method of pressing all at the same time, and may be a method of pressing sequentially such as a password, for example. .

  Further, in the present embodiment, the reset means adopts a form in which the CPU 4 is reset by a reset signal. However, the present invention is not limited to this. For example, the power of the electronic device 1 with a reset function is forcibly shut down, or the FPGA 3 Another FPGA that has received the reset signal from may reset the CPU 4 or shut down the electronic device 1 with a reset function.

1 Electronic device with reset function 2 Key panel 21 Key 21A Specific key (predetermined key)
3 FPGA (external circuit)
4 CPU
S4 Reset S5 Interrupt generation (interrupt signal)
S6 Manual scan setting S7 Key first row setting (request signal)
S8 Key nth column setting (request signal)
S15 Specific key pressed (predetermined key pressed)

Claims (2)

A key panel in which multiple keys are arranged;
An external circuit that scans the key panel and obtains key scan information related to an operation state of the key panel;
A CPU that operates independently of the external circuit and is connected to the external circuit so as to be able to transmit and receive,
When the key is pressed, the external circuit transmits an interrupt signal to the CPU, and when the CPU receives the interrupt signal, the CPU transmits a request signal for requesting acquisition of the key scan information to the external circuit. And
The external circuit includes reset means for resetting the CPU when a predetermined key is pressed and the interrupt signal is transmitted to the CPU and the request signal is not received within a predetermined time.
An electronic device with a reset function. Any key can be set as the predetermined key.
The electronic device with a reset function according to claim 1.

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