JPS5690363A - Resetting system of multiple-constitution processor - Google Patents

Resetting system of multiple-constitution processor

Info

Publication number
JPS5690363A
JPS5690363A JP16858679A JP16858679A JPS5690363A JP S5690363 A JPS5690363 A JP S5690363A JP 16858679 A JP16858679 A JP 16858679A JP 16858679 A JP16858679 A JP 16858679A JP S5690363 A JPS5690363 A JP S5690363A
Authority
JP
Japan
Prior art keywords
signal
held
reset
constitution
ff12a
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16858679A
Other languages
Japanese (ja)
Other versions
JPS5832425B2 (en
Inventor
Kenichiro Miyazaki
Shigeki Furuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54168586A priority Critical patent/JPS5832425B2/en
Publication of JPS5690363A publication Critical patent/JPS5690363A/en
Publication of JPS5832425B2 publication Critical patent/JPS5832425B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To enable resetting processing easily and efficiently by the constitution that eliminates the need to pay attention to device state of other systems.
CONSTITUTION: In system A, when a resetting indication is generated, FF12A is set since signals -RST and -SLMP are both at "0". As FF12A is set, signal -ANRSTB from gate 8A is held at "0" and sent to system B. Further, FF13A is reset and signal -SLMP is held at "1". Thus, FF14A is reset and system A operates as a single system. As signal -SLMP is held at "1", FF12A is reset and signal +SLRST is held at "0", setting FF13A. At this point in time, FF14B at the side of system B has been reset already, so that the state of FF14A does not change. On receiving signal -ANRSTA of "0", the system B side operates as if the resetting indication were generated.
COPYRIGHT: (C)1981,JPO&Japio
JP54168586A 1979-12-25 1979-12-25 Reset method for multi-configuration processing equipment Expired JPS5832425B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54168586A JPS5832425B2 (en) 1979-12-25 1979-12-25 Reset method for multi-configuration processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54168586A JPS5832425B2 (en) 1979-12-25 1979-12-25 Reset method for multi-configuration processing equipment

Publications (2)

Publication Number Publication Date
JPS5690363A true JPS5690363A (en) 1981-07-22
JPS5832425B2 JPS5832425B2 (en) 1983-07-13

Family

ID=15870795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54168586A Expired JPS5832425B2 (en) 1979-12-25 1979-12-25 Reset method for multi-configuration processing equipment

Country Status (1)

Country Link
JP (1) JPS5832425B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58200315A (en) * 1982-05-14 1983-11-21 Fujitsu Ltd Diagnostic system for power source of automatic transaction system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58200315A (en) * 1982-05-14 1983-11-21 Fujitsu Ltd Diagnostic system for power source of automatic transaction system

Also Published As

Publication number Publication date
JPS5832425B2 (en) 1983-07-13

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