JPS5723132A - Acquisition system for priority right of interruption - Google Patents

Acquisition system for priority right of interruption

Info

Publication number
JPS5723132A
JPS5723132A JP9824480A JP9824480A JPS5723132A JP S5723132 A JPS5723132 A JP S5723132A JP 9824480 A JP9824480 A JP 9824480A JP 9824480 A JP9824480 A JP 9824480A JP S5723132 A JPS5723132 A JP S5723132A
Authority
JP
Japan
Prior art keywords
interruption
terminal
flop
flip
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9824480A
Other languages
Japanese (ja)
Inventor
Hiroshi Nagase
Takao Ueno
Kazuhiro Hiraide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9824480A priority Critical patent/JPS5723132A/en
Publication of JPS5723132A publication Critical patent/JPS5723132A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To prevent erroneous reception due to a conflict by permitting the processing of one of interruptions requested at the same time on preferential basis and by holding other interruption requests. CONSTITUTION:All circuits are assumed to be cleared. In this case, when an interruption request pulse is generated at the terminal of the (i)-th interruption requesting circuit, a flip-flop (FF) 5 is set via an interruption request line 12. When an interruption priority acquisition bus 4 is not making an interruption request display ''1'', a signal line 11 is at a ''0'' and the output of the FF5 sets a flip-flop 2 via an inhibition gate 1. Further, the output of the FF2 drives a bus driver 3 to make the interruption priority acquisition bus 4 make an interruption display. Once a terminal Si acquires the priority right of interruption, other interruption requesting terminals are inhibited from making interruptions, so a processor processes the interruption of the terminal Si.
JP9824480A 1980-07-18 1980-07-18 Acquisition system for priority right of interruption Pending JPS5723132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9824480A JPS5723132A (en) 1980-07-18 1980-07-18 Acquisition system for priority right of interruption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9824480A JPS5723132A (en) 1980-07-18 1980-07-18 Acquisition system for priority right of interruption

Publications (1)

Publication Number Publication Date
JPS5723132A true JPS5723132A (en) 1982-02-06

Family

ID=14214539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9824480A Pending JPS5723132A (en) 1980-07-18 1980-07-18 Acquisition system for priority right of interruption

Country Status (1)

Country Link
JP (1) JPS5723132A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113885A2 (en) * 1982-12-17 1984-07-25 Siemens Aktiengesellschaft Circuit arrangement for a data transmitting-receiving device
EP0114485A2 (en) * 1982-12-21 1984-08-01 Texas Instruments Incorporated Communications system and device therefor employing control line minimization
US4908749A (en) * 1985-11-15 1990-03-13 Data General Corporation System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113885A2 (en) * 1982-12-17 1984-07-25 Siemens Aktiengesellschaft Circuit arrangement for a data transmitting-receiving device
EP0114485A2 (en) * 1982-12-21 1984-08-01 Texas Instruments Incorporated Communications system and device therefor employing control line minimization
US4908749A (en) * 1985-11-15 1990-03-13 Data General Corporation System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal

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