JPS5534522A - Time sheaking multiple control system - Google Patents

Time sheaking multiple control system

Info

Publication number
JPS5534522A
JPS5534522A JP10650278A JP10650278A JPS5534522A JP S5534522 A JPS5534522 A JP S5534522A JP 10650278 A JP10650278 A JP 10650278A JP 10650278 A JP10650278 A JP 10650278A JP S5534522 A JPS5534522 A JP S5534522A
Authority
JP
Japan
Prior art keywords
signal
terminal
time
transmission
slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10650278A
Other languages
Japanese (ja)
Other versions
JPS5851461B2 (en
Inventor
Noriaki Fujimura
Kazuo Matsuoka
Tsuneo Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53106502A priority Critical patent/JPS5851461B2/en
Publication of JPS5534522A publication Critical patent/JPS5534522A/en
Publication of JPS5851461B2 publication Critical patent/JPS5851461B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1629—Format building algorithm

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To ensure a high-efficiency multiplication as well as to secure an easy decision at the reception side for the slot allotment process at the transmission side for the time shearing multiple control system with which the idle time and slot are allotted when the transmission requests are given from terminal circuits of different transmission velocities. CONSTITUTION:The time slot on the circuit forms one frame shown in A and then allots previously slot T0 to channel CH0 like CH1 against the terminal of 50BPS like B. For the terminal of 100BPS, T0 and Tn plus T1 and Tn+1 are allotted to CH0 and CH1 respectively. In case the data transmission requests are given at one time from several units of terminal circuits, the request from only one terminal is made effective based on the expected priority sequency with other requests put under the holding state. The indication signal is provided to the idle CH, and the idle CH allotted by occurrence of the transmission signal request receives the transmission start indication signal (one signal row) instead of the idle state signal (zero signal row). Thus the reception side recognizes the allotment state based on the signal change.
JP53106502A 1978-08-31 1978-08-31 Time division multiplex control method Expired JPS5851461B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53106502A JPS5851461B2 (en) 1978-08-31 1978-08-31 Time division multiplex control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53106502A JPS5851461B2 (en) 1978-08-31 1978-08-31 Time division multiplex control method

Publications (2)

Publication Number Publication Date
JPS5534522A true JPS5534522A (en) 1980-03-11
JPS5851461B2 JPS5851461B2 (en) 1983-11-16

Family

ID=14435201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53106502A Expired JPS5851461B2 (en) 1978-08-31 1978-08-31 Time division multiplex control method

Country Status (1)

Country Link
JP (1) JPS5851461B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189493U (en) * 1983-05-30 1984-12-15 三菱電機株式会社 pulse drive circuit
JPS6060813U (en) * 1983-09-29 1985-04-27 松下電工株式会社 Ceiling recessed lighting fixtures
JP2017505031A (en) * 2013-12-28 2017-02-09 インテル コーポレイション Dynamic interconnect using partitioning and platform prototyping in emulation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516406A (en) * 1974-07-04 1976-01-20 Fujitsu Ltd
JPS5119405A (en) * 1974-08-09 1976-02-16 Nippon Electric Co

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516406A (en) * 1974-07-04 1976-01-20 Fujitsu Ltd
JPS5119405A (en) * 1974-08-09 1976-02-16 Nippon Electric Co

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189493U (en) * 1983-05-30 1984-12-15 三菱電機株式会社 pulse drive circuit
JPS646000Y2 (en) * 1983-05-30 1989-02-15
JPS6060813U (en) * 1983-09-29 1985-04-27 松下電工株式会社 Ceiling recessed lighting fixtures
JPS6343765Y2 (en) * 1983-09-29 1988-11-15
JP2017505031A (en) * 2013-12-28 2017-02-09 インテル コーポレイション Dynamic interconnect using partitioning and platform prototyping in emulation

Also Published As

Publication number Publication date
JPS5851461B2 (en) 1983-11-16

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