JPS57109026A - Bus controlling system - Google Patents

Bus controlling system

Info

Publication number
JPS57109026A
JPS57109026A JP18690480A JP18690480A JPS57109026A JP S57109026 A JPS57109026 A JP S57109026A JP 18690480 A JP18690480 A JP 18690480A JP 18690480 A JP18690480 A JP 18690480A JP S57109026 A JPS57109026 A JP S57109026A
Authority
JP
Japan
Prior art keywords
signal
time
circuit
detecting
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18690480A
Other languages
Japanese (ja)
Other versions
JPS607307B2 (en
Inventor
Tomohito Shibata
Shigeru Hashimoto
Masaaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18690480A priority Critical patent/JPS607307B2/en
Publication of JPS57109026A publication Critical patent/JPS57109026A/en
Publication of JPS607307B2 publication Critical patent/JPS607307B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To improve the processing efficiency of a processing system by giving priority to a bus access request from an I/O side over that from a CPU side when both the access requests conflict with each other and the access request the I/O side arrived in prescribed time. CONSTITUTION:When an address request signal (c) is set in a register 4 at time t1, a deteting circuit 7 detects that to generate an acceptance signal at time t2 and also trigger a delay circuit 8. On the other, an access request signal is sent from an I/O control register 11 at time t3 and then set in a register 9. Then, even when detecting the signal (a), a detecting circuit 12 holds the transmission of the acceptance signal (h). An output signal (g) is generated by the circuit 8 at time t4 prescribed time after the time t2, and sent to a detecting circuit 10. On detecting the signals (f) and (a) at the time t4, the circuit 10 sends a detection signal D. This signal D controls the circuits to stop the signal (f) and to generate the signal (h) of the circuit 12 at time t6, thereby permitting the I/O side to use a bus.
JP18690480A 1980-12-26 1980-12-26 Bus control method Expired JPS607307B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18690480A JPS607307B2 (en) 1980-12-26 1980-12-26 Bus control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18690480A JPS607307B2 (en) 1980-12-26 1980-12-26 Bus control method

Publications (2)

Publication Number Publication Date
JPS57109026A true JPS57109026A (en) 1982-07-07
JPS607307B2 JPS607307B2 (en) 1985-02-23

Family

ID=16196711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18690480A Expired JPS607307B2 (en) 1980-12-26 1980-12-26 Bus control method

Country Status (1)

Country Link
JP (1) JPS607307B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0192838A2 (en) * 1985-02-28 1986-09-03 International Business Machines Corporation Bus arbiter for a data processing system having an input/output channel
JPS62146735A (en) * 1985-12-21 1987-06-30 Toyota Motor Corp Drive output control method for vehicle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0192838A2 (en) * 1985-02-28 1986-09-03 International Business Machines Corporation Bus arbiter for a data processing system having an input/output channel
JPS62146735A (en) * 1985-12-21 1987-06-30 Toyota Motor Corp Drive output control method for vehicle

Also Published As

Publication number Publication date
JPS607307B2 (en) 1985-02-23

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