JPS54133847A - Control system of memory unit - Google Patents

Control system of memory unit

Info

Publication number
JPS54133847A
JPS54133847A JP4139678A JP4139678A JPS54133847A JP S54133847 A JPS54133847 A JP S54133847A JP 4139678 A JP4139678 A JP 4139678A JP 4139678 A JP4139678 A JP 4139678A JP S54133847 A JPS54133847 A JP S54133847A
Authority
JP
Japan
Prior art keywords
memory
actuated
access request
timing
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4139678A
Other languages
Japanese (ja)
Other versions
JPS6143741B2 (en
Inventor
Yoshio Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4139678A priority Critical patent/JPS54133847A/en
Publication of JPS54133847A publication Critical patent/JPS54133847A/en
Publication of JPS6143741B2 publication Critical patent/JPS6143741B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To constitute an economical memory system and also to make memory achieve overlap operation effectively, by providing two timing generating circuits to several memory modules. CONSTITUTION:Now, two continuous memory-access requests (a1) and (a2) are supposed to be sent from processor 4 to memory unit 6. In control circuit 7, there are two timing circuits TC1 and TC2 provided. When access request (a1) is made, TC1 is actuated with both TC1 and TC2 idle. When the other access request (a2) is made in process of access request (a1), TC2 is actuated if memory module 8 is not the same, and the timing is not actuated newly if the same. It is a matter of course that when TC1 and TC2 are both busy, the timing is never actuated even if any access request is made. A time interval between (a1) and (a2) is shorter than a memory cycle time for processing (a1).
JP4139678A 1978-04-08 1978-04-08 Control system of memory unit Granted JPS54133847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4139678A JPS54133847A (en) 1978-04-08 1978-04-08 Control system of memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4139678A JPS54133847A (en) 1978-04-08 1978-04-08 Control system of memory unit

Publications (2)

Publication Number Publication Date
JPS54133847A true JPS54133847A (en) 1979-10-17
JPS6143741B2 JPS6143741B2 (en) 1986-09-29

Family

ID=12607209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4139678A Granted JPS54133847A (en) 1978-04-08 1978-04-08 Control system of memory unit

Country Status (1)

Country Link
JP (1) JPS54133847A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59134975U (en) * 1983-02-28 1984-09-08 日本電気ホームエレクトロニクス株式会社 Display control circuit for television teletext receiver
JPS60217443A (en) * 1984-04-12 1985-10-31 Nec Corp Storage control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59134975U (en) * 1983-02-28 1984-09-08 日本電気ホームエレクトロニクス株式会社 Display control circuit for television teletext receiver
JPS60217443A (en) * 1984-04-12 1985-10-31 Nec Corp Storage control system
JPH0368420B2 (en) * 1984-04-12 1991-10-28 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6143741B2 (en) 1986-09-29

Similar Documents

Publication Publication Date Title
JPS5454540A (en) Data buscontrol system
JPS56114063A (en) Multiprocessor
JPS54133847A (en) Control system of memory unit
KR830010423A (en) Data exchange method of data processing system
JPS5295939A (en) Common contrl device for input/output
JPS55121521A (en) Data bus control system
JPS5336149A (en) Information processing system
JPS5798194A (en) Storage device
JPS56135266A (en) Data processing system
JPS5759220A (en) Data transfer system
JPS56163581A (en) Memory refreshing system
JPS5534522A (en) Time sheaking multiple control system
JPS5434728A (en) Input/output control system
JPS57109026A (en) Bus controlling system
JPS5346243A (en) Processor control system
JPS52120731A (en) Refresh control circuit
JPS5469923A (en) Memory shared device
JPS5339022A (en) Information process unit
JPS6476254A (en) Device for arbitrating bus
JPS54124939A (en) Memory-unit refresh control system
JPS5744278A (en) Selecting system of memory module
JPS57176463A (en) Data processor
JPS56110126A (en) Data transfer system
JPS57105056A (en) Register control system
JPS6488616A (en) Clock switch control system