JPS5469923A - Memory shared device - Google Patents

Memory shared device

Info

Publication number
JPS5469923A
JPS5469923A JP13693177A JP13693177A JPS5469923A JP S5469923 A JPS5469923 A JP S5469923A JP 13693177 A JP13693177 A JP 13693177A JP 13693177 A JP13693177 A JP 13693177A JP S5469923 A JPS5469923 A JP S5469923A
Authority
JP
Japan
Prior art keywords
flag register
address
memory controller
signal
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13693177A
Other languages
Japanese (ja)
Inventor
Seigo Oida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13693177A priority Critical patent/JPS5469923A/en
Publication of JPS5469923A publication Critical patent/JPS5469923A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the contention of access requests among a plural number of processor only by providing a simple flag register.
CONSTITUTION: When processor 1 sends out an access request and an address to be accessed to memory controller 4 at the same time, memory controller 4 detects what memory module among M1 to Mn the address belongs to, and checks the contents of flag register 10 which corresponds to the address. If not flag register 10 is set, that means no access from any other processor, so that the signal will be sent back as an accessible signal to memory controller 4 via bus 11 at the same time when the flag register is set. By the signal from flag register 10, memory controller 4 sends out a control timing pulse, address signal, write data, etc., to the memory module via bus 5.
COPYRIGHT: (C)1979,JPO&Japio
JP13693177A 1977-11-15 1977-11-15 Memory shared device Pending JPS5469923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13693177A JPS5469923A (en) 1977-11-15 1977-11-15 Memory shared device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13693177A JPS5469923A (en) 1977-11-15 1977-11-15 Memory shared device

Publications (1)

Publication Number Publication Date
JPS5469923A true JPS5469923A (en) 1979-06-05

Family

ID=15186895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13693177A Pending JPS5469923A (en) 1977-11-15 1977-11-15 Memory shared device

Country Status (1)

Country Link
JP (1) JPS5469923A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0683700A (en) * 1991-12-30 1994-03-25 Gold Star Co Ltd Apparatus and method for controlling memory access of multiprocessor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0683700A (en) * 1991-12-30 1994-03-25 Gold Star Co Ltd Apparatus and method for controlling memory access of multiprocessor system

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