JPS57105056A - Register control system - Google Patents

Register control system

Info

Publication number
JPS57105056A
JPS57105056A JP55181322A JP18132280A JPS57105056A JP S57105056 A JPS57105056 A JP S57105056A JP 55181322 A JP55181322 A JP 55181322A JP 18132280 A JP18132280 A JP 18132280A JP S57105056 A JPS57105056 A JP S57105056A
Authority
JP
Japan
Prior art keywords
reset
register
bit
request signal
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55181322A
Other languages
Japanese (ja)
Inventor
Noboru Yamaguchi
Norio Aihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55181322A priority Critical patent/JPS57105056A/en
Publication of JPS57105056A publication Critical patent/JPS57105056A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To reset only the processed bit, by using the JK type FFs to plural registers connected to a memory bus to set or reset the register by a CPU with every bit. CONSTITUTION:Registers 101 and 102 of JK type FF which can be set or reset are connected to a memory bus 2 led from a memory access device 1. At the same time, a module 15 which is not synchronous with the device 1 and can set or reset the registers 101 and 102 is provided, and the contents of the register 101 or 102 to which a bit is set by a request signal given from the module 15 (picture recording control device) is read by the device 1 via a read data bus. A desired data process is carried out by the device 1 to the above-mentioned request signal. Thereafter, the register 101 or 102 which is reset via an address bus 3 is designated. Then only the bit that is set by the request signal of the register 101 or 102 is reset based on a table of truth of the JK type FF. Thus a process request is processed in an assured way.
JP55181322A 1980-12-23 1980-12-23 Register control system Pending JPS57105056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55181322A JPS57105056A (en) 1980-12-23 1980-12-23 Register control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55181322A JPS57105056A (en) 1980-12-23 1980-12-23 Register control system

Publications (1)

Publication Number Publication Date
JPS57105056A true JPS57105056A (en) 1982-06-30

Family

ID=16098650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55181322A Pending JPS57105056A (en) 1980-12-23 1980-12-23 Register control system

Country Status (1)

Country Link
JP (1) JPS57105056A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104831A (en) * 1976-02-28 1977-09-02 Shimadzu Corp Offering multiplex device with preferential level
JPS5354433A (en) * 1976-10-28 1978-05-17 Fujitsu Ltd Register setting system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104831A (en) * 1976-02-28 1977-09-02 Shimadzu Corp Offering multiplex device with preferential level
JPS5354433A (en) * 1976-10-28 1978-05-17 Fujitsu Ltd Register setting system

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