JPS57127259A - System for high-speed data transfer - Google Patents

System for high-speed data transfer

Info

Publication number
JPS57127259A
JPS57127259A JP1081981A JP1081981A JPS57127259A JP S57127259 A JPS57127259 A JP S57127259A JP 1081981 A JP1081981 A JP 1081981A JP 1081981 A JP1081981 A JP 1081981A JP S57127259 A JPS57127259 A JP S57127259A
Authority
JP
Japan
Prior art keywords
reply
data
memory module
outputs
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1081981A
Other languages
Japanese (ja)
Inventor
Naoki Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Denki Seizo KK
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Denki Seizo KK
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Denki Seizo KK, Toyo Electric Manufacturing Ltd filed Critical Toyo Denki Seizo KK
Priority to JP1081981A priority Critical patent/JPS57127259A/en
Publication of JPS57127259A publication Critical patent/JPS57127259A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To execute the data transfer in the two-fold speed faster than the conventional speed and transfer data surely with a reply control circuit, by performing one read operation in a CPU module to transfer data. CONSTITUTION:When a CPU module 1' performs the read operation in prescribed addresses of a memory module 21' and a memory module 22', the memory module 21' outputs data to a data line 4' synchronously with a read control signal 6' and outputs a reply signal 81 to a reply control circuit 9. Simultaneously, the memory module 22' takes in data, which is outputted from the memory module 21', through the data line 4' synchronously with the read control signal 6' and outputs a reply signal 82 to the reply control circuit 9. The reply control circuit 9 to which reply signals 81 and 82 are outputted outputs a reply signal 8' to the CPU module 1'.
JP1081981A 1981-01-29 1981-01-29 System for high-speed data transfer Pending JPS57127259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1081981A JPS57127259A (en) 1981-01-29 1981-01-29 System for high-speed data transfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1081981A JPS57127259A (en) 1981-01-29 1981-01-29 System for high-speed data transfer

Publications (1)

Publication Number Publication Date
JPS57127259A true JPS57127259A (en) 1982-08-07

Family

ID=11760957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1081981A Pending JPS57127259A (en) 1981-01-29 1981-01-29 System for high-speed data transfer

Country Status (1)

Country Link
JP (1) JPS57127259A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814260A (en) * 1981-07-17 1983-01-27 Fujitsu Ltd Data transfer system
JPS6235950A (en) * 1985-08-09 1987-02-16 Casio Comput Co Ltd Inter-memory data transfer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814260A (en) * 1981-07-17 1983-01-27 Fujitsu Ltd Data transfer system
JPS6316779B2 (en) * 1981-07-17 1988-04-11 Fujitsu Ltd
JPS6235950A (en) * 1985-08-09 1987-02-16 Casio Comput Co Ltd Inter-memory data transfer system

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