JPS6235950A - Inter-memory data transfer system - Google Patents

Abstract

PURPOSE:To transfer a large quantity of data between memories directly at a high speed by supplying a NOP code to the CPU side in the data transfer mode. CONSTITUTION:Various devices (a ROM 2 and RAMs 1 and 2) are coupled to a CPU 1 through a system data bus SDB. A data bus switch/NOP generating part 5 is provided with a tri-state buffer, which is used to disconnect the CPU 1 from the bus SDB when the direction of the bidirectional system data bus SDB is controlled and data is transferred at a high speed, and a NOP generating part which supplies the NOP code to the CPU side in the disconnection state. An address bus AB is connected to a device selecting logic part of a control signal control part 6. The address bus AB is connected to other various devices, and the address of the address bus is given from an address counter of the CPU 1 through the AB output.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a data transfer method between memories.

[Prior Art and Problems] Generally, in the case of program transfer, a CPU transfers data by once reading data from a memory and then writing the data to another memory. However, this transfer method requires about 10 instructions to be executed, which takes a very long time (especially when transferring a large amount of data).

To solve this problem, a direct memory access method using a DMA (direct memory access) controller is used. Although this method enables high-speed transfer, the DMA controller itself requires logic such as a small CPU, so various devices (typically
address register, counter register, control register,
(status registers, etc.), the configuration is complex, and the cost is high.

[Purpose of the Invention] Therefore, the present invention provides a transfer method that can transfer a large amount of data between memories with a simple configuration and at high speed (a method using a DMA controller) without using a DMA controller. The purpose is to

[Summary of the Invention] This invention focuses on the fact that when the CPU reads a NOP (NO0PERATION) code, the CPU increments (increments/decrements) an internal address counter. an address counter provided in the CPU; a means for disconnecting the system data bus from the CPU and supplying a NOP code to the CPU;
The gist of the present invention is to have means for controlling the writing side memory and the reading side memory to write and read states, respectively, while the address counter incremented by the NOP judgment in U holds the same address. It is something.

[Embodiment] FIG. 1 is a block diagram of a minimum-medium embodiment using the present invention. 1 is a CPU, and 11 is an address counter provided in the CPU, which generates an address to be specified according to a program. 2 is a ROM (basic memory) that stores programs for CPU operation, and 3 and 4 are RA
The MI and RAM 2 store calculation results by the CPU, various data (input via an input device not shown), programs, and the like.

Normally, various devices (here ROM2 and R
AMI and RAM2) are coupled to the CPU via a system data bus SDR.

5 is a data bus switch/NOP generation unit, which controls the direction of the bidirectional system data bus SDB as described later;
and a 3-state buffer for isolating the CPU from the system SDR (which is done during high-speed data transfers in this embodiment) and a NOP in the disconnected state.
It has a NOP generation section that supplies code to the CPU side.

Reference numeral 6 denotes a control signal control section to which an address bus AB is coupled to a device selection logic section. The address bus hB is
Other various devices include RAMI, RAM2,
It is connected to ROM, and the address on the address bus is C.
It is given via the AB small output from the address counter of the PUI.

Various control signals are coupled between devices, and for the sake of explanation, the illustrated control signals will be listed and their meanings explained.

C31: RAMI selection signal. The control signal is sent to the control signal controller 6 from the CPUI. Normally, it is at high level, and when data is transferred using RAMI as a read-side memory, it becomes low level (active state to enable data transfer).

CS2: R, AM2 selection signal. The following is the same as CSt.

INT: Control signal controller 6 at the end of data transfer
A signal that interrupts the CPU. When an interrupt signal (low level) is generated, the CPU returns to normal operation.

RD: Read signal output by the CPU (active at low level). Sent to devices 5 and 6.

WR: Write signal issued by the CPU (active at low level). Sent to devices 5 and 6.

R/W1. From device 6, the first memory is RAM.
Read/write signal supplied to I (write at low level, read at high level).

R/W2: Second memory from device 6, here RMA2
read/write signals provided to The following is the same as R/Wl.

MGSI: Memory selection signal supplied to RAMI from device 6 (enabled at low level).

MC52: Memory selection signal supplied from device 6 to RAM2.

C5ROM: Memory selection signal sent from device 6 to ROM2.

C: Data transfer signal. CPU to redata path switch/
This is a signal input to the Nor generating section 6, which is at a high level in the data transfer mode, and the data bus switch /No? Generate a NOP code from the generator. Usually low level.

Next, the data bus switch/NOP generating section 5 will be described in detail with reference to FIG. As shown, data bus switch/No? The generation unit 5 includes two 3-state buffers 5
1 and 52. The 3-state buffer 51 is a switch for controlling data reading from a peripheral device to the CPU 1, and becomes conductive when the RD double signal (low level) is inputted through the OR gate 54 during reading during program transfer from the CPU 1. Also 3 state buffer 52
is a switch that controls data transfer from the CPU to peripheral devices, and when writing in program transfer by the CPU, the WR multiplied signal (low level) is inputted via the OR gate 53 and becomes conductive (switched on). but,
In the high-speed data transfer mode according to this embodiment, since the high-level C signal is applied to the second input of the two-operated OR gates 53 and 54, both switches, that is, the three-state buffer, are 51 and 52 are in an open state (output impedance is high), and the CPUI is separated from the system data bus SDR.

55 is a Nor generation section, which is connected to the data bus D on the CPUI side.
It is combined with BI, and in high-speed data transfer, the CPU
It supplies a NOP code to I. Here, N
The OP generating section 55 has a configuration in which each line of the data bus DBI is connected via a resistor (a so-called pull-down configuration). Therefore, in the high-speed data transfer mode in which both switches constituted by the 3-state buffers 51 and 52 are open, the NOP generator 55 inputs all "0" (OOH) (7):l to the input data bus DB11-. - code is generated and provided to the CPUI. In this case, the OOH code becomes a NOP code for the CPUI. Depending on the CPU model, other patterns such as al
l Some use “l” (IIH) as a NOP code. In that case, the NOP generating section 55 may be configured to generate that pattern. For example, C.P.
If the UI uses 11H as the NOP code,
Make it a pull-up configuration.

Next, the control signal controller 6 will be described in detail with reference to FIG. Reference numeral 66 denotes a memory selection logic unit, which is comprised of an address decoder that decodes a part of the address from the address bus AB to generate a memory selection signal. The memory (device) selection logic section is generally an element used by the CPU in a microcomputer to select one peripheral memory (device) when transferring a program.壬) 1 field 16 chome 41 tsusaiban 1 arrival field 1. Deis h
It is t ten.

67 (END Ad) is for storing the final address of high-speed data transfer, and when the final address is generated on the address bus, the comparator 68 outputs an INT output (low level) indicating the completion of high-speed data transfer.

AND gate 65 is coupled with the C32 signal from the CPUI and the AC32 signal from address decoder 66, and its output signal MC52 is applied to the chip select input (active at low level) of RAM2. Similarly, the C3I signal from the CPLTI and the AC3I signal from the address decoder 66 are input to the AND gate 64, and its output signal MC3I is applied to the chip selection input of the RAMI. O
The R gate 63 receives the C52 signal and the HD multiplied signal from the CPUI, and its output is added to the second signal of the AND gate 62 which uses the WR multiplied signal from the CPUI as the first signal. The output signal of AND gate 62 is applied to the read/write input of RAM2. Similarly, the OR gate 61
The C3I signal from I and the RD multiplied signal are input, and the output is the WR multiplied signal from the CPUI.
The output of AND gate 62 is applied to the read/write input of RAMI.

The C3I signal and C32 signal from the CPUI are signals used for high-speed data transfer.
Do not use (as memory selection signal). That is, it is normally fixed at a high level, and the CPU selects the memory mainly via the address bus AB and the address decoder 66. For example, when selecting RAM2, the address decoder outputs a low-level RAM2 selection signal AC3.
2 is output, which passes through gate 65 (negative logic OR gate) to select RAM2 (MC82 signal is at low level). How to use the C81 and C32 signals in the high-speed data transfer mode will be explained in the following operational description.

The operation of high-speed data transfer will be explained below. For convenience, it is assumed that data is transferred from RAM1 to RAM2, and the explanation will be given with reference to FIGS. 4, 5, and other figures.

First, in step 100, the selection signal C92 is enabled (set to low level) for RAM2 (FIG. 1), which is the memory on the data receiving side (that is, the writing side). is sent and RAM2 is chip-enabled (Fig. 3, Fig. 1,
Figure 5). However, the CSI signal remains at high level. In step 101, the data transfer control signal C is enabled "H" to disconnect the CPU from the system data bus SDR.
A NOP code is generated (see Figure 2). Next, CP
The UI jumps to the start address of the data transfer (address within the RAMI area, which is the memory on the data sending side) (step 102). This allows address bus A B
This address is generated at -l2, a portion of which is sent to address decoder 66 (FIG. 3), which is the memory selection logic. Therefore, the selection signal AC3I of RAMI becomes enabled "L" and is passed through the gate 64 to the data transmitting side (
RAMJ, which is a memory on the read side), is chip-enabled. Here, the memories on the data sending side and the receiving side, RAMI and RAM2, are in the selected state, and the same address is input to the address input of each memory (addressing is done by the same address). ), a NOP code appears on the data bus DBI on the CPUI side. Here, the CPU outputs an RD double signal in an attempt to read the OF code (operation code). However, what is actually read is not OP Kotsu but N
It is an or code. Therefore, the CPUI does not execute anything, and the address counter is incremented at the next clock φ and moves to the next address. On the other hand, due to the generation of the RD double signal (low level), this signal is input as a write signal (low level signal) to the write/read input terminal R/W2 of RAM2 via the gate 63.62 of device 6. , RAM2 is in data input state r car; input Jl'
ffl)L”, trS-*f=RAM 1
tT+婁; input/u output/input terminal R/Wl is at high level (
Since the C5I signal remains at "°H', the WR signal 11H"), the data output state (read state) is reached. For this reason,
Data is output from the storage location in RAMI specified by the start address, and the data is output from the storage location in RAMI specified by the start address.
The data is transferred directly to the storage location in M2, and one piece of data is transferred. After this, CPUI does the same and NOPs
The code is read, only the address is counted up, and data is transferred from RAMI to RAM2 every time the RD clock signal is generated. Eventually, the address on the address bus AB is transferred to the final address storage section 67 (third
If it matches the address data in the figure) (data transfer complete)
, the comparator 68 inputs the interrupt signal INT to the CPUI. As a result, the CPU 1 restores the connection between the CPU 1 and the system bus by returning the C82 signal to high level (step 104) and returning the data transfer signal C to low level (step 105), and sets the address to ROMZ.
(step 106), the predetermined address of ROM2 is outputted onto the address bus, and the minus address is decoded via the address decoder 66 to output the C5ROM signal, which is output to the RO.
M2 is chip-enabled and the remaining lower address specifies a predetermined storage location within the ROMZ. Therefore, the operation code is extracted from the same storage location in the ROM 2 and output onto the system data bus. The CPU outputs the RD multiplied signal (step 107).
This operation code is read (108) and normal operation is resumed. In normal program transfer, the CPU
I selects a memory and specifies a storage location within the selected memory via the address bus and address decoder 66;
From the WR double signal, the memory read/write signal R/W,
R/Wl is controlled (WR-R/W1=R/W2
:See Figure 3).

When performing high-speed, direct data transfer from RAM2 to RAMI, it is sufficient to do the opposite of the transfer from RAM1 to RAM2.

In addition, in the first embodiment described in 1, RA is used as the first memory.
Although RAM2 is used as the MI as the second memory, the present invention is not limited to this, and for example, a ROM may be used as the first memory (in this case, there is no need to change the configuration shown in FIG. 3 at all. (It is always just the memory of the data sender).

Further, a third memory may be added as a memory to which data is directly transferred. In this case, a means for generating the C33 signal is provided on the CPU 1 side, the signal line is connected to the control signal controller, and the control signal controller 6 side is provided with a means for generating the C33 signal.
The address decoder circuit is provided with means for decoding the address signal to generate an AC33 signal, and the R/W3
．． A circuit for generating 14C93 signals (i.e. ACS
It is only necessary to add an AND gate that connects RD and C33 and outputs MC33, an OR gate that connects RD and C33, and an AND gate that connects the output of this OR gate with WR and outputs R/W3. Similarly, even if an arbitrary number of memories are added, it can be easily handled by adding the same means as above, and this can be easily handled by adding the same number of memories as above. High speed by invention,
It is possible to perform direct data transfer.

FIG. 6 shows the configuration of a control signal controller 6' used in a second embodiment of the invention.

- I- Product temperature The difference from the embodiment 1 (Figures 1 to 5) is that the selection signal C3I selects the memory to be used in the data transfer mode and distinguishes between the receiving side memory and the transmitting side memory. The reason is that the Dl and D2 signals are used as control signals.

Among the control signals supplied from the CPU 1 to the control signal control unit 6', C3I, CS2. A table showing the logic levels of D1 and D2 is shown below (the logic levels of other control signals are the same as in the first embodiment).

In FIG. 6, 6A is a NAND gate and when the data transfer signal is "HII" and the D1 signal is "H", its output II L
(OR game) 6C is enabled in II, and the read signal RD (or the CLOCK signal synchronized with this) is passed.

The signal passed in this way is the direct write signal nw of the first memory.
It is supplied to AND gate 62 as it. 2nd memory direct write credit nWR 9th grade) I: Good quality shout T
Since it is the same as that of Inagitsuji in '5WT) 1, the explanation of its configuration will be omitted. In short, in the circuit of FIG. 6, during the direct data transfer mode, the read/write signal R/Wl of the first memory is
is directly controlled by the write signal DWRl (R/W1=D
W R1), the read/write signal R/W2 of the second memory is directly controlled by the write signal DWR2 (R/W1=DW
R2). Similarly, during the direct data transfer mode, the first memory selection signal MC5I is controlled only by the selection signal C81 (
MC31=CS 1), similarly MC32=C52.

On the other hand, in the normal mode, R/Wl and R/W2 cannot be controlled by the write signal WR (W R= R/W1= R/W2
), MC5I, and MC32 are respectively controlled by selection signals AC31 and AC32 output from the address decoder 6' (MC5l=AC51, MC52=ACS2).

For example, from the first memory (RAMI) to the second memory (RAMI)
When transferring data directly to M2), C3I “L”
", CS2 ' is specified as "L", so MC31"L
", MCS 2 '"L becomes 11, RAMI and R
Both AM2 are chip enabled. Also, D2 is H
” (because it is related to the reception memory RAM2), and DI remains at tt L 11. As a result, the timing at which the transfer control signal changes from “L” to “H” (data transfer start timing ), RD or CLOC
The K signal passes through gate 6D and further passes through gate 62 to control writing into RAM2, which is a receiving memory. On the other hand, D
Since WRl is “H11,” the first memory is R/Wl.
is placed in the read state at "H".

The subsequent execution of data transfer is the same as that described in the operation of the first embodiment.

When the address on the address bus AB (the address output from the address counter in the CPUI) exceeds the area of RAM2 (or RAMI) (data transfer is completed),
The address decoder 66' outputs an active "L" interrupt signal INT (because the address range in which INT is generated is a range different from the address range for selecting any memory (memory unused range)). Thereafter, the same recovery process as explained in connection with FIG.
, and the lead designation of D2.)

This second embodiment also has expandability like the first embodiment,
Additional memories such as third and fourth memories can be used.

Finally, in the first and second embodiments, a type of memory in which writing/reading is controlled by one terminal (R/W) is used as the RAM 1.2, but this is not limited to this. The present invention can also be applied to a type of memory in which readout is carried out through separate terminals, and the necessary modifications therefor are within the scope of those skilled in the art.

[Effects of the Invention] As is clear from the above description, according to the present invention, the address is incremented each time the 1-1 CPUI reads a NOP code so that the NOP code is supplied to the CPU 1 side in the data transfer mode. While the counter holds the same address, the memory on the read side is in the data transmission state, and the memory on the write side is in the memo 1) k7' - evening reception state, so between the memories (RAMMRAM, RAM card 4 -
Conventional DMA, which can directly and quickly transfer large amounts of data (ThRAM, ROM-+RAM, etc.), has a simple configuration, and requires small CPU-level logic.
There is no need for anything like a controller.

[Brief explanation of drawings]

FIG. 1 is an overall configuration block diagram showing a first embodiment of the present invention, and FIG. 2 is a data bus switch/N. Figure 3 is a diagram of the configuration of the P generation section, Figure 3 is a diagram of the configuration of the control signal controller, Figure 4 is a flowchart of data transfer, Figure 5 is a timing chart of data transfer, and Figure 6 is a control used in the second embodiment. FIG. 3 is a configuration diagram of a signal control section. ■...CPU, 2...ROM, 3.
...RAM1.4...RAM2.5...
...Data bus switch/NOP generation section, 6.6'
...Control signal control section.

Claims (1)

[Claims] means for selecting memory on the read side and memory on the write side, an address counter provided in the CPU, and a CPU
Disconnect the system data bus and write the NOP code to C.
means for supplying the data to the PU, and means for controlling the memory on the write side and the memory on the read side to write and read states, respectively, while the address counter, which is incremented by a NOP judgment in the CPU, holds the same address. An inter-memory data transfer method characterized by comprising: