JPH01166152A - Program storage control system - Google Patents

Abstract

PURPOSE:To simplify the circuit structure of a program storage control system and to reduce cost by using an existing program counter also for an initial program transfer. CONSTITUTION:In a time t1, when a load start signal LOADs becomes on, a clear signal is impressed on the clear terminal (CLR) of muPC 21a through an inverter 23a and the muPC 21a is cleared and its output muADD is made into '0'. The LOADs is impressed also on a ROM control part 32 and the ROM control part 32 outputs a load enable signal LOADE. This LOADE disables a decoder 4 through an inverter 25a, is impressed on an OR gate 24a and becomes a signal to generate a write enable signal WE of a SRAM 1a. The muPC 21a outputs muADD=0 to the SRAM 1a and a ROM 31 by a clock CLK impressed on a clock terminal CP and thus, microprogram data muDATA of an address 0 of the ROM 31 are impressed on the SRAM 1a. On the other hand, a clock CLK Is impressed on an OR gate 24, the write enable signal WE is generated and the muDATA are stored into the SRAM 1a.

Description

[Detailed Description of the Invention] [Summary] Regarding a storage control system that initially transfers a program from an external memory to an internal memory, the purpose is to simplify the circuit configuration. A program storage control system that includes a program control unit having a counter that specifies a memory address, and an external memory that is provided outside these units and stores the program, and that transfers the program in the external memory to the internal memory at an initial stage, A counter in the program control unit is shared as an address counter for the internal memory and the external memory only during the initial program transfer,
The configuration is such that the initial program transfer is performed.

[Industrial application field]

The present invention relates to a program storage control system that once transfers a program stored in an external memory to an internal memory upon startup and then performs control processing based on the transferred program.

A central processor of a control system using a computer, such as an automatic switching system, has an internal memory that stores programs and data and is used directly for control processing, such as a static RAM, as well as an external memory that stores programs to be operated in the internal memory. A memory, for example a ROM, is provided. There are various reasons for providing external memory, some of which will be described below. The first reason is to respond quickly and safely to changes in the processing content of the central processor. If the processing content of the central processor is changed, debug it in advance with the changed processing content using another computer, and then run the program after debugging is completed.
Store it in OM. R of external memory on the central processor side
Replace the OM with the ROM after debugging, reboot, and transfer the contents of the replaced ROM to the internal memory.

Thereby, on the central processor side, the program whose processing has been changed after debugging is completed can be operated with the shortest downtime. The second reason is that when volatile memory is used as internal memory that requires high-speed operation, if the contents of the internal memory are destroyed due to power outage, etc., when restarting from non-volatile or battery-backed external memory, Used to back up internal memory by retransferring programs.

[Conventional technology]

FIG. 4 shows the configuration of a control system for storing microprograms as an example of a conventional program storage control system.

ROM that stores microprograms as external memory
3a, a static RAM 1a is provided as an internal memory. At initialization or restart, the program in ROM3a is sent to SR in response to the load start signal LOAD.
An address counter 5a is provided for transfer to AM la. Microprograms are sequentially transferred from the ROM 3a to the RAM 1a as data μDAT. During this time, the output of the microprogram counter 21a in the microprogram control unit 2a is prohibited, and the decoder 4a is rendered inoperable.

After the initial microprogram transfer, the output of the address counter 5a is prohibited, and the microprogram in the SRAM 1a is read out using the address from the microprogram counter 21a, decoded by the decoder 4a, and used for control processing.

[Problem that the invention seeks to solve]

The microprogram control unit 2a has SRA during normal operation.
A microprogram counter 21a is provided for addressing M1a, but its output is prohibited and is not used during initial program transfer. On the other hand, an address counter 5a for initial program transfer is provided separately. For this reason, there is a waste in that the microprogram counter 21a is not used at the time of initial program transfer, and there are problems in that the address counter 5a is provided separately, which makes the circuit configuration complicated and expensive.

Furthermore, the RAM 1a has a micro program counter 21a.
Since the address of the address counter 5a and the address of the address counter 5a must be selectively accepted, the circuit becomes complicated.

In view of the above-mentioned problems, it is an object of the present invention to make effective use of existing counters, simplify the circuit configuration, and ultimately reduce the cost.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the program storage control system of the present invention.

In FIG. 1, a program control section 2 having a program counter 21, an internal memory 1, and an external memory 3 are connected as shown. A conventional address counter is provided, and a program counter 21 is provided in the internal memory 1.
and is connected to external memory 3. The program counter 21 is used both during initial program transfer and during normal operation.

[Function] At initial startup or restart, a program load signal is applied to the program counter 21 and the external memory 3.

``Thus, the program counter 21 is set to the initial address for initial program loading. Decoder 4 is rendered inactive.

The external memory 3 outputs the program at the address given by the program counter 21 as data to the internal memory 1, and the internal memory 1 stores the program data from the external memory at the address given from the program counter 21. The program counter 21 sequentially updates addresses in response to the application of the clock CK. As a result, the program data in the external memory 3 is sequentially stored in the internal memory 1. The above program transfer continues until the program counter 21 overflows.

When the program counter 21 overflows, output of program data from the external memory 3 is prohibited and the decoder 4 becomes operational. From this point on, the process shifts to normal program control.

As described above, by using the existing program counter 21 for initial program transfer, the circuit configuration can be simplified and the cost can be reduced.

(Embodiment) As an embodiment of the present invention, a microprogram storage control system will be described with reference to FIG.

In FIG. 2, a microprogram control section 2a is provided as the program control section 2, a static RAM 1a is provided as the internal memory 1, and a ROM memory 3'' is provided as the external memory 3.

The microprogram control @2a has a microprogram counter (ttPC) 21a, an AND gate 22a, an inverter 23a, an OR gate 24a, and an inverter 25a. ROM memory 3
' is the ROM31 that stores the microprogram and this R
It consists of a control section 32 of the OM. The microprogram address (μADD) output from μPC21a is SRA
A common voltage is applied to M1a and ROM 31 via buses 51 and 52, respectively. Microprogram data (u DATA) is transferred from ROM31 to SRAM1a via bus 5.
4.53.

The operation of the circuit of FIG. 2 will be described with reference to the timing diagrams of FIGS. 3(a) to (h).

At time t1, load start signal LOADs (third
(b)) is turned on, a clear signal is applied to the clear terminal (CLR) of μPC21a via the inverter 23a, clearing μPC21a and setting its output μADD to "0" (Figure 3(d)). ). LOADs is also applied to the ROM control unit 32, and the ROM control unit 32 outputs a load enable signal LOADE (FIG. 3(b)). This LOADt disables the decoder 4 via the inverter 25a, and also disables the decoder 4 through the inverter 25a.
The write enable signal WE of SRAM la is applied to
It becomes a signal of occurrence. The μPC21a sets μADD=O to S by the clock CLK applied to the clock terminal CP.
By outputting to RAM Ia and ROM 31 (
3(d)), the microprogram data μDATA at address 0 of the ROM 31 is applied to the SRAM la (FIG. 3(e)). On the other hand, the clock CLK is applied to the OR gate 24a, and the write enable signal WE (third
((to)) is generated, and μDATA is stored in the SRAM 1a (FIG. 3(f)).

Time t2. After t3, the μPC 21a is updated by 1 each time the clock CLK is applied, and μDATA is transferred from the ROM 31 to the SRAM 1a for the sequentially updated μADD.

At time tn, when the μPC 21a overflows, an overflow output signal (
Figure 3 (h)) shows the load terminals LD and A of μPC21a.
It is output to the ND gate 22a and the ROM control section 32. As a result, the ROM control unit 32 sets the load enable signal LOADE to the "high" level and the μ from the ROM 31 is
In addition to inhibiting the output of DATA, the OR gate 124a for generating an initial load enable is also inhibited, and the decoder 4 is enabled (operating state). μPC21a
On the side, the initial address ADD,,l, for normal operation is AN
It is loaded via the D gate 22a. Below, μPC2
The microprogram transferred to the SRAM 1a based on the μADD from 1a is decoded by the decoder 4 to perform control processing.

In the above embodiment, the initial microprogram transfer is from the initial address = 0 until the counter (μPC) 21a overflows, but it is also possible to transfer the initial microprogram from any initial address to any end address. .

Although the SRAM 1a is illustrated as the internal memory 1, a dynamic RAM or other semiconductor memory can be used. On the other hand, although the case where the ROM 31 is used as the external memory 3 has been exemplified, a battery-backed RAM or the like may be used. Various types of internal memory 1 and external memory 3 can be used as long as the transfer time is within the clock cycle range.

Incidentally, although the above has been exemplified with respect to the transfer of a microprogram, the present invention is not limited to microprograms, and can also be applied to ordinary program codes.

〔Effect of the invention〕

As described above, according to the present invention, the circuit configuration of the program storage control system can be simplified by using an existing program counter for initial program transfer. Accordingly, the cost of the program storage control system can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a program storage control system of the present invention, FIG. 2 is a configuration diagram of a microprogram storage control system as an embodiment of the present invention, and FIGS. Figure 4 is an operational timing diagram of the system. Figure 4 is a configuration diagram of a conventional microprogram storage control system. (Explanation of symbols) ■・・・・・・Internal memory, 1a・・・Static RAM, 2・・・・・・
...Program control unit, 2a...Micro program control unit, 3...External memory, 4.4a...Decoder, 5a...Address counter, 21...Program counter, 21a.
......Micro program counter, 31.
・・・・・・ROM. 32...120M controller. Mouth\Slap

Claims (1)

[Claims] 1. An internal memory (1) that stores a program, a program control unit (2) that has a counter that specifies the address of the internal memory, and an external memory that is provided outside these and stores the program. (3) In a program storage control system that transfers a program in an external memory to an internal memory at an initial time, a counter in the program control section is set to a counter in the internal memory and the external memory only at the time of the initial program transfer. A program storage control system, characterized in that it is configured to be used commonly as an address counter to perform the initial program transfer. 2. The program storage control system according to claim 1, wherein the program transferred to the internal memory is a microprogram, and the counter is a microprogram counter. 3. The program storage control system according to claim 1 or 2, wherein the internal memory is a volatile memory and the external memory is a replaceable nonvolatile memory. 4. The program storage according to any one of claims 1 to 3, wherein the initial program transfer is performed sequentially and continuously from an initial value set in the counter until the counter overflows. control system.