JPS63117396A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To temporarily interrupt a writing on the way of the writing and to read data from an EEPROM by providing a writing timing generating circuit for stopping the generation of a timing signal according to an external writing interrupting signal, an auxiliary address latch and an auxiliary data latch. CONSTITUTION:According to a writing start signal 7 from a CPU6, a non- volatile semiconductor memory device (EEPROM) is brought into a writing state and when the writing interrupting signal 14 is inputted to the writing timing generating circuit 2 from the CPU6, an operating is stopped, a timer 3 is cleared, a writing interrupting flag 13 is set and the EEPROM1 can be made access. At that time, the address of a first address latch 4 and the data of a first data latch 5 are respectively saved to a second address latch 11 and a second data latch 12. After the writing is interrupted, when an address different from an address before the interruption is read, at the time of sending a reading address to the first address latch 4, the data of the EEPROM 1 of the address is sent to the first data latch 5 and the CPU6 can read the data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an electrically rewritable non-volatile semiconductor memory device (hereinafter referred to as EEFROM), and particularly to a control method for interrupting and resuming erasure and writing thereof. It is related to circuits.

[Conventional technology]

Because writing to EEPROM takes several milliseconds due to its structure, complicated timing signals are required to control the writing.Recently, the mainstream method has been to generate the timing signal for writing inside the EEPROM. ing.

FIG. 2 shows a conventional EEPROM with a built-in circuit that generates write timing. In the figure, 1 indicates EE
PROM memory, 2 is a write timing generation circuit, 3
is a timer to measure the time (several milliseconds) required for writing to this EEPROM, 4 is an address latch for storing the write address, 5 is a data latch for storing the data to be written, and 6 is an external control. Circuit (hereinafter referred to as C
PU), 7 is a write start signal, 8 is a write end signal from the timer 3 to the write timing generation circuit, 9 is an address signal from the CPU 6 to the address latch 4, and 10 is a data signal from the CPU 6 to the data latch 5. It is.

Next, the operation will be explained.

When trying to write data to EEFROMI, CP
U6 confirms that the write timing generation circuit 2 is not in the write state. Next, the cpU 6 stores the address and data to be written into the respective address latches 4. The CPU 6 sends the data to the data latch 5 to be stored therein, and further sends a write start signal 7 to the write timing generation circuit 2 and the timer 3 to start writing. When writing is started, the EEPROM I side operates independently of the CPU 6, and the CPU 6 performs other work.

When the time required for writing (several milliseconds) has elapsed, the timer 3 sends a write end signal 8 to the timing generation circuit 2, thereby causing the write timing generation circuit to stop its operation and the writing to be completed.

[Problem that the invention seeks to solve]

Since the write control circuit of the conventional EEFROM structure is constructed as described above, there is a problem in that once the EEPROM starts writing, the EEPROM cannot be accessed at all until the writing is completed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an EEPROM in which writing to the EEPROM can be interrupted and writing that has been interrupted can be restarted.

[Means for solving problems]

The EEFROM according to the present invention includes a write timing generation circuit that generates a timing signal for a write operation in response to an external write start signal, and stops the generation of the timing signal in response to an external write interrupt signal; An auxiliary address launch and an auxiliary data latch are provided for temporarily saving data in the address latch and main data latch.

[Effect]

In this invention, since a write timing generation circuit that stops the generation of the timing signal in response to an external write interrupt signal and an auxiliary address latch and an auxiliary data latch that launch addresses and data when writing is interrupted are provided, writing cannot be interrupted. Also, interrupted writing can be resumed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a nonvolatile semiconductor memory device according to an embodiment of the present invention, in which 1 indicates an EEPROM memory cell;
2 is a write timing generation circuit, 3 is a timer, 4 is a first address latch (main address latch), 5 is a first data latch (main data latch), 6 is an external control circuit (
7 is a write start signal, 8 is a write end signal, 9 is a first address signal, and 10 is a first data signal, which correspond to 1 to 10 in FIG. 2, respectively. Further, 11 is a second address latch (auxiliary address launch) that latches the address before the write is interrupted, 12 is the second data latch (auxiliary data latch) that latches the data before the write is interrupted, and 13 is the write interrupt signal 14. A write interrupt flag 14 is sent from the CPU 6 to the write timing generating circuit 2. A write interrupt signal is input to the timer 3 and the write interrupt flag 13, 15 is the second address signal from the second address latch 11 to the first address latch 4, and 16 is the second address signal from the second data latch 12 to the first address latch 4.
The second data signal 17 to the data latch 5 is a delay circuit for delaying the start of writing when restarting.

Next, the operation will be explained.

1l ゛The EEPRO is activated by the write start signal 7 from the CPU 6.
M is in a write state, and in this state, when the write interrupt signal 14 is input from the CPU 6 to the write timing generation circuit 2, the operation is stopped. At this time, the timer 3 is cleared and the write interrupt flags 1-3 is sent, and EEPROM1 becomes accessible. At this time, the address of the first address latch 4 and the data of the first data latch 5 are respectively transferred to the second address latch 11.
and is saved to the second data latch 12. In this state, any address can be read as before. For example, when reading an address different from the address before the interruption after writing is interrupted, if the read address is sent to the first address latch 4 through the address signal 9, the data in the EEPROMI at that address is transferred to the first data latch 5.
The CPU 6 can read the data.

Next, the operation of restarting the interrupted writing will be explained. When the write start signal 7 is sent from the CPU 6 to the write timing generation circuit 2 again, if the write interruption flag 13 is set, the address before the write interruption is sent to the first address latch 4 through the second address signal 15. A signal is sent from the second address latch 11. Similarly, the data before writing is interrupted is sent from the second data latch 12 to the first data latch 5 through the data signal 16. On the other hand, a write start signal 18 delayed by a delay circuit 17 is inputted to the write timing generation circuit 2 and the timer 3K by a time period in which the rewrite address and data are determined. Furthermore, the write interruption flag 13 is reset at the same time as rewriting is started.

In this way, this embodiment is provided with a write timing generation circuit that stops the generation of the timing signal in response to an external write interrupt signal, and an auxiliary address latch and an auxiliary data latch that latch the address and data when writing is interrupted. In the middle of the process, writing can be temporarily interrupted and data can be read from the EEFROM.
Additionally, interrupted writing can be resumed immediately.

In the above embodiment, the auxiliary address latch 11° and the auxiliary data latch 12 are provided, but these are
When reading EPROMI, the first address latch 4.
If the first data raft 5 is not used, it may not be provided.

Furthermore, in the above embodiment, the case where the EEPROMI and CPUB are separate chips has been explained;
In the case of a microcomputer in which the OMI and the CPU 6 are configured on the same chip, the same effect as in the above embodiment can be obtained.

Further, in the above embodiment, the delay circuit 17 is provided, but this is a conventional circuit in which the write timing generation circuit 2 and the timer 3 start operating after the write start signal 7 is input to the EEPROMI. If a delay occurs until then, the delay circuit 17 may not be provided.

Further, in the above embodiment, the case of writing has been described, but this may also be the case of erasing, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a write timing generation circuit that stops generation of a timing signal in response to an external write interrupt signal, and an auxiliary address latch and an auxiliary data latch that respectively latch addresses and data when a write is interrupted. Since this is provided, data can be read from the EEPROM by temporarily interrupting writing in the middle of writing, and the interrupted writing can be resumed immediately.

[Brief explanation of the drawing]

FIG. 1 is an EEPRO diagram according to an embodiment of the present invention, in which 2 is a write timing generation circuit, 3 is a timer, and 4 is a write timing generation circuit.
．． 11 is the first. 2nd address launch, 5.12 is 1st
．． Second data latch, 13 is write interrupt flag, 1
4 is a write interrupt signal, and 17 is a delay circuit °h3. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a nonvolatile semiconductor memory device that has a built-in circuit for writing data into memory using an external signal, a main address latch and a main data latch each latch the write address and data input from the outside, and the above when writing is interrupted. An auxiliary address latch and an auxiliary data latch are used to temporarily save the address of the main address latch and the data of the main data latch, and the auxiliary address latch and auxiliary data latch are used to receive a write start signal from an external source and generate a timing signal for a write operation, and to perform a write operation from an external source. A nonvolatile semiconductor memory device comprising: a write timing generation circuit that stops generation of the timing signal in response to an interruption signal.