JPH0140433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a read/write control device for a random access memory (RAM), and more particularly to a data write control device used in a system having a data retention mode.

[Technical background of the invention]

Generally, write control in a RAM read/write device is performed at the timing shown in FIG. First, the address data on the address bus is latched at time _t0 , then the chip select signal of the RAM chip goes low at time _t1 , then the write enable signal goes low at time _t2 , and then at time _t3. The data on the data bus when the signal goes high is written. That is, when the signal and the signal are in the low level state, the RAM cell at the address specified by the address data fixed on the address bus is fixed on the data bus by the time the signal goes from low level to high level. This is the data that is written. Pulse width of the above write enable signal
tw is determined by the operating frequency of the system in which the RAM and the read/write control device are used, and as the operating frequency decreases, the pulse width tw (write time) increases.

[Problems with background technology]

By the way, in a system that has an operation mode (data retention mode) that retains the previous data when the operating power is turned off or when the power supply voltage drops below a specified value, the low level of the write enable signal It is possible that the device may enter data retention mode when in this case,
Since the write gate of the RAM cell is opened by the WE signal, the reliability on the data bus is low when entering data retention mode, and data that should not be retained may be written and retained by mistake. In this case, as mentioned above, as the operating frequency of the system decreases and the pulse width tw of the signal becomes longer, the probability of entering data retention mode when this signal is low level increases, causing incorrect data to be written and retained. The fear becomes stronger.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
To provide a data write control device for a random access memory, which can prevent as much as possible the possibility of writing and holding incorrect data when entering a data holding mode, and can hold correct data.

[Summary of the invention]

That is, the RAM data write control device of the present invention generates a write enable signal having a pulse width necessary and sufficient for data writing to the RAM, latches write data at the leading edge of this signal, and
The feature is that this latch data is written.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In the microcomputer shown in Figure 2,
1 is a CPU (central processing unit), and a common bus 2
It sends address data and write data to the common bus 2, takes in read data from the common bus 2, sends a read signal to the read control line 3, and sends a write signal to the write control line 4, and these operations are performed at predetermined timings. Let's do it. Address latch circuit 5 latches address data on address bus 6 connected to common bus 2 at a predetermined timing. In the read-only memory (ROM) 7, data at an address specified by address data provided from the address latch circuit 5 via the address bus 8 is read out onto a data bus 9 connected to the common bus 2. A data latch circuit 10 latches write data on the common bus 2 in response to a write signal from the write control line 4. The first buffer circuit 11 receives the latch data (write data) of the data latch circuit 10 and outputs the write data to the data bus 12 when a write enable signal 'to be described later is input to an output enable input terminal.

On the other hand, a monostable multivibrator 13, for example, is used as a write enable signal generating circuit, and when the write signal is input, it generates a write enable signal' having a predetermined width tw' synchronized with the trailing edge. Reference numeral 14 denotes a two-input OR gate into which the write enable signal' and the read signal are input, and its OR output is input to the chip enable input terminal of the RAM 15 as a chip select signal'. This RAM
15, address data is applied from the address latch circuit 5 via the data bus 16, the write enable signal' is applied to the read/write control input terminal R/W, and the data input/output terminal is connected via the data bus 12. The first buffer circuit 1
1 and the input side of the second buffer circuit 17. This second buffer circuit 1
7 outputs the read data on the data bus 12 read from the RAM 15 to the data bus 18 connected to the common bus 2 when the read signal is input to the output enable input terminal.

Next, the write mode and read mode operations of the RAM in the microcomputer having the above configuration will be explained with reference to FIGS. 3 and 4.

FIG. 3 shows the timing of data and signals in a write operation to RAM. First, the time
After the address data is determined at t ₀ , it is latched by the address latch circuit 5 and applied to the RAM 15 . Next, a write signal is generated at time _t1 , and at the trailing edge (time _t2 ), the write data on the common bus 2 is latched into the data latch circuit 10. Also,
A write enable signal is generated by the monostable multivibrator 13 in synchronization with the trailing edge of the above write signal.
WE' is generated, and this ' signal becomes the write control input of the RAM 15. In this case, the pulse width tw of the 'signal' is set to a value necessary and sufficient for writing data to the RAM 15, and is greater than the pulse width tw of the write signal (corresponding to the write enable signal in the conventional example). It's small. Then, at the leading edge of the ' signal, the latch data (write data) of the data latch circuit 10 is output from the first buffer circuit 11 to the data bus 12. Further, the 'signal' passes through the OR gate 14 and becomes a chip select signal ', which becomes a chip enable control input for the RAM 15. Therefore,
At the trailing edge of write enable signal ′ (time t ₃ )
The operation of writing write data to the RAM 15 is completed.

FIG. 4 shows the timing of data and signals in the data read operation of the RAM. First of all,
After the address data is determined at time _t0 , it is latched by the address latch circuit 5. Next, a read signal is generated at time _t1 , and this signal passes through the OR gate 14 and becomes the chip select signal'.
This is the chip enable control input for RAM15.
As a result, the data at the currently specified address in the RAM 15 is read out to the data bus 12 and then transferred to the data bus 1 through the second buffer circuit 17.
8 is output.

According to the RAM write control described above, a constant pulse width that is necessary and sufficient to write data to the RAM is synchronized with the trailing edge of the write signal.
It forms the write enable signal of tw′ and this
The latched write data is written at the leading edge timing of the WE' signal. Therefore, even if the microcomputer has a data retention mode as described above, its operating frequency is low, and the pulse width tw of the write signal is large, the pulse width tw' of the write enable signal ' By setting it to a constant value that is always smaller than the above tw, the probability of entering data retention mode during the period of this pulse width tw' (write time) is lowered, so there is a risk of writing and retaining incorrect data. will be prevented as much as possible, making it possible to maintain correct data.

Note that the present invention is also applicable to the RAM of a one-chip microcomputer.

〔Effect of the invention〕

As described above, according to the data write control device for a random access memory of the present invention, it is possible to prevent as much as possible the possibility of writing and holding incorrect data when entering the data holding mode, and it is possible to hold correct data.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the operation timing of a conventional RAM in write mode, and FIG. 2 is a diagram showing the operation timing in the write mode of a conventional RAM.
FIGS. 3 and 4 are explanatory diagrams showing an embodiment of a RAM data write control device, and are diagrams showing operation timings of the device shown in FIG. 2 in write mode and read mode, respectively. 1...CPU, 10...Data latch circuit, 1
2... Buffer circuit, 13... Monostable multivibrator.

Claims (1)

[Claims] 1. In a data write control device for a random access memory having a data retention mode, a control means for sending out address data and write data to be applied to the random access memory and sending out a write signal when the random access memory is in the write mode; A data latch circuit that latches the write data at the trailing edge of the write signal sent from the control means, and a data latch circuit that is necessary and sufficient for data writing operation to the random access memory in synchronization with the trailing edge of the write signal sent from the control means. a write enable signal generating circuit which generates a write enable signal ' having a constant pulse width tw' and supplies it as a write control input to the random access memory; A data write control device for a random access memory, comprising: a buffer circuit for inputting write data to a random access memory, and configured to reduce the probability of entering a data holding mode during writing by the write enable signal.