JPS61245255A - Nonvolatile memory device - Google Patents

Nonvolatile memory device

Info

Publication number
JPS61245255A
JPS61245255A JP8679785A JP8679785A JPS61245255A JP S61245255 A JPS61245255 A JP S61245255A JP 8679785 A JP8679785 A JP 8679785A JP 8679785 A JP8679785 A JP 8679785A JP S61245255 A JPS61245255 A JP S61245255A
Authority
JP
Japan
Prior art keywords
circuit
control
writing
latch
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8679785A
Inventor
Hideo Nakamura
Terumi Sawase
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8679785A priority Critical patent/JPS61245255A/en
Priority claimed from US06/854,889 external-priority patent/US4744062A/en
Publication of JPS61245255A publication Critical patent/JPS61245255A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To facilitate an interface with a microcomputer for pipeline control by connecting a delay means which delays only the control signal for erasion and writing to a temporary latch means which latches temporarily the control signal supplied to a control means.
CONSTITUTION: The control signals are supplied to an EEPROM control circuit 6 as well as a control latch 1. THe output of the circuit 1 is supplied to the circuit 6 via a delay circuit 7. The data are given to a data latch 3 via a tri- state data buffer 2 which is controlled by the control signal given from the circuit 6. The circuit 7 keeps the delay time which can perform the normal reading operation between the latch timing of the signal needed for writing and the writing start timing. Thus the reading processing is possible immediately after the writing signal.
COPYRIGHT: (C)1986,JPO&Japio
JP8679785A 1985-04-23 1985-04-23 Nonvolatile memory device Pending JPS61245255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8679785A JPS61245255A (en) 1985-04-23 1985-04-23 Nonvolatile memory device

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP8679785A JPS61245255A (en) 1985-04-23 1985-04-23 Nonvolatile memory device
US06/854,889 US4744062A (en) 1985-04-23 1986-04-23 Semiconductor integrated circuit with nonvolatile memory
US07/174,975 US4821240A (en) 1985-04-23 1988-03-29 Semiconductor integrated circuit with nonvolatile memory
US07/329,515 US4920518A (en) 1985-04-23 1989-03-28 Semiconductor integrated circuit with nonvolatile memory
US07/501,542 US4974208A (en) 1985-04-23 1990-03-30 Microcomputer incorporating a nonvolatile semiconductor memory

Publications (1)

Publication Number Publication Date
JPS61245255A true JPS61245255A (en) 1986-10-31

Family

ID=13896778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8679785A Pending JPS61245255A (en) 1985-04-23 1985-04-23 Nonvolatile memory device

Country Status (1)

Country Link
JP (1) JPS61245255A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528039A (en) * 1991-07-22 1993-02-05 Melco:Kk Storage device
US6351787B2 (en) 1993-03-11 2002-02-26 Hitachi, Ltd. File memory device and information processing apparatus using the same
US6931467B2 (en) 1995-10-19 2005-08-16 Rambus Inc. Memory integrated circuit device which samples data upon detection of a strobe signal
US7320082B2 (en) 1997-10-10 2008-01-15 Rambus Inc. Power control system for synchronous memory device
US8923433B2 (en) 1997-06-20 2014-12-30 Massachusetts Institute Of Technology Digital transmitter

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528039A (en) * 1991-07-22 1993-02-05 Melco:Kk Storage device
US6351787B2 (en) 1993-03-11 2002-02-26 Hitachi, Ltd. File memory device and information processing apparatus using the same
US6662264B2 (en) 1993-03-11 2003-12-09 Hitachi, Ltd. File memory device and information processing apparatus using the same
US6952752B2 (en) 1993-03-11 2005-10-04 Hitachi, Ltd. File memory device and information processing apparatus using the same
US6931467B2 (en) 1995-10-19 2005-08-16 Rambus Inc. Memory integrated circuit device which samples data upon detection of a strobe signal
US7287109B2 (en) 1995-10-19 2007-10-23 Rambus Inc. Method of controlling a memory device having a memory core
US9647857B2 (en) 1997-06-20 2017-05-09 Massachusetts Institute Of Technology Digital transmitter
US9419824B2 (en) 1997-06-20 2016-08-16 Massachusetts Institute Of Technology Digital transmitter
US8989303B2 (en) 1997-06-20 2015-03-24 Massachusetts Institute Of Technology Digital transmitter
US8923433B2 (en) 1997-06-20 2014-12-30 Massachusetts Institute Of Technology Digital transmitter
US7986584B2 (en) 1997-10-10 2011-07-26 Rambus Inc. Memory device having multiple power modes
US7626880B2 (en) 1997-10-10 2009-12-01 Rambus Inc. Memory device having a read pipeline and a delay locked loop
US7320082B2 (en) 1997-10-10 2008-01-15 Rambus Inc. Power control system for synchronous memory device

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