JPH09146767A - Method for reloading program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time from the completion of program loading up to its execution in a computer system provided with a non-volatile memory capable of electrically reloading a program to be executed by a CPU and storing the program and RAM loaded with the program stored in the non-volatile memory. SOLUTION: When a program to be stored in a flash EEPROM 13 is loaded from an external system 2 to a 1st RAM 14, control is transferred to the program loaded to the RAM 14. During the execution of the program stored in the RAM 14, the contents of the RAM 14 are copied to the EEPROM 13 by using the idle time of a CPU 11, and after the completion of the copying, control is transferred to the EEPROM 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program rewriting method in a computer system in which a program executed by a CPU is stored in an electrically rewritable non-volatile memory such as an EEPROM or a flash EEPROM.

[0002]

2. Description of the Related Art A computer system in which a program executed by a CPU is stored in an electrically rewritable non-volatile memory such as a flash EEPROM has been conventionally proposed. In this way, by storing the program executed by the CPU in the electrically rewritable nonvolatile memory, it is possible to eliminate the inconvenience that occurs when the program is stored in the RAM or the ROM. That is, when the program is stored in the RAM, there is a problem that the program must be externally loaded into the RAM every time the system is started up. When the program is stored in the ROM, it is difficult to rewrite the program. However, such a problem can be solved by using an electrically rewritable nonvolatile memory.

By the way, in a computer system in which a program executed by a CPU is stored in an electrically rewritable non-volatile memory, rewriting of the program has conventionally been performed as follows.

First, the operation of the computer system is interrupted, and then the rewriting program is loaded from the external system to the RAM in the computer system. Next, the nonvolatile memory is collectively erased, and after the erase is completed, R
The rewriting program loaded in the AM is stored in the non-volatile memory. Here, it is the flash EEPROM that loads the rewriting program into the RAM once and then stores the rewriting program in the nonvolatile memory.
This is because the writing speed of such a non-volatile memory is very slow and it is difficult to directly write to the non-volatile memory. After that, the control is transferred to the program stored in the non-volatile memory, and the operation of the computer system is restarted (for example, JP-A-3-150651).

[0005]

As described above, conventionally, the rewriting program loaded from external system to the RAM is written in the nonvolatile memory having a very slow writing speed, and then the program stored in the nonvolatile memory. Since the control is transferred to, there is a problem that it takes a lot of time after the program is loaded from the external system to the RAM until the program is executed.

Therefore, an object of the present invention is to provide a program rewriting method capable of shortening the time from the loading of the program from the external system to the RAM to the execution of the program.

[0007]

In order to achieve the above object, the present invention loads an electrically rewritable nonvolatile memory storing a program executed by a CPU and a program stored in the nonvolatile memory. In a program rewriting method in a computer system including a RAM, a program stored in the nonvolatile memory is loaded into the RAM, control is transferred to the program loaded in the RAM, and the program is loaded into the RAM. During execution of the program, a process of erasing the contents of the non-volatile memory and a process of copying the program loaded in the RAM to the non-volatile memory are sequentially executed, and after the copying is completed, the program is stored in the non-volatile memory. The control is transferred to the existing program.

Further, according to the present invention, the program loaded in the RAM is copied to the non-volatile memory in a free time of the CPU in order to efficiently perform the processing that should be originally performed in the computer system. It was done like this.

Furthermore, according to the present invention, in order to effectively use the address space of the computer system, the RAM and the non-volatile memory are arranged at the same address, and when the program is loaded into the RAM, the R
The writing to the AM is prohibited and the writing to the nonvolatile memory is prohibited. When the program loaded in the RAM is executed, the reading from the RAM is prohibited and the reading from the nonvolatile memory is prohibited. When the program stored in the non-volatile memory is executed, reading from the RAM is prohibited and reading from the non-volatile memory is permitted.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a computer system 1 for implementing the program rewriting method of the present invention. The computer system 1 includes a CPU 11
A ROM 12; a flash EEPROM 13 which is an electrically rewritable nonvolatile memory;
RAMs 14 and 15, a memory access control circuit 16 including a parallel output circuit 16a and AND gates AND1 to AND4, a decoder 17, and a communication LSI 18.
And OR gate OR. Also, an external system 2 is connected to the computer system 1 via a transmission path 3, and when rewriting a program stored in the flash EEPROM 13, the external system 2 is used.
The rewriting program is loaded from.

FIG. 2 is a memory layout diagram in the computer system 1, in which only the second RAM 15 is located at addresses N to (M-1) and the flash EEPROM 13 is located at addresses M to (L-1). The first area of the first RAM 14 and the ROM 12 are arranged at addresses L to K.
And the second area of the first RAM 14 are arranged.

FIG. 3 is a diagram showing an example of a program stored in the ROM 12, and at its head address L, writing to the flash EEPROM 13 and the first R
Prohibit reading from AM14, flash EEPR
Instructions for permitting reading from the OM 13, writing to the first RAM 14, and reading from the ROM 12 are stored. The addresses (L + 1) to (K-2) are stored in the first RAM 14 from the external system 2 to the addresses. First and second
The loader used to load the program to the area is stored, and the flash EEPR is stored at address (K-1).
Writing to the OM 12 and reading from the first RAM 14 are permitted, reading from the flash EEPROM 13, writing to the first RAM 14, and ROM 1
An instruction for prohibiting reading from 2 is stored.
No instruction is stored in the final address K.

FIG. 4 is a diagram showing an example of a program stored in the second area of the first RAM 14, and at the head address L thereof, an instruction for turning on an erase flag for instructing collective erase of the flash EEPROM 13 is made. However, at the address (L + 1), there is an instruction to turn on the copy flag for instructing to copy the contents of the first area of the RAM 14 to the flash EEPROM 13. The instruction to turn on the control transfer flag that instructs the transfer is at the address (L + 3) in the first area of the first RAM 14.
The instruction to transfer control to the beginning of the area is stored. Further, at the final address K of the second area, an instruction for transferring control to the head address L of the second area is stored. No instruction is stored in the addresses (L + 4) to (K-1).

The rewriting program loaded from the external system 2 is stored in the first area of the first RAM 14, and the rewriting program loaded in the first area is stored in the flash EEPROM 1 while the CPU 11 is idle.
3 is stored. The second RAM 15 is used as a work area.

The address output from the address terminal AD of the CPU 11 is supplied to the decoder 17 and R
OM12, flash EEPROM13, first RAM
14, the second RAM 15, the parallel output circuit 16a, and the address terminal AD of the communication LSI 18.

The decoder 17 sets the chip select signal CS1 to "1" when the address N to (M-1) is output from the address terminal AD of the CPU 11 to the second RAM.
If 15 is selected and the addresses M to (L-1) are output, the chip select signal CS2 is set to "1" to select the flash EEPROM 13 and the first RAM 14, and if the addresses L to K are output. Chip select signal C
The ROM 12 and the first RAM 14 are selected by setting S3 to "1".

The data terminal D of the CPU 11 is the ROM 1
2, flash EEPROM 13, first RAM 14,
Second RAM 15, parallel output circuit 16a, communication LSI
The eighteen data terminals D are connected by a data bus.

The memory access control circuit 16 includes the CPU 1
1, its output terminals ROMW, ROMR, RAM
According to the output signal of the parallel output circuit 16a in which the value of the signal output from W, RAMR is set to "1" or "0", the write signal output from the write signal terminal WR of the CPU 11 is stored in the flash EEPROM 13, the first RAM 14 Control whether or not to supply to
It controls whether or not the read signal output from the read signal terminal RD of 11 is supplied to the ROM 12, the flash EEPROM 13, and the first RAM 14.

Each output terminal ROM of the parallel output circuit 16a
When setting the values of the signals output from W, ROMR, RAMW, and RAMR, the CPU 11 outputs the address assigned to the memory access control circuit 16 and performs IO.
The write signal is set to "1", and the output terminals ROMW, ROMR, and RAM are further provided for the first to fourth bits, respectively.
The data in which the value (“1” or “0”) of the signal to be output from W, RAMR is set is output. For example, CPU
11 sets the first bit and the fourth bit to "0", and the second bit
When the data in which the bit and the third bit are set to "1" is output, each output terminal ROM of the parallel output circuit 16a
The signals output from W, ROMR, RAMW, and RAMR are "0", "1", "1", and "0", respectively, and AND gates AND1 and AND4 are turned off, and AND gates AND2 and AND3 are turned on. . As a result, C
The write signal output from the write signal terminal WR of the PU 11 is supplied to the first RAM 14 but is not supplied to the flash EEPROM 13, and the read signal output from the read signal terminal RD is R
It is supplied to the OM 12 and the flash EEPROM 13, but not supplied to the first RAM 14. That is, writing to the first RAM 14 and the ROM 1
2. Reading from the flash EEPROM 13 is permitted, but writing to the flash EEPROM 13 and reading from the first RAM 14 are prohibited. Note that the CPU 11 sets the first bit to the fourth bit to "0", "1", and
The data in which "0" and "0" are set is output, and the state of the memory access control circuit 16 is changed to the ROM 12 and the flash E.
Reading from the EPROM 13 is permitted, and the flash E
Writing to the EPROM 13 and the first RAM 14 and reading from the first RAM 14 are prohibited.

Next, the operation of rewriting the program stored in the flash EEPROM 13 will be described.

Communication LSI in computer system 1
When receiving a rewrite request for the program stored in the flash EEPROM 13 from the external system 2 via the transmission path 3, the CPU 18 receives the CPU 1
Interrupt 1 As a result, the CPU 11 determines the type of information received by the communication LSI 18, and if it determines that the request is a program rewrite request, it terminates the process that is currently being executed, and then controls the start address L of the ROM 12 to control. Move.

At the head address L of the ROM 12, as shown in FIG. 3, writing to the flash EEPROM 13 and reading from the first RAM 14 are prohibited, and reading from the flash EEPROM 13 and first RAM are performed.
Since an instruction for permitting writing to the ROM 14 and reading from the ROM 12 is stored, the CPU 11 executes
As shown in the flowchart of FIG. 5, writing to the flash EEPROM 13 and reading from the first RAM 14 are prohibited, and reading from the flash EEPROM 13, writing to the first RAM 14, and reading from the ROM 12 are permitted (S1). That is, the CPU 11 assigns “0”, “1”, to the first to fourth bits, respectively.
Data with "1" and "0" set is output from the data terminal D, and the output terminals ROMW and RO of the parallel output circuit 16a are output.
The values of the signals output from MR, RAMW and RAMR are set to "0", "1", "1" and "0", respectively.

Next, the CPU 11 executes the loader stored in the addresses (L + 1) to (K-2) of the ROM 12 to load the program from the external system 2 into the first RAM.
14 is loaded (S2). The programs loaded into the first RAM 14 include a rewriting program that replaces the program stored in the flash EEPROM 13 and the program shown in FIG. 4, and the rewriting program is the first program of the first RAM 14. The program loaded in the area and shown in FIG.
Will be loaded into the second area of.

After that, the CPU 11 executes the instruction stored in the address (K-1) of the ROM 12. This instruction, as shown in FIG.
3 is stored, and an instruction for permitting writing from the first RAM 14 and reading from the flash EEPROM 13, prohibiting writing from the first RAM 14, and reading from the ROM 12 is stored.
The PU 11 permits writing to the flash EEPROM 13 and reading from the first RAM 14, and reads from the flash EEPROM 13 and the first RAM.
Writing to 14 and reading from ROM 12 are prohibited (S3). That is, the CPU 11 sets the first bit to
"1", "0", "0", "1" in the 4th bit respectively
Is output from the data terminal D, and the output terminals ROMW, ROMR, RAM of the parallel output circuit 16a are output.
The values of the signals output from W and RAMR are set to "1", "0", "0", and "1", respectively.

After that, in the CPU 11, the value of the program counter (not shown) is "K", the reading from the ROM 12 is prohibited by the memory access control circuit 16, and the reading from the first RAM 14 is prohibited. Since it is permitted, the instruction stored in the address K of the first RAM 14 is executed.

The address K of the first RAM 14 is shown in FIG.
As shown in (1), since an instruction for transferring control to the start address L of the second area of the first RAM 14 (for example, a jump instruction with the jump destination as the address L) is stored,
The CPU 11 transfers the control to the start address L of the second area and executes the program from the address L (S4).

Addresses L, (L + of the first RAM 14
In 1) and (L + 2), as shown in FIG. 4, an instruction to turn on an erasing flag for instructing collective erasing of the flash EEPROM 13, and a content of the first area of the first RAM 14 are copied to the flash EEPROM 13. Since an instruction for turning on the copy flag for instructing that, and an instruction for turning on the control transfer flag for instructing to transfer the control to the flash EEPROM 13 after the copy are stored, the CPU 11 follows these instructions.
Turns on the erase flag, the copy flag, and the control transfer flag. Note that these flags are set in the second RAM 15, for example. After that, the CPU 11 executes the first
Stored in the address (L + 3) of the RAM 14 of
In accordance with an instruction (for example, a jump instruction whose address is the jump destination M) of the control to the first address M of the first area of the first RAM 14, the control is moved to the first address M of the first area of the first RAM 14, and from there. The program is executed (S5).

In the program stored in the first area of the first RAM 14, as shown in the flow chart of FIG.
When the PU 11 is waiting for the elapse of a certain time T, that is, when the CPU 11 is idle, the flash EEPROM 13
Batch erasure, flash EE contents of the first RAM 14
Flash EE for processing and control of copying to PROM13
Processing for shifting to the program stored in the PROM 13 is incorporated.

As shown in FIG. 6, the CPU 11 waits for a certain time T to elapse (S11),
It is determined whether the erasing flag is on, and if the erasing flag is on, the flash EEPR
The stored contents of the OM 13 are collectively erased, and then the erase flag is turned off (S13, S14).

When the fixed time T has elapsed at the time when the batch erasing of the flash EEPROM 13 is completed, the CPU 11 executes the processing performed after the fixed time has passed (S26). In addition, flash EEPROM1
If the predetermined time T has not elapsed even after the stored contents of 3 are erased all at once (NO in S12 and S13), it is determined whether the copy flag is on (S1).
5). If the copy flag is on, the program stored in the first RAM 14 is copied to the flash EEPROM 13 according to the next copy start address stored in the predetermined area of the second RAM 15 (S16). ).

If a certain time T has passed before the copy is completed (S17, S18), the CPU 11 records the next copy start position in a predetermined area of the second RAM 15 (S19), and then the process of S26. I do. When the copying is completed, the CPU 11 turns off the copying flag and then determines whether the control shifting flag is turned on if the fixed time T has not passed (S20,
S21, S22).

When it is determined that the control transition flag is not turned on, after waiting for the elapse of the fixed time T (S23), the process of S26 is performed. Also,
If it is determined that it is turned on, the control transition flag is turned off, and then a certain period of time T elapses (S2
3, S24).

When a certain time T has passed, the CPU
Reference numeral 11 denotes writing to the flash EEPROM 13, writing to the first RAM 14, and first RAM
Reading from 14 is prohibited, flash EEPROM
Reading from 13 and reading from ROM 12 are permitted (S25). That is, the CPU 11 sets the first bit to
"0", "1", "0", "0" in the 4th bit respectively
Is output from the data terminal D, and the output terminals ROMW, ROMR, RAM of the parallel output circuit 16a are output.
The values of the signals output from W and RAMR are set to "0", "1", "0", and "0", respectively.

As a result, the CPU 11 has the first RAM
Flash E instead of the program stored in 14
Although the program stored in the EPROM 13 will be executed (FIG. 5, S6), the flash EEPROM
13 and the first area of the first RAM 14 are arranged at the same address, and the program stored in the flash EEPROM 13 is the same as the program stored in the first area of the first RAM 14, The program running on the first RAM 14 can continue to run on the flash EEPROM 13.

FIG. 7 is a block diagram showing another configuration example of a computer system for carrying out the program rewriting method of the present invention. The computer system 100 is a CP.
U111, ROM112, flash EEPROM
113, a first RAM 114, and a second RAM 115
And a decoder 117 and a communication LSI 118. In addition, the computer system 100 includes a transmission line 3
The external system 2 is connected via the external system 2, and when the program stored in the flash EEPROM 113 is rewritten, the rewriting program is loaded from the external system 2.

FIG. 8 is a memory layout diagram in the computer system 100. The second RAM 115 is located at addresses N to (M-1), the flash EEPROM 113 is located at addresses M to (L-1), and the address L is located at address L. RO for K
M112 is the first RAM for addresses (K + 1) to J
The first area 114 indicates that the second area of the first RAM 114 is located at the addresses (J + 1) to E.

FIG. 9 is a diagram showing an example of instructions stored in the ROM 112. When loading a program from the external system 2 to the first area of the first RAM 114 at addresses L to (K-1). A loader to be used is stored, and an address K stores an instruction to transfer control to the head address (J + 1) of the second area of the first RAM 114.

FIG. 10 is a diagram showing an example of a program stored in the second area of the first RAM 114, and the flash EEPROM 1 is stored at the head address (J + 1).
An instruction for turning on the erase flag for instructing batch erase of 14 is stored, and the first RAM 1 is stored at the address (J + 2).
The contents of the first area 14 of the flash EEPROM 11
3 stores an instruction to turn on a copy flag for instructing copying, and an address (J + 3) stores an instruction to turn on a control transition flag for instructing to transfer control to the flash EEPROM 113 after completion of copying. The address (J + 4) stores an instruction to transfer control to the head address of the first area of the RAM 114.

The rewriting program loaded from the external system 2 is stored in the first area of the first RAM 114, and the rewriting program loaded in the first area is stored in the flash EEPROM in the idle time of the CPU 111.
It is stored in 113. The second RAM 115 is used as a work area.

The address output from the address terminal AD of the CPU 111 is supplied to the decoder 117 and also the ROM 112, the flash EEPROM 113, the first RAM 114, the second RAM 115, and the communication LSI.
It is supplied to the address terminal AD of 118.

The decoder 117 sets the chip select signal CS1 to "1" when the addresses N to (M-1) are output from the address terminal AD of the CPU 111, and the second R is set.
When the AM 115 is selected and the addresses M to (L-1) are output, the chip select signal CS3 is set to "1" to select the flash EEPROM 113, and the addresses L to K are selected.
Is output, the chip select signal CS4 is set to "1".
To select ROM 112 and select addresses (K + 1) to E
Is output, the chip select signal CS2 is set to "1".
Then, the first RAM 114 is selected.

Next, the operation for rewriting the program stored in the flash EEPROM 113 will be described.

L for communication in the computer system 100
When the SI 118 receives the rewrite request for the program stored in the flash EEPROM 113, which is sent from the external system 2 via the transmission line 3,
Interrupt the CPU 111. This allows the CPU
The 111 judges the type of information received by the communication LSI 18, and if it judges that it is a program rewriting request, it terminates the process currently being executed, and then the ROM 1
Control is transferred to the first address L of 12.

As a result, the CPU 111 causes the ROM 112 to
To load the program from the external system 2 into the first RAM 114. The programs loaded into the first RAM 114 include a rewriting program that replaces the program stored in the flash EEPROM 113 and the program shown in FIG. 10. The rewriting program is the first R program.
The program is loaded into the first area of the AM 114, and the program shown in FIG. 10 is loaded into the second area of the first RAM 114.

After that, the CPU 111 executes the instruction stored in the address K of the ROM 112, and transfers the control to the head address (J + 1) of the second area of the first RAM 114.

Address of the first RAM 114 (J +
Since the instructions shown in FIG. 10 are stored in 1), (J + 2), and (J + 3), the CPU 111 turns on the erase flag, the copy flag, and the control transfer flag in accordance with these instructions. After that, the CPU 111
The instruction stored in the address (J + 4) of the RAM 114 is executed, and the control is transferred to the head address (K + 1) of the first area of the first RAM 114.

As a result, the CPU 111 causes the first RA
The program loaded in the first area of M114 is executed. While executing the program on the first RAM 114,
As described above, the CPU 111 uses the idle time of the CPU to collectively erase the flash EEPROM 113.
The contents of the first area (rewriting program) of the RAM 114 are copied to the flash EEPROM 113. Then, when the copy process is completed, the CPU 1
11 is the address of the jump destination [(address currently being executed) + (flash EEPROM 113 and RAM 11
Then, a jump instruction with an address offset amount of 4) +1] is executed, and control is transferred to the flash EEPROM 113. As a result, the program running on the first RAM 114 continues to run on the flash EEPROM 11
Run on three.

[0049]

As described above, according to the present invention, the control of the program is immediately transferred after the program is loaded into the RAM, and the writing of the program to the non-volatile memory is performed during the execution of the program. Therefore, as compared with the conventional technique in which the control is transferred to the program written in the nonvolatile memory after the writing of the program in the nonvolatile memory is completed, the process from loading the program in RAM to executing the program There is an effect that the time can be shortened.

Further, according to the present invention, the copying of the program loaded in the RAM to the non-volatile memory is performed during the idle time of the CPU, so that there is an effect that the processing originally intended for the computer system can be efficiently performed. .

Further, according to the present invention, since the RAM into which the program is loaded and the non-volatile memory are arranged at the same address, the address space of the computer system can be effectively used. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a computer system that implements a program rewriting method of the present invention.

2 is a memory layout diagram in the computer system 1 shown in FIG. 1. FIG.

FIG. 3 is a diagram showing an example of contents of a ROM 12.

FIG. 4 is a diagram showing an example of contents of a second area of the first RAM 14.

FIG. 5 is a flowchart showing a processing example of the computer system 1 when rewriting a program.

FIG. 6 is a block diagram showing the contents of a first area of the RAM 14 which are erased in a flash EEPROM.
6 is a flowchart showing a processing example of the computer system 1 when copying to the EPROM 13.

FIG. 7 is a block diagram showing another configuration example of a computer system that implements the program rewriting method of the present invention.

8 is a memory layout diagram in the computer system 100 shown in FIG. 7. FIG.

FIG. 9 is a diagram showing an example of contents of a ROM 112.

FIG. 10 is a diagram showing an example of contents of a second area of the first RAM 114.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Computer system 11 ... CPU 12 ... ROM 13 ... Flash EEPROM 14 ... First RAM 15 ... Second RAM 16 ... Memory access control circuit 16a ... Parallel output circuit 17 ... Decoder 18 ... Communication LSI 2 ... External system 3 ... Transmission path 100 ... Computer system 111 ... CPU 112 ... ROM 113 ... Flash EEPROM 114 ... First RAM 115 ... Second RAM 117 ... Decoder 118 ... Communication LSI

Claims (3)

[Claims] 1. A program rewriting method in a computer system comprising an electrically rewritable non-volatile memory storing a program executed by a CPU, and a RAM loaded with the program stored in the non-volatile memory. Where the program stored in the non-volatile memory is stored in the RAM
The program loaded in the RAM, control is transferred to the program loaded in the RAM, and the program loaded in the RAM is erased while the program loaded in the RAM is being executed. Rewriting method, characterized in that a process of copying to a non-volatile memory is sequentially executed, and after the copying is completed, control is transferred to the program stored in the non-volatile memory. 2. The program rewriting method according to claim 1, wherein the program loaded in the RAM is copied to the non-volatile memory in a free time of the CPU. 3. The RAM and the non-volatile memory are arranged at the same address, and when the program is loaded into the RAM, the RAM
Write to the non-volatile memory is prohibited and write to the non-volatile memory is prohibited. When the program loaded in the RAM is executed, read from the RAM is prohibited and read from the non-volatile memory is prohibited. 3. The program rewriting method according to claim 2, wherein when the program stored in the memory is executed, reading from the RAM is prohibited and reading from the non-volatile memory is permitted.