JPH0261896A - Electrically erasable programmable read only memory - Google Patents

Electrically erasable programmable read only memory

Info

Publication number
JPH0261896A
JPH0261896A JP21116488A JP21116488A JPH0261896A JP H0261896 A JPH0261896 A JP H0261896A JP 21116488 A JP21116488 A JP 21116488A JP 21116488 A JP21116488 A JP 21116488A JP H0261896 A JPH0261896 A JP H0261896A
Authority
JP
Japan
Prior art keywords
write
readout
data
circuit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21116488A
Other languages
Japanese (ja)
Inventor
Toshihide Tsuboi
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP21116488A priority Critical patent/JPH0261896A/en
Publication of JPH0261896A publication Critical patent/JPH0261896A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/20Suspension of programming or erasing cells in an array in order to read other cells in it

Abstract

PURPOSE: To enable readout to be executed even during write by performing a write operation after storing a write address and write data, and executing a readout operation preferentially by interrupting the write when a readout command is issued during the write.
CONSTITUTION: When a read/write signal R/W to be inputted to a control circuit 18 is set at a write state, a cell array 11 corresponding to an address AD is selected, and also, the address AD is stored in an address memory circuit 15. Next, data DA is held at a data memory circuit 17, and the write operation is performed. When the signal R/W is set at a read state during the write, the circuit 18 interrupts the impression of a write voltage transiently, and performs a readout operation. On completing the readout, the circuit 18 reads out the address from the circuit 15, and restarts the impression of the write voltage based on the data in the circuit 17. In such a way, it is possible to perform the readout of the data even during the write operation, and to always utilize the data stored in a P-ROM.
COPYRIGHT: (C)1990,JPO&Japio
JP21116488A 1988-08-25 1988-08-25 Electrically erasable programmable read only memory Pending JPH0261896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21116488A JPH0261896A (en) 1988-08-25 1988-08-25 Electrically erasable programmable read only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21116488A JPH0261896A (en) 1988-08-25 1988-08-25 Electrically erasable programmable read only memory

Publications (1)

Publication Number Publication Date
JPH0261896A true JPH0261896A (en) 1990-03-01

Family

ID=16601461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21116488A Pending JPH0261896A (en) 1988-08-25 1988-08-25 Electrically erasable programmable read only memory

Country Status (1)

Country Link
JP (1) JPH0261896A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319281A (en) * 2001-04-19 2002-10-31 Canon Inc Magnetic memory and drive method therefor
JP2014186787A (en) * 2013-03-25 2014-10-02 Toshiba Corp Nonvolatile semiconductor memory device, memory controller, and memory system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319281A (en) * 2001-04-19 2002-10-31 Canon Inc Magnetic memory and drive method therefor
JP4726169B2 (en) * 2001-04-19 2011-07-20 キヤノン株式会社 Magnetic memory and driving method thereof
JP2014186787A (en) * 2013-03-25 2014-10-02 Toshiba Corp Nonvolatile semiconductor memory device, memory controller, and memory system
US9558837B2 (en) 2013-03-25 2017-01-31 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device

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