JPS62130427A - Memory read/write system - Google Patents

Abstract

PURPOSE:To prevent such a case that once accepted interruption processing remains interrupted by insuring an offering request from the outside against being reset after the processing of error, which may occur while a memory is read and written, is completed. CONSTITUTION:According to a micro instruction (a), data is initially read and written in the memory. Immediately after an offering request is issued from an external device, a CPU sets a flip-flop 9. Afterwards, the instruction advances, a signal 100 comes to a high level at the timing of a mu-END (microend of the micro-instruction), and a clock to the CPU from a basic clock generator circuit 14 is interrupted by a gate 15. Accordingly, even if error processing is executed in the middle of memory read/write execution, the flip-flop 9 is not reset, and the interruption request from the external device can be surely executed at the initial mu-END after error processing ends.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a read/write method for a memory connected to a CPU of a microprogram controlled computer via an external bus.

[Technical Background of the Invention] Conventionally, in an arithmetic control method for a microprogram-controlled computer, when reading or writing to a memory connected to a CPU via an external bus, memory Control is performed to temporarily stop the execution of instructions, except for specific microinstructions, even during read/write execution. In this case, we will use a method that does not use clock stop control that disables the clock of the arithmetic control unit, and if multiple interrupts occur simultaneously during program execution, we will use a method that starts execution from the interrupt processing with the highest priority. The computer controlled by the control section performs operations as shown in the time chart of FIG. The specific microinstructions mentioned above include, for example, an instruction to read a register in the CPU where data read from memory is set during a memory read, an instruction to start the next memory write while a memory write is being executed, etc. There are instructions that cannot be executed until memory read/write is completed.

In Figure 3, (A), (B), (C), (D)
, (E), and (F) are the basic clock and flip-flop set timing indicating memory access, respectively.
Interrupt reception is based on flip-flop set timing,
The set timing of the flip-flop indicating the occurrence of an error interrupt, the address of the ROM for the microprogram, and the instructions of the executed microprogram are shown respectively.
b is the micro-end, d is the first interrupt processing instruction from an external device, e is the flip-flop glue set micro-instruction that indicates the occurrence of an error interrupt, f is the first micro-instruction for error interrupt processing, and ※※ This shows that nothing happens in interrupt acceptance because the flip-flop is in reset 1, and 81 to e1 show the microaddress of the microinstruction. First, the CPU starts memory access according to the memory read/write of the microinstruction, and performs the memory read/write at timing A in Figure 3 (8).
Sets a flip-flop indicating execution of a write. Note that this flip-flop is used to enable the clock stop when a special microinstruction is to be executed during memory read/write, as described above. Next, an interrupt request is generated from an external device during memory read/write execution, and when the CPU accepts this interrupt request, the flip-flop indicating that the interrupt request has been received is activated at the timing shown at the beginning of FIG. 3(C). Set this to notify the external device that issued the interrupt request that the request has been accepted. After that, at the timing of the micro-end (hereinafter referred to as μ-END) of the micro-instruction, the address a1 of the ROM where the microprogram is written is replaced with the address d1 for interrupt processing, as shown in FIG. 3(E). The above interrupt processing is started. During this processing, the CPU uses a microinstruction to reset the flip-flop indicating interrupt acceptance at timing 2 in FIG. 3(C). However, if an error interrupt occurs during the necessary memory read/write during execution before all of the above interrupt processing started by the CPU is completed, the error interrupt will be detected as shown in Figure 3 (D). Set the flip-flop shown at the timing E. Here, the above μmEND
is executed at the end of a software instruction, and if instruction prefetch control is performed, the software that has already been prefetched and is in instruction buffer 1 is read. Also, if prefetch control is not performed, instruction fetching is started. Normal interrupts other than error interrupts are μ-instructions that start processing at this timing.

[Problems with Background Art] When the above situation occurs, the following inconveniences occur. That is, when an error interrupt occurs at the timing E in FIG. 3(D), the microinstruction address b1 shown in FIG. 3(E) is changed to the error interrupt processing address f1 to perform error processing. . Even if this error interrupt processing is all completed, a new instruction is fetched, a software instruction is started, and μ-END is executed, the interrupt processing from the external device that was interrupted due to the above error interrupt will be interrupted by this interrupt. Since the flip-flop indicating that the processing request has been accepted is reset at timing 2 in FIG. 3(C), the processing is not executed. However, once the CPU accepts the request, the external device that issued the interrupt request will
Thereafter, the user has to wait for the requested interrupt processing for a long time, which is an inconvenience.

[Object of the Invention] In view of the above drawbacks, an object of the present invention is to provide a memory read/write method that prevents interrupt processing once accepted from remaining suspended.

[Summary of the Invention] The present invention provides that when a CPU receives an interrupt request from an external device while reading or writing a memory connected via an external bus, the first μ
The synchronous clock supplied to the CPU is stopped at mEND, and after the execution of reading or writing of the memory is completed, the synchronous clock is supplied to the CPU again, and error processing that may occur during execution of reading or writing of the memory is prevented. Even after the interrupt request from the external device is completed, the flip-flop indicating acceptance of the interrupt request from the external device is not reset, and control is executed to execute the interrupt request from the external device at the first μm END that is seen thereafter. This achieves the purpose of preventing interrupt processing from remaining suspended.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of a microprogram control computer to which the memory read/write method of the present invention is applied. 1 is a plurality of ROMs in which microprograms for controlling the operation of a CPU (not shown) are written;
2 is a register that sets output contents according to the address supplied to the ROM 1; 3 is a microprogram counter; the counter value is one of a plurality of addresses supplied to the ROM 1; 4 is a gate circuit that supplies an address to ROM 1 according to the priority of various interrupts generated in the CPU; 5 is a selector that selects one of the multiple types of addresses that can be supplied to ROM 1; 6 is a CPU
This is a gate circuit that controls the selector 5 according to the state of the selector 5. 7 is a flip-flop that is set by an error interrupt that occurs when the CPU reads/writes the memory, and is set for a predetermined period of time (1 block), and is set when a clock stop (described later) occurs, but is reset. I don't talk. 8 is a flip-flop that is left while the CPU is reading/writing the memory; it is set by the read/write microinstruction, and is automatically reset in synchronization with the clock when the read/write is finished. Ru. Reference numeral 9 denotes a Noritsubu flop that is set when the CPU accepts a pJ interrupt request from an external device, and is set by a reset microinstruction during interrupt processing.

Reference numeral 10 indicates gates 1 to 1 which enable the output of the flip-flop 9 at the μ-END timing and send the output to the gate circuit 4 and gate 12. Reference numeral 11 denotes a gate that outputs one of the causes of clock stop when the CPU executes a special microinstruction while the flip-flop 8 is set. Reference numeral 12 denotes a gate that outputs one of the causes of clock stop when the output of the gate 10 is enabled while the flip-flop 8 is set. 13 is multiple Chlorus 1~
The gates 1 to 1 calculate the logical sum of the knobs and output the result to the gate 15. 14 is a basic clock generation circuit, 15
is a gate that allows the basic clock output from the basic clock generation circuit 14 to pass when the clock stop output from the gate 13 is in a false state.

Note that the reference numeral 50 indicates a microaddress input from a source other than the microprogram counter 3 and the gate circuit 4.
0 indicates an interrupt request input from a source other than the flip-flop 7 and gate 10, and 70 indicates a clock stop cause signal input from a source other than gates 11 and 12.

Next, the operation of this embodiment will be explained with reference to FIG. First, the contents a1 of the microprogram counter 3 are selected by the selector 5 as the supply address of the ROM1, and this is sent to the ROM1. Therefore, the corresponding microinstruction a is read from the ROM 1 and set in the register 2. In addition, ROM1 is shown in (G) in Figure 2.
The output timing of the read address a1 is shown in FIG. Figure 2 (
At the timing shown in D), the flip-flop 8 is set, and at the same time, a read or write process is started for the CPU (not shown, as it is connected to the CPU via an external bus). Immediately after that, an interrupt request is generated from an external device (not shown), and the CPU accepts this and sets the flip-flop 9 at the timing shown by C in FIG. 2(E). After that, execution of the microinstruction proceeds,
The signal 100 becomes high level and is output to the gate 10 at the timing of μmEND, which is a microinstruction that appears immediately before the next software instruction is to be executed.

At this time, since the external interrupt flip-flop 9 is set, the signal 100 passes through the gate 10 and is input to the gate circuit 4 and gate 12. Furthermore, since the flip-flop 8 is also set at this time, the signal 100 passes through the gate 12, further passes through the OR gate 13, and is input to the gate 15. Therefore, this gate 15 is
It closes at timing A shown in FIG. 2(C), and at this timing, the clock output from the basic clock generation circuit 14 is cut off by the gate 15, as shown in FIG. 2(8).

On the other hand, the gate circuit 4 receives the signal @1 as shown in FIG. 2(G).
When 00 is input, the address d1 corresponding to the processing of the interrupt request from the external device is output to the selector 5, and the gate circuit 6 selects the address supplied from the gate circuit 4 and outputs it to the ROM 1. Generates a select signal to

Thereafter, the reading/writing of the memory proceeds while the clock is stopped, but if an error occurs at the timing shown in FIG. 2(F) during the process, the flip-flop 7 is set at this timing. Therefore, the output J of the gate circuit 4 outputs the address e1 of the microinstruction that starts error interrupt processing with a high interrupt priority at the timing shown in FIG. Since the signal does not change, address e1 passes through selector 5 and is supplied to ROM1. In this state, when reading/writing to the memory is completed, the 7 lip-flop 8 is reset at the timing shown in FIG. 2(D), and the gate 12 is closed. As a result, the clock stop signal output from the gate 13 is stopped, and the gate 15 opens. The clock generated from the basic clock circuit 14 passes through this gate and is output to the CPU as shown in FIG. 2 (8). Therefore, as shown in FIG. 2 (G), 01), microinstruction e according to microaddress e1 is set from ROM1 to register 2, and the CPU starts executing error interrupt processing according to this microinstruction e. do. After that, all error interrupt processing is completed, a new instruction is fetched, the first software instruction is executed, and the first μm
Since the gate 10 opens at the timing when END is set in the register 2, the output of the flip-flop 9 can be input to the gate circuit 4. Thereby, the gate circuit 4 outputs to the selector 5 the address d1 for reading the microprogram in the ROM 1 corresponding to the processing of the interrupt request from the external device. This time, since there are no other interrupt factors, the address d output from the gate circuit 4
1 is output to the ROM 1, a microinstruction d corresponding to this address is read from the ROM 1 and set in the register 2, and processing of an interrupt request from an external device is executed. After that, when this interrupt request processing is completed, Fig. 2 (E
) The flip-flop 9 is reset at the timing indicated by . Incidentally, FIG. 2(A) shows the generation timing of the basic clock generated from the basic tarlock generation circuit 14.

According to this embodiment, after accepting an interrupt request from an external device during memory read/write execution, the first μ-E
Since the clock to the CPU is stopped at ND, even if an error occurs during memory read/write execution and this error processing is performed, the flip-flop 9 is not reset and the first μm END after this error processing is performed. Since the interrupt request of the external device can be reliably executed in the above-described manner, a situation in which the external device that has accepted the interrupt request is left waiting for its processing will not occur.

[Effects of the Invention] As described above, according to the memory read/write method of the present invention, an interrupt request from an external device can be accepted while the CPU is reading or writing a memory connected via an external bus. , then the first μmE
The ND stops the synchronous clock supplied to the CPU, and after the execution of the memory read or write is completed, the synchronous clock is supplied to the CPU again, and the error processing that occurs during the execution of the memory read or write is handled. Even after the interrupt request from the external device has been completed, the flip-flop indicating reception of the interrupt request from the external device is not reset, and control is executed to execute the interrupt request from the external device at the first μm END that is explained thereafter. This has the effect of preventing interrupt processing once accepted from remaining suspended.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer system to which the memory read/write method of the present invention is applied, and FIG. 2 is an operation timing chart of the system shown in FIG.
FIG. 3 is an example of an operation timing chart explaining a conventional memory read/write method. 1...ROM 2...Register 3...
- Micro program counter 4.6... Gate circuit 5... Selector 7.8.
9...Flip-flop 10, 11.12.13.15...Gate 14...
Basic clock generation circuit agent Patent attorney Nori Chika Yudo Sanno −

Claims (1)

[Claims] In a microprogram-controlled computer system that has a memory connected to the CPU via an external bus and executes interrupt requests in the order of their priority, the CPU
a flip-flop that is set when an interrupt request is received from an external device during execution of read/write to the memory; and a synchronous clock that is supplied to the CPU at the first microend timing after accepting the interrupt from the external device. synchronous clock supply stop means for stopping the periodic clock supply to the CPU when the execution of reading/writing of the memory is completed; control means for starting execution of the external device interrupt request using the set signal of the flip-flop in the first microend after the execution of this interrupt request is completed when an interrupt request that has priority over the external device interrupt request occurs; A memory read/write method, characterized in that the flip-flop is not reset while reading/writing the memory.