JPH11282787A - Input/output control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output control device which is equipped with a micro program a structure of which is simplified by eliminating insertion of a micro instruction with no logical connection. SOLUTION: In this input/output control device, by being equipped with a control storage 11 for storing a micro program provided with an execution time set instruction that can set the execution time for each micro instruction, it is possible to execute each micro instruction by substantially freely changing the fixed execution time. Also, control of the execution time is performed by a timer circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input / output control device (microprogram control device) for controlling a plurality of channel devices by a microprogram control method.

[0002]

2. Description of the Related Art A microprogram is a control word (microinstruction) that controls low-level hardware operations that cannot be seen from software in order to realize computer hardware functions (machine language instructions and interrupt operations). ), And is sometimes referred to as firmware (FW). This microprogram is distinguished from a general program using machine language instructions.

In general, the processing operation of one machine language instruction consists of taking out data from a register or a memory, sending the data to an arithmetic unit, and storing the operation result in the register or the memory again. Further, in order to realize this processing operation, the inside of the hardware is provided with a channel device such as a register, an address generation circuit, various arithmetic units, and a data bus connecting them, which are not visible from a general program. Furthermore,
When executing a general program, it is necessary to control each channel device at an appropriate timing in accordance with the designation of a machine language instruction.

[0004] The microprogram control system accesses the control memory when controlling each channel device as described above, and performs control using the control word read therefrom.

Here, a configuration of a conventional microprogram controller (input / output controller) will be described with reference to the drawings.

As shown in FIG. 7, a conventional input / output control device 1 has a control storage (CS) 11 storing a microprogram composed of a plurality of microinstructions representing a plurality of instructions, and a control storage (CS) 11. A control storage address register (CSAR) 12 for generating a read address signal for accessing the memory 11 and a read register (CSDR) 13 for holding a microinstruction read from the control storage 11
A decoder 14 for decoding a microinstruction held by the read register 13 to generate a control signal;
4, an interface circuit 15 for transmitting the control signal generated to the plurality of channel devices 2 to n and controlling various signals with the plurality of channel devices 2 to n, and a microprogram control unit 16 for controlling the execution time of the microinstruction. And

The outline of the operation of the conventional input / output control circuit 1 having such a configuration is as follows.

The control storage address register 12 generates a read address signal indicating where the microinstruction to be selected is stored in the control storage 11, and sends the read address signal to the control storage 11.

The control memory 11 that has received the read address signal sends the microinstruction designated by the read address signal to the read register 13 as instruction data.

When receiving the instruction data, the read register 13 holds the received instruction data until the execution of the microinstruction indicated by the instruction data is completed. here,
At the same time, the read address value of the control storage address register 12 is incremented by one.

The decoder 14 decodes the instruction data held in the read register 13 to generate an instruction signal,
At the same time as sending to the interface circuit 15, the microcontroller 16 sends an instruction type signal unique to the microinstruction indicated by the instruction data to the microprogram controller 16.

The interface circuit 15 sends an instruction signal generated by the decoder 14 to other circuits in the input / output control device and a plurality of channel devices 2 to n.

Further, the microprogram control unit 16
By decoding the instruction type signal received from the decoder 14, the holding time of the instruction data indicated by the instruction type signal in the read register 13 is obtained. Further, upon obtaining the microinstruction holding time in the read register 13, the microprogram control unit 16 sends an address update inhibit signal to the control storage address register 12, and inhibits the update of the read address more than necessary. Here, the execution time of each micro-instruction is different for each micro-instruction, and is fixed and does not change for each micro-instruction.

In this way, the input / output control device 1 controls the plurality of channel devices 2 to n to perform desired operations.

Here, it is known that there are micro-instructions that cannot be executed continuously due to restrictions on the hardware or software of a computer. When such a microinstruction is executed, it is necessary to guarantee a certain time interval between the microinstruction and the next microinstruction. On the other hand, the micro-instruction conventionally has a fixed instruction execution time as described above. Therefore, conventionally, in order to guarantee the time, a required number of NOP instructions (dummy microinstructions only for timing) are inserted.

[0016]

However, the conventional input / output control device has the following problems since a NOP instruction is inserted to guarantee time.

That is, in the conventional input / output control device,
There is a problem in that the structure of the microprogram itself is complicated by inserting a process having no logical connection.

Further, the NOP instruction, which is a dummy micro instruction merely for time guarantee, wastes the number of steps, that is, places a limit on the microprogram that can be stored in the control memory (CS). There was a problem.

An object of the present invention is to provide an input / output control device having a microprogram whose structure is simplified by eliminating the insertion of microinstructions which are not logically connected in order to solve the above problem. It is in.

Another object of the present invention is to provide N
An object of the present invention is to provide an input / output control device capable of effectively utilizing the capacity of a control storage by deleting an OP instruction.

[0021]

The present invention proposes the following means in order to solve the above problems.

That is, according to the present invention, by providing a control memory storing a microprogram having an execution time setting instruction capable of setting the execution time of each microinstruction, the fixed execution of each microinstruction is provided. An input / output control device that can be executed with the time substantially freely changed is obtained.

Further, according to the present invention, the input / output control device can obtain an input / output device capable of effectively utilizing the capacity of control storage by eliminating the NOP instruction only for time guarantee.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an input / output control device according to an embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, an input / output control device according to an embodiment of the present invention comprises a control storage (CS) 11, a control storage address register (CSAR) 12, a read register (CSDR) 13, a decoder 14, An interface circuit 15 and a timer circuit 10 are provided. The control storage (CS) 11 stores a microprogram including a plurality of microinstructions each representing a plurality of instructions. Here, the plurality of microinstructions stored in the control storage 11 include an execution time setting instruction for setting an execution time. The execution time setting instruction is indicated by, for example, “TIMEx” in FIG. When x is a number, it indicates a time xT to be set as an execution time for an instruction executed immediately before the TIME command,
In the case of "R", it means that instructions below the instruction executed immediately after the TIME command are returned to the default time. “T” means the unit time of the execution time of the instruction data. Control storage address register (CSAR) 1
2 generates a read address signal for accessing the control memory 11. The read register (CSDR) 13
The microinstruction read from the control storage 11 is held as instruction data. The decoder 14 includes a read register 13
Is decoded to generate an instruction signal. The interface circuit 15 sends the command signal generated by the decoder 14 to the plurality of channel devices 2 to n and controls various signals with the plurality of channel devices 2 to n. The timer circuit 10 dynamically sets the execution time of each microinstruction.

First, the operation when a general microinstruction is executed will be described in detail.

The control memory address register 12 generates a read address signal indicating where the microinstruction to be selected is stored in the control memory 11, and sends the read address signal to the control memory 11.

The control memory 11, which has received the read address signal sent from the control memory address register 12, sends the microinstruction designated by the read address signal to the read register 13 as instruction data.

The read register 13 holds the received instruction data until the execution of the microinstruction indicated by the instruction data is completed.

The decoder 14 decodes the instruction data held in the read register 13 to generate an instruction signal and sends it to the interface circuit 15.

The interface circuit 15 sends the command signal generated by the decoder 14 to other circuits in the input / output control device and the plurality of channel devices 2 to n.

In this manner, each microinstruction is executed, and the plurality of channel devices 2 to n are controlled.

Next, the operation when the execution time setting command, which is one of the features of the present invention, is executed will be described in detail.

First, like the other microinstructions, an execution time setting instruction is read from the control memory 12 to the read register 13 in accordance with the read address signal generated by the control memory address register 16 and held in the read register 13. You.

The decoder 14 decodes the execution time setting instruction held by the read register 13 and sets the setting time indicated by the execution time setting instruction in the timer circuit 10. The time set here is valid until it is set again by the time setting command. However, this execution time setting instruction is not affected by the set time at that time, and ends when the set time is set in the timer circuit 11.

The timer circuit 10 sends the read address update signal to the control storage address register 16
Is updated, and the control storage address register 16 is updated.
Generates a read address signal according to the address and reads the next microinstruction.

Further, the timer circuit 10 will be described with reference to FIG.

As shown in FIG. 3, the timer circuit 10 includes, for example, a counter circuit 101 and a data register 10.
2. Instruction determination circuit 103, comparison circuit 104, OR circuit 1
05 can be realized. The counter circuit 101 counts up by +1 and is reset by receiving a reset signal described later. The data register 102 receives the set time data from the decoder 14 and sets the set time. When the execution time setting command is not executed, “0” is set in the data register 102. The instruction determination circuit 103 receives the instruction type signal from the control storage 11,
The type of the instruction data stored in the read register 13 is determined. If the instruction data is an execution time setting instruction, a read address update signal is output, and the next instruction is read.
At this time, if the instruction is another instruction, the instruction determination circuit 103 acquires the execution time required to execute the other instruction. The execution time is obtained based on the result of decoding the instruction type signal. The instruction type signal is an operation code (instruction code) included in the instruction data.
Means that When the result of the determination by the instruction determination circuit 103 indicates that the instruction is another instruction, the comparison circuit 104 determines whether the set time is shorter than the minimum execution time of the instruction data or not. For each, the counter circuit 101 and the data register 10
2, and a read address update signal is generated from the information output from the instruction determination circuit 103.

As described above, when the instruction is an instruction other than the execution time setting instruction, the instruction determination circuit 103 determines the time required to execute the instruction. The counter circuit 101 starts measuring the execution time, considering the time when the instruction is read from the control storage 11 as the start time of the execution of the instruction.

Here, the comparison circuit 104 determines the set time stored in the data register 102 and the instruction determination circuit 1
The operation is performed as follows by comparing the minimum execution time determined in step S03 with the minimum execution time and according to the comparison result.

1) When the set time is shorter than the minimum execution time of the instruction data The comparison circuit 104 compares the value held in the data register 102 with the value determined by the instruction determination circuit 103, Is shorter than the minimum execution time of the instruction data, the counter value of the counter circuit 101 is compared with the value of the instruction determination circuit 103, that is, the minimum execution time, and the counter value of the counter circuit 101 is
If it is longer than the minimum execution time, a read address update signal is sent. The counter circuit 101 is reset by the read address update signal. The initial value at the time of reset in the counter circuit 101 is “1”. This series of processing is shown in FIG.

2) When the set time is equal to or longer than the minimum execution time of the instruction data The comparison circuit 104 compares the value held in the data register 102 with the value determined by the instruction determination circuit 103, and When it is determined that the time is equal to or longer than the minimum execution time of the instruction data, the counter value of the counter circuit 101 is compared with the value held in the data register, and the counter value of the counter circuit 101 is equal to or larger than the value held in the data register. , A read address update signal is sent.

Here, when the counter value of the counter circuit 101 is larger than the set time, the enable signal is invalidated. In other cases, the enable signal is:
Always enabled.

Next, referring to FIGS. 2, 5 and 6,
The operation of the conventional technology and the operation of the input / output control device according to this embodiment will be compared and studied.

FIG. 2 shows a case where the instruction "B" is to be executed after the instruction "A", and a time guarantee of 5T is required between the instruction "A" and the instruction "B". FIG. 7 is a diagram comparing the firmware according to the related art with the firmware according to the present embodiment in a case. Referring to FIG. 2A, the conventional input / output control device does not include an execution time setting instruction as a microprogram, and does not include a device corresponding to the timer circuit 10 according to the present embodiment. For this reason, time is guaranteed by inserting five NOP instructions between the instruction “A” and the instruction “B”. On the other hand, in the input / output control device according to the present embodiment, as shown in FIG. 2B, the command "TIME 6" and the command "TIME
A similar process can be performed using "R".
That is, "TIME 6" is executed before the execution of the instruction "A", and the execution time after the instruction "A" is set to 6T. Furthermore,
After the execution of the instruction "A", the instruction "B" and the subsequent steps are returned to the default time using "TIMER". As a result, the time can be guaranteed only by the instruction "A", and the NOP required in the conventional device becomes unnecessary.

FIG. 5 shows an example of the input / output control device according to the present embodiment shown in FIG. 1 and the conventional input / output control device shown in FIG. This is an example showing the guaranteed time up to the next instruction (here, a write instruction) in the case of performing the operation. FIG. 6 shows a processing flow when the processing shown in FIG. 5 is executed.

As will be understood with reference to FIGS. 5 and 6, in the conventional input / output control device, a time guarantee program is required for each channel device. In the above, the execution time setting command is executed for each channel device before the execution of the read command, whereby the time guarantee program of the conventional device becomes dependent. Therefore, according to the present embodiment, the program structure can be shared and simplified. Also, in this processing example, a case has been described in which an instruction is issued to two channel devices. However, the more devices that have different guaranteed times are connected, the more compared to the input / output control device of the conventional configuration. This is effective because the firmware structure can be shared and simplified.

Further, according to the present embodiment, since a portion where a NOP instruction is conventionally inserted for time guarantee can be omitted, the number of steps in firmware can be reduced. Further, for the same reason, it is possible to prevent the firmware structure from becoming complicated due to insertion of an excessive firmware process such as insertion of a NOP instruction.

[0049]

As described above, according to the present invention,
Since there is no need to insert a logically unconnected program routine such as the insertion of a NOP instruction which has been conventionally required for time assurance, the firmware structure can be simplified.

Further, according to the present invention, since it is not necessary to insert a NOP instruction for time guarantee, the number of steps in the firmware can be saved, and the number of significant instructions that can be stored in the control memory can be reduced. That is, the storage capacity in the control storage can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an input / output control device according to an embodiment of the present invention.

FIG. 2 is a diagram for comparing a firmware structure according to the present embodiment with a firmware structure according to a conventional example.

FIG. 3 is a diagram showing a configuration of a timer circuit according to the present embodiment.

FIG. 4 is a diagram showing one process of a timer circuit shown in FIG. 3;

FIG. 5 is a diagram showing a guaranteed time required when issuing an instruction to the channel device 2 and the channel device 3;

FIG. 6 is a diagram showing a processing flow of instruction execution performed after guaranteeing the guaranteed time shown in FIG. 5;

FIG. 7 is a block diagram illustrating a configuration of an input / output control device having a conventional configuration.

[Explanation of symbols]

 Reference Signs List 1 input / output control device 2 to n channel device 10 timer circuit 101 counter circuit 102 data register 103 instruction determination circuit 104 comparison circuit 105 OR circuit 11 control storage (CS) 12 control storage address register (CSAR) 13 read register (CSDR) 14 Decoder 15 interface circuit

Claims (5)

[Claims] 1. An input / output control circuit for controlling a plurality of channel devices, comprising: a control storage for storing a microprogram comprising a plurality of control words representing a plurality of instructions; and an access control circuit for accessing the control storage. A control storage address register for generating a read address signal, a read register for holding the control word read from the control storage, a decoder for decoding the control word held by the read register and generating an instruction signal; An input / output control device comprising: an interface circuit for transmitting the command signal generated by the decoder to the plurality of channel devices and controlling various signals with the plurality of channel devices. An execution time setting instruction for setting an execution time of the instruction is stored, and the execution time setting instruction is executed to execute the execution time setting instruction. An input / output control device wherein the execution time is set to a time including a guaranteed time. 2. The input / output control device according to claim 1, wherein the control storage is capable of effectively utilizing a capacity by reducing unnecessary no-operation instructions. 3. The input / output control device according to claim 1, further comprising: a timer circuit for dynamically setting an execution time of each of the instructions, wherein the execution time of each of the instructions is reduced. An input / output control device characterized by being variable. 4. The input / output control device according to claim 3, wherein the timer circuit holds a counter circuit that measures an execution time of each of the instructions and data of a set time set by the execution time setting instruction. A data register, an instruction determination circuit that decodes a minimum execution time of each instruction read from the control storage to the read register, and a comparison between the execution time measured by the counter circuit and the set time. A comparison circuit that generates a read address update signal that is a signal for transmitting an update timing that is a timing for shifting to the instruction. 5. An input / output control circuit for controlling a plurality of channel devices, said control memory storing a microprogram comprising a plurality of control words representing a plurality of instructions, and an access control circuit for accessing said control memory. A control storage address register for generating a read address signal, a read register for holding the control word read from the control storage, a decoder for decoding the control word held by the read register and generating an instruction signal; And an input / output control device having an interface circuit for transmitting the command signal generated by the decoder to the plurality of channel devices and controlling various signals with the plurality of channel devices, and guaranteeing the execution time of the command. A new execution time setting instruction is stored in the control memory, and the execution time setting instruction is used. Execution time guarantee method that ensures the execution time of the instruction Te.