JPH0445862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device using a microprogram control method.

[Prior art]

In conventional microprogram-controlled information processing devices, when data is written to the main memory, the microinstruction immediately after starting the write or after a specified step is executed by the machine until the actual write to the main memory is completed. The cycle time was extended and the machine was in a waiting state.

This is useful when the main memory is constructed using a mixture of memory elements with different response times, and the response time may vary depending on the address, or when the response time may vary each time the access is made due to a cache memory device, etc. It was noticeable.

[Purpose of the invention]

The purpose of the present invention is to continue microinstruction processing beyond the end of the main memory operation when writing data to the main memory, and if a microinstruction that starts a new main memory appears while the main memory is operating. For example, an object of the present invention is to provide a processing method that extends the machine cycle time and avoids main memory contention.

[Summary of the invention]

The present invention allows the execution of microinstructions to proceed regardless of the operating state of the main memory if the microinstruction after the microinstruction that starts writing to the main memory does not newly refer to the main memory.
When a new reference is made to the main memory, the machine cycle of the microinstruction that is about to be activated is extended until the operation of the main memory ends, thereby avoiding main memory contention.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a microinstruction execution control circuit in a conventional information processing device.

Microinstructions are stored in microinstruction memory 1. The address indicated by the micro-address register 2 is read from the micro-instruction memory 1 and set in the micro-instruction register 3. The micro address register 2 is set to the value of the next address by the adder 4. The microaddress register 2 and microinstruction register 3 are updated by a synchronization signal 6 generated by a clock control circuit 5.

The clock control circuit 5 has a control input 7 of logic = 1.
If so, the periodic signal 6 is output at a constant period. When the control input 7 becomes logic 0'', the synchronization signal 6 is not output and is in a waiting state.The period from rise to rise of the synchronization signal 6 is called machine cycle time.

Microinstruction register 3 has read start bit 8.
and write activation bit 9. The outputs of these bits are logically summed by an OR gate 10 and input to a flip-flop 11. Flip-flop 11 outputs an activation signal for main storage device 13 to signal line 12 using synchronization signal 6 as a trigger.

Access to the main memory device 13 is activated via the signal line 12, and when the access is completed, an end signal is output to the signal line 14. Signal line 14 is connected to the reset input of flip-flop 11 and resets the activation signal on signal line 12.

Since the control input 7 is the inversion of the signal line 12, the control input 7 is logic while the main memory 13 is being accessed.
0”, extending the machine cycle time.

The relationship between these signals is shown in FIG. here,
#1, #2, . . . attached to the drawings indicate the numbers of corresponding microinstructions. In this figure, #1 is a microinstruction that requests activation of the main memory for writing or reading, and #2 to #4 are microinstructions that do not request activation of the main memory 13, such as registers (not shown). This is a microinstruction that requests an operation on the operands in (the arithmetic unit is not shown for simplicity). Further, C1 to C4 are machine cycle addresses. As can be seen from this figure, regardless of whether microinstruction #1 requests writing or reading from the main memory, the machine cycle C3 for the execution phase of that instruction continues until the operation of the main memory 13 is completed by subsequent microinstruction #1. 2 and subsequent steps are executed again.

As described above, in the conventional system, once the main memory is activated, the machine cycle time is extended until the access is completed, regardless of whether the next microinstruction refers to the main memory.

FIG. 3 shows an embodiment of the invention. The flip-flop 15 only remembers that it is a read activation,
Flip-flop 16 only remembers that it is write activated. The outputs 17 and 18 of each flip-flop and the access activation signal 19 form a control input 7 through an AND gate 20 and a NOR gate 21. When the output 17 is logic 〓1'', that is, in the case of read activation, the control input 7 is output by the NOR gate 21.
becomes logic = 0" and extends the synchronization signal 6. However, in the case of write activation, during write activation (output 18
is logic = 1") and there is a request to start the main memory after the microinstruction that started writing (the access activation signal 19 is logic = 1"), the control input 7 becomes logic = 0", Extend synchronization signal 6.

In other words, if it is a write activation, unless a subsequent microinstruction attempts to activate the main memory,
Processing of microinstructions can proceed.

FIG. 4 shows an example of a time chart when this embodiment is used. In the figure, #1 is a microinstruction that requests activation of the main memory 13 for writing, and #2 and #3 are processes other than activation of the main memory 13, such as operations on operands in registers (not shown). (The arithmetic unit for this is not shown for simplicity), #4
is a microinstruction that requests activation of main memory 13,
Here, it is assumed that this is a microinstruction that requests activation of the main memory 13 for reading. Further, #5 can be any type of microinstruction. Note that C1 to C6 are machine cycle numbers.

As can be seen from the figure, when microinstruction #1, which requests activation of main memory 13 for writing, is set in microinstruction register 2 at the rising edge of machine cycle C2, write activation bit 8 of this instruction is set to 1. Therefore, at the rise of the next machine cycle C3, flip-flop 1
1 and 16 are set. flipflop 11
The output signal 12 of becomes 1, and the main memory 13 is activated. At this time, write start bit 8 is set to main memory 1.
3, and notifies the main memory 13 that it is activated for writing. The data to be written is supplied from register 30, for example. Output 18 indicates that main memory 13 is being activated for writing, and is used to determine whether to extend the clock when executing a subsequent microinstruction. This write operation continues until the middle of main cycle C5. When the writing is completed, the main memory 13 sets the line 14 to "0", and the flip-flop 1
5 and 16 (in the present example, flip-flop 15 remains reset).

On the other hand, during execution of this write operation, when the next machine cycle C3 rises and microinstruction #2 that does not use main memory activation is set in the microinstruction register 3, the write activation flag 8 of this instruction is set to read activation. Since both flags 9 are assumed to be 0, the AND gate 20 remains closed and the output 7 of the NOR gate 21 remains 1.
No extension of the machine cycle will be made. In other words,
In this embodiment, when the preceding microinstruction #1 is an instruction to start writing to the main memory 13 and the following instruction #2 is a microinstruction that does not start the main memory, the clock is not extended.

In this way, execution of this microinstruction #2 is started at the rising edge of the next machine cycle C4. Similarly, the next microinstruction #3 is also started to be executed at the rising edge of the next machine cycle C5.

When the next microinstruction #4 is set in the microinstruction register at the rising edge of machine cycle C5, in this embodiment, the operation of the main memory 13 for the preceding instruction #1 is performed in the second half of machine cycle C5. Assuming it ends.

Therefore, when microinstruction #4 is set in microinstruction register 3, flip-flop 16 remains set. OR gate 1 due to write flag 9 of microinstruction #4
Since the output 19 of 0 becomes 1, the AND gate 20
The output of is 1, and the output 7 of the NOR gate 21 is 0.
becomes. In this manner, the clock control circuit 5 extends the clock when the subsequent microinstruction #4 requests activation of the main memory while the writing to the main memory for the microinstruction #1 is not completed.

When the end signal 14 is output from the main memory 13 in the latter half of the extended machine cycle #5 because the main memory write for microinstruction #1 is completed, the flip-flop 16 is reset and the clock extension is stopped. .

Thus, when the next machine cycle C6 rises after this predetermined time, flip-flops 11 and 15 open the read flag R in microinstruction #4.
8, it is set at the rise of machine cycle C6, and thereafter this microinstruction is executed.

As described above, in this embodiment, even during the execution of microinstruction #1 that activates the main memory for writing, subsequent microinstructions captured in microinstruction register 3 are processed as microinstructions #2 and #3. When main memory activation is not required, the clock is not extended. When a subsequent microinstruction requests main memory activation, such as microinstruction #4, the clock is extended until main memory activation for microinstruction #1 is completed.

Since microinstruction #4 is a main memory activation instruction for reading, flip-flop 15 in FIG. 3 is set at the rise of machine cycle C5, and its output 17 causes OR gate 21
The output 7 becomes 0, and the clock control circuit 5 extends the clock.

If the main memory is activated by writing in this manner, processing of microinstructions unrelated to the activation of the main memory can proceed without delay.

Additionally, if a main memory start request is made after the microinstruction that started the write during a write start, the main memory operation currently being executed will end within the machine cycle time of the microinstruction that attempted to start the main memory. By extending it to

〔Effect of the invention〕

According to the present invention, a microinstruction starts reading data from the main memory, and the execution of subsequent microinstructions is delayed until the main memory finishes reading data. If the instruction starts writing data to the main memory, even if the main memory does not finish writing, microinstructions after the started microinstruction will continue processing unless they try to start the main memory. can. Moreover, the above control can be realized by simple control of whether or not to extend the clock.

In addition, even if a microinstruction tries to newly start the main memory before the write that has started is completed, the machine cycle time of the microinstruction itself that is trying to start will be extended, and the system will wait until the write that is currently being executed ends. Therefore, there is no conflict in main memory access.

[Brief explanation of drawings]

Figure 1 shows an example of a conventional microinstruction execution control circuit.
FIG. 2 shows a timing chart of a conventional example, FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows a timing chart of an embodiment. 15...Flip-flop, 16...Flip-flop, 20...AND gate, 21...NOR
Gate.

Claims (1)

[Scope of Claims] 1. A main memory device, a microinstruction storage device, and a microinstruction reading circuit responsive to a clock that sequentially reads out the addresses of microinstructions to be read from the microinstruction storage device in each cycle of the clock. , a microinstruction register that responds to the clock and holds microinstructions sequentially read out from this microinstruction storage device in the cycle following the cycle in which they were each read out, and a microinstruction register that is sequentially held in this register. an execution circuit responsive to the clock for sequentially executing instructions in the cycle following the cycle in which each instruction is held; the microinstruction reading circuit for generating the clock; and the microinstruction register;
In an information processing device having a clock generation circuit for supplying an execution circuit, the microinstruction register responds to the clock signal in the cycle following the cycle in which the microinstruction is held in the microinstruction register, and the held microinstruction is It is set to the first state when it is the first microinstruction to access the storage device for data reading, and then responds to a signal indicating access completion supplied from the main storage device via a predetermined signal line. a first flip-flop that is reset to a second state by a first flip-flop; and a first flip-flop that responds to the clock signal in the cycle following the cycle in which the microinstruction is held in the microinstruction register, and that the held microinstruction is transferred to the main memory. It is set to the first state when it is a second microinstruction that accesses the device for writing data, and is then set to the first state in response to a signal indicating access completion provided from the main memory device via the signal line. a second flip-flop that is reset to state 2; and a second flip-flop that responds to the clock signal in the cycle following the cycle in which the microinstruction is held in the microinstruction register, and that the held microinstruction is transferred to the first microinstruction. or means for accessing the main memory when the second microinstruction is from the first flip-flop;
in response to an output from the second flip-flop indicating that it is set in the first state, instructing the clock generation circuit to then extend the clock; and a third microinstruction held in the microinstruction register after the second microinstruction that accesses the main memory for reading or writing, and then extending the clock. It tells the clock generation circuit what to do and after the second microinstruction even when an output is provided from the second flip-flop indicating that it is set to the first state. and a logic circuit that does not instruct extension of the clock when the microinstruction held in the microinstruction register is not a microinstruction that accesses the main memory for reading or writing.