JPS5938828A - Data processing system - Google Patents

Abstract

PURPOSE:To perform the starting processing in a high speed, by using a data transfer end signal for a synchronous external device but not using it for an asynchronous external device on a basis of information which discriminates whether the external device started by a processor is the synchronous or asynchronous device. CONSTITUTION:The system is operated in the synchronous transfer mode for a high-speed storage device 2. In response to a synchronous transfer request on a line 152 and a read/write indication on a line 155, the high-speed storage device 2 uses an address on an address bus 140 to perform the read/write in one machine cycle. The system is operated in the asynchronous transfer mode for a low-speed storage device 3. In response to an asynchronous signal transfer request on a line 153 and a read/write indication on the line 155, the low-speed storage device 3 performs the read/write in several machine cycles. After the read/write, the transfer end signal is outputted to a signal line 151 and is sent to a one-chip processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system having different types of external devices and processors.

In a data processing system consisting of multiple external devices connected to a common bus, such as storage devices and input/output devices, and a processor that transfers data to these devices, the termination of data transfer occurs when the processor executes a data transfer instruction. A signal (ACK) indicating this is sent from the external device to the processor. When the processor receives the ACK signal from the processor, it knows that the data transfer is complete and executes the next instruction. The reason why the external device notifies the processor of the end of data transfer is that the time from when the processor starts the data transfer until the external device responds and ends the data transfer is not constant. . For example, when a processor executes an instruction to transfer data to an input/output device, the data reception end time differs depending on the operating state of the eight-person output device at that time. Furthermore, when a dynamic memory is used as a storage device, the timing at which data transfer ends differs depending on whether or not the memory is performing a refresh operation. In the following, such an external device whose time from activation by the processor to completion of the activated operation is not constant will be referred to as an asynchronous external device. Therefore, conventionally, an ACK signal is sent from an asynchronous external device to the processor so that the processor can know when the data transfer ends.

On the other hand, some external devices, such as static memory, have a constant time from when data transfer is activated until it is completed. Hereinafter, such an external device will be referred to as a synchronous external device. If such a synchronous external device is configured to send an ACK signal to the processor at the end of data transfer in the same way as other asynchronous external devices according to the conventional method, all synchronous external devices will receive an ACK signal regardless of the type of external device. Since the ACK signal is sent to the processor, there is an advantage that only one circuit is required for detecting the end of data transfer for multiple external devices.However, with this method, the timing at which the ACK signal is output depends on the processor. Since it is not synchronized with the clock signal that controls the operation, a circuit is required to detect the ACK signal in synchronization with the clock signal, and this detection requires the inherent time delay required to synchronize so-called asynchronous signals. It has the disadvantage of being accompanied by

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing system that can speed up processing by a processor to start up a synchronous external device that is used together with an asynchronous external device.

The inherent delay described above for asynchronous external devices is necessary due to the nature of this type of external device. However, for synchronous external devices, it is not always necessary to send an ACK signal. Furthermore, although high-speed static memories that can be operated in one machine cycle of a processor have appeared in recent years, the above-mentioned method cannot fully utilize their high-speed performance.

Therefore, in the present invention, paying attention to the difference between the above two external devices, an ACK signal is used for the asynchronous external device,
We have invented a data processing system that does not use an ACK signal for synchronous external devices.

That is, in the present invention, means is provided for storing information that identifies whether or not an external device by the processor is a synchronous type, and when the stored identification information is for a synchronous type external device, a certain generates a signal to control the processor after a time period of Means for outputting the control information at different timings depending on the stored identification information is provided, such as outputting a signal.

Hereinafter, the present invention will be explained with reference to Examples.

An example of a system to which the present invention is applied is shown in FIG. This system consists of a one-chip processor, 1 degree high-speed storage device, and 2
．． Low speed storage device 3. It consists of an input/output device 4. Processor 1 and these devices share a common address bus 1401, a common data bus 141, and other control signal lines 151-1.
55.

The high-speed storage device 2 is capable of synchronous data transfer with the processor 1, but the low-speed storage device 3. Since the input/output device 4 has a slow operating speed, it performs asynchronous data transfer with the processor 1.

Further, data transfer between the low-speed storage device 3 and the processor 1 can be broadly divided into data transfer other than machine language instructions and fetch of machine language instructions. The former is performed using the input/output data register (FIG. 2, 41), while the latter is performed via the machine language instruction register (FIG. 2, 44).

Therefore, even if the data transfer command is directed to the same low-speed storage device 3, it is desirable to control the execution of the data transfer by distinguishing whether the command is for normal data or a machine language instruction. Furthermore, in this example,
As will be described later, starting data transfer to the low-speed storage device 3 and starting transferring 10 data to the input/output device 4 are performed using separate signal lines. This allows 31 low-speed storage devices to access the output device 4 without increasing the number of address bits. Because of these various transfer types, four transfer modes are used in this embodiment.

1) Synchronous transfer mode This indicates synchronous data transfer to and from the high speed storage device 2.

2) Asynchronous transfer mode This indicates asynchronous data transfer to and from the low-speed storage device 3.

3) I10 Transfer Mode This indicates the asynchronous transfer of I10 data to and from the input/output storage device 4.

4) Instruction Fetch Mode This indicates asynchronous instruction fetching from slow storage 3.

It should be noted here that in cases 3) and 4), as in case 2), data is transferred asynchronously, and for the sake of explanation, a different mode name from 2) is used. That's true.

Below are details of the example and (9) in these modes. The operation will be explained with reference to FIG.

The processor 1 consists of a control section, a calculation section, and an interface section. As shown in FIG. 2, the control section includes a microinstruction memory 10, a microinstruction address generation circuit 11, a microinstruction register 20. The arithmetic section consists of a micro-instruction decoding circuit 21 and a machine language instruction register 44, the arithmetic section consists of an arithmetic unit 3o and a group of arithmetic registers 31, and the interface circuit section consists of an address register 40 for holding addresses. a data register 41 that exchanges data with the device;
It consists of a transfer request circuit 57 that requests data transfer to each device and other circuits. In this embodiment, microinstructions are sequentially read out every machine cycle. The operation within each machine cycle is controlled divided into four timings To-'I'3.

Therefore, the clock To-T3 generated at these four timings is used. Timing T.

indicates the timing of reading the microinstruction, and T1 to T3 indicate the timing of execution of the read microinstruction.

(10) If the microinstruction read from the microinstruction memory 10 to the microinstruction register 20 at timing TO is a data transfer instruction, the microinstruction decoder 21 outputs a data transfer instruction decode signal 160. When the data transfer instruction decode signal 160 is output, the transfer mode data and read/write instruction data in the microinstruction register 20 are transferred to the line 12 at timing T1.
The transfer mode designation register 50 and the read/write designation register 51 are set via the signal 1.1.120, and the transfer execution display flip-flop 52 is set by the signal 160. At the same time, the contents of the register specified by the register specification field of the microinstruction register 20 among the calculation register group 31 are read out and sent to the address register 40 as an address via the internal node 130.
is set at timing T1 and sent to the address bus 140.

The relationship between the data transfer mode data and the transfer mode in this processor is as follows.

(11) The read/write instruction data is 1-bit data that is counted as 1.0 at the time of reading and commitment, respectively.

Transfer request circuit 57 decodes the output of transfer mode instruction register 50 and sends a corresponding request signal to one of the corresponding devices 2 to 4 from timing T1 until transfer execution flip-flop 52 turns off. That is, when the output of the transfer mode instruction register 50 is "00", a synchronous transfer request signal is sent to the high-speed storage device 2 via the line 152, and when the output is "01" or "11", an asynchronous transfer request signal is sent to the high-speed storage device 2 via the line 152. Send a transfer request signal to the low-speed storage device 3 via line 153, "10"
In this case, the I10 transfer request signal is output to the input/output device 4 via the line 154.

The read/write instruction is made by sending the output of the read/write instruction (12) register 51 as a read/write instruction signal to the devices 2, 3.4 via the line 155.

During storage, the output of the read/write instruction register 51 is O, and the output of the transfer execution display flip 70 knob 52 is 1. In response to these signals, the data output control circuit 55 turns on the output permission signal 163 at timing T1, and this signal 163 causes the data output circuit 42 to output the contents of the υ data register 41 to the data bus 141 at timing T1. .

Needless to say, the data register 41 is set with data to be written by the instruction executed in the previous machine cycle.

(Operation in synchronous transfer mode) When the storage is for the high-speed storage device 2, in response to the synchronous transfer request on the line 152 and the read/write instruction on the line 9155, the high-speed storage device 2 receives the data from the address bus 140. The data from the data node (141) is read into the address by the next timing TO, but no signal is returned to the processor 1 (13).

When the output of the register 50 indicates the synchronous transfer mode, the termination condition selection circuit 56 selects the clock TO 170 and outputs it as the clear signal 164 of the transfer execution display flip-flop 52.

The flip-flop 52 uses this signal to determine the timing TO.
Since the output permission signal 163 is cleared by the data output section 55, the output permission signal 163 is turned off, and the data output circuit 42 is prohibited from outputting data.

At the time of output, the high-speed storage device 2 transfers the data specified by the address on the address bus 140 to the data bus 141 at timing T3, based on the synchronous transfer request and read/write instruction on the lines 152 and 155. Output.

The selection circuit 54 responds to the outputs of the transfer mode instruction register 50 and the read/write instruction register 51, and selects the clock signal T0°170 when these outputs indicate reading in the synchronous transfer mode. and outputs it as a data register set signal 162. data bus 1
Read data on 41 (14) is selected by the data selection circuit 43 when the data register set signal 162 is on, and is set in the data register 41 at timing TO.

Therefore, in the synchronous mode, read data is set in the data register 41 at timing TO of the machine cycle following the machine cycle in which the microinstruction instructing data transfer was set in the register 20, so the next microinstruction is immediately executed. This data can be used.

(When a write operation is performed on the low-speed storage device 3 in the asynchronous transfer mode, the device 3 transfers the data on the data bus 141 to the address bus in response to an asynchronous signal transfer request on line 153 and a read/write instruction on line 155.) It takes several machine cycles to store the address in response to the address on 140, and then outputs an ACK signal to the common signal line 151.In the time chart of FIG. It is assumed that this occurs in

(15) When the output of the register 5o indicates a mode other than the synchronous transfer mode, the selection circuit 56 selects and outputs the ACK synchronization signal 156, which is the ACK signal 151 synchronized with the timing of the processor. It is configured. Therefore, the flip-flop 52 is reset at timing TO after the ACK signal 151 arrives. The data output circuit 42 is then prohibited from transmitting data, as in the synchronous transfer mode.

On the other hand, reading from the low-speed storage device 3 is also performed on line 15.
3,155.

As a result, for example, if data is read onto the data bus 141 at timing T3 of machine cycle 3 as shown in FIG. 3, the low-speed storage device 3 also outputs the ACK signal 151 at this time.

The selection circuit 54 is configured to select and output the ACK synchronization signal 156 when the output of the register 50.51 indicates reading in the asynchronous transfer mode or the I10 transfer mode. Therefore, data on the data bus 141 is set in the register 41 via the selection circuit (16) 43, for example, at timing To of machine cycle 5.

The ACK signal 151 is at the processor's internal timing TO~
Since it is not synchronized with T3, a circuit to synchronize it is required. This circuit will now be explained. ACK
Signal 151 is input to flip-flop 57 which is triggered at timing T2. The output signal 157 of the flip-flop 57 is converted into a timing signal T by an AND circuit 58.
It is ANDed with O170 and becomes the ACK synchronization signal 156.

The output signal 157 of the flip-flop 57 is further ANDed with the timing signal TO170 by the ACK signal 15.
1 and timing T2 are not synchronized, the output signal 157 of the flip-flop 57 may become uncertain, and in order to avoid this, the signal 157 is used after it is determined. Due to the above synchronization, for example, when data is read to the data bus at T3, although it would normally be possible to take in the data at timing To of the next machine cycle, it is delayed one machine cycle later (17 ) Data is captured at the timing TO. Here, it is assumed that the external device turns off the output of ACK and data after a certain period of time (data hold time) after the asynchronous transfer request signal 153 turns off.

(1) Operation in 10 transfer mode The operation in this case is the same as the operation in the asynchronous transfer mode.

(Operation in Instruction Fetch Mode) The activation of the low-speed storage device 3 at this time is performed in the same manner as in the asynchronous transfer mode described above.

The instruction fetch control circuit 53 outputs the ACK signal 151 as the instruction fetch signal 161 when the output of the register 50 indicates the instruction 7 fetch mode. The machine language instruction register 44 takes in the machine language instruction on the data bus 141 when the instruction fetch signal 161 is on, and sends it to the microinstruction address generation circuit 11.

When data transfer is started by the data transfer microinstruction, the transfer execution indicator 7 flip-flop (18) 52 is set and the transfer execution indicator signal 165 is output. This signal is connected to the microinstruction address generation circuit 11 and the microinstruction decoding circuit 21, and prohibits updating of the microinstruction address and execution of the microinstruction while this signal 165 is output. That is, when the transfer execution display signal 165 is output in the first phase (T1) of the processor timing, the microinstruction address generation circuit 11 points to the current microinstruction address and stops, and the microinstruction decoding circuit 21 The decoding of microinstructions is prohibited, and therefore their execution is also prohibited. If the transfer execution display signal 165 is not output at T□1, the microinstruction address generation circuit 11 generates the address of the next instruction of the microinstruction in the microinstruction register 20, and outputs the output signal of the microinstruction decoding circuit 21. The current microinstruction is then executed. In the synchronous transfer mode, the transfer execution indication flip-flop 52 (19) is cleared by the first clock TO of the next machine cycle of the data transfer microinstruction, so at the timing T1, the transfer execution indication signal 165. is not output and execution of the microinstruction is not stopped. In modes other than synchronous transfer, the transfer execution indication flip-flop 52 is not cleared and the transfer execution indication signal 165 remains output until the transfer is completed and the ACK signal 151 is output. The microinstruction address generation circuit 11 and the microinstruction decoding circuit 21 check the transfer execution display signal 165 at every timing T1, and restart execution of the microinstruction when the transfer is completed and this signal is cleared. Therefore, in synchronous transfer mode, operations can be performed using the transferred data in the machine cycle following the data transfer microinstruction; in other transfer modes, execution of the microinstruction is suspended until the transfer is completed, so the data It can also be easily interfaced with devices with slow transfer speeds.

The detailed configuration of the microinstruction address generation circuit 11 is described in the fourth section.
This will be explained using figures. Microinstruction address generation circuit 1
1 consists of a register 12 for holding a microinstruction address (20), a +1 circuit 13 for incrementing the address, a selector 14 for specifying a branch by a microinstruction, a branch by a machine instruction word, and others.

During normal instruction execution, the address held in the register 12 is set in the register 12 again via the +1 circuit 13 and selector 14, and then sent to the line 110 as the next instruction address.
to the microinstruction store 10 via the microinstruction store 10. When specifying a branch using a microinstruction, the microinstruction register 20
When the branch address signal 122 from the machine command register 44 is specified by a machine command word, the address signal 142 from the machine command register 44 is set in the register 12 via the selector 14. The 7 flip-flop 15 that controls the update of the microinstruction address is a level trigger flip-flop that is triggered at timing TO, and is designed so that the microinstruction address update clock signal 112 is not output when the output signal 111 is rOJ. There is. Therefore, if the signal 165 is "1" at the end of timing To, that is, at the start of timing T1 (21), the microinstruction address is not updated and remains pointing to the current address.

According to this embodiment, data transfer with the high-speed storage device is synchronous transfer, and data transfer with the low-speed storage device and input/output control device can be performed asynchronous transfer. Can be interfaced with pins.

Note that in the above embodiment, execution of the next microinstruction is stopped during data transfer, but this can be modified to
Subsequent microinstructions can also lock onto instructions that require data transfers and halt their execution.

According to the embodiments described above, it is possible to identify whether the external device activated by the processor is a synchronous type or not based on the transfer mode designation information included in the microinstruction. However, the present invention is not limited to such a case, but can also be applied to a system in which a different address is assigned to each external device, such as a normal microcomputer.
In that case (22), it is sufficient to use means for decoding which external device the address sent by the processor to the address bus is addressed to, and in that case, as in this embodiment, the transfer mode is specified by an instruction. There's no need. In addition, in such a microcomputer system, there is no need to provide a signal line for activating each external device for each external device as in this embodiment, and the address sent to each external device via the address bus is not necessary. What is necessary is to provide a decoder that decodes whether or not it indicates itself.

As described above, according to the present invention, the startup sequence of each external device can be performed using a method suitable for each device, so that performance such as data transfer speed does not deteriorate.

[Brief explanation of the drawing]

Figure 2 is a diagram in which the present invention is applied to a microprogram-controlled one-chip processor, Figure 1 is a wiring diagram of a computer system using the processor in Figure 2, and Figure 3 is a diagram of the data transfer of the processor in Figure 2. Time chart, 4th
The figure is a detailed block diagram of the microinstruction address generation circuit of the processor (23) shown in FIG. 40...Address register, 41...Data register, 42...Data output circuit, 43...Data selection circuit, 44...Machine instruction register, 50...Transfer mode instruction register, 51...・Read/write instruction register, 52...Transfer execution display flip-flop, 53
... Instruction fetch control circuit, 54 ... Read condition selection circuit, 55 ... Data output control circuit, 56 ... End condition selection (b) path, 57 ... Transfer request circuit, 160
...Data transfer instruction decode signal, 161...Instruction fetch signal, 162...Data register set signal, 163...Output permission signal, 164...Transfer execution display flip-flop clear signal, 165... Transfer execution display signal, 11... microinstruction address generation circuit,
21...Micro instruction decoding circuit, 151...A
CK signal, 156 (24) Figure 1 Certain Figure 2 [

Claims (1)

[Claims] 1. A processor that sequentially executes instructions, a first external device that is activated by the processor and completes a predetermined operation within a certain period of time after activation, and a second external device that is activated and sends a response signal indicating the end of the activated hindlimb operation to the processor when a certain period of time has elapsed; the processor is activated by a command; 1st. means for storing information identifying which one of the second external devices is the external device; and means for outputting signals for controlling the processor at different timings according to the stored identification information, the means for outputting signals for controlling the processor at different timings according to the stored identification information, If the response signal is for the first external device, after a certain period of time has passed since the activation of the hind limb, or when the response signal is received if the stored identification information is for the second external device. and a data processing system that outputs the control signal. 2. The output means provides instruction execution means within the processor,
2. The data processing system according to claim 1, wherein the data processing system outputs, as one of the control signals, a signal that permits the start of execution of the next instruction. 3. The output means includes a flip-flop that is set in response to a command to activate an external device, and a flip-flop that is set in response to a command to activate an external device, and a flip-flop that outputs the stored identification information from the first . selection means for switching and selecting a predetermined clock signal and the response signal depending on which of the second external devices they are directed to, and resetting the flip-flop according to the selected signal; 2. The data processing system according to claim 2, wherein the output of the clipflock at the time of reset is output as the permission signal. 4. The data processing system according to item 1, wherein the storage means is a means for extracting and storing the identification information included in a command for activating an external device. 5. The data processing system of clause 4, wherein the instruction is a microinstruction. 6. Said 1st. A second external device is connected to the first external device via a common data bus. each has a second storage device, and the output means switches and selects the predetermined clock signal and the response signal depending on whether or not the stored identification information is for the first storage device. comprising means for outputting the selected signal as one of the control signals,
6. The data processing system of any one of clauses 1 to 5, wherein the processor includes a data register that receives a signal on the data bus in response to the selected signal. 7. The second external device has another external device connected to the common data bus, and the second storage device and the other external device transmit the response signal therefrom to the processor. 6. The data processing system of clause 6, which is connected to a common signal line for input. 8. The data processing device of claim 6, wherein the certain time is less than or equal to one machine cycle of the processor. 9. The data processing device according to item 8, wherein the first storage device is a static type memory and the second storage device is a dynamic type memory.