JPS6375960A - logic LSI - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic LSI such as a microprocessor, and particularly to a bus control method suitable for realizing high-speed pass cycles.

[Conventional technology]

It is expected that the system configuration will be difficult with conventional microprocessors, etc. Upper logic LSIs are bus-connected to various devices with different access times? For this reason, an asynchronous bus control method has been introduced.The asynchronous bus control method uses bus communication between the logic LSI and the device to be accessed, and a shake hand method. . In the pass cycle, the logic LSI side first outputs an access address, and in the write cycle, it also outputs data. The accessed device side sends a bus cycle end signal to the logic LSI side to notify the timing of the end of one communication.

After receiving this signal, the el thick LSI reads data from the bus in the read cycle and completes the pass cycle. In this way, with asynchronous bus control, the accessed device writes data onto the bus. Before transmitting or receiving data from the bus, it is necessary to predict the end timing of the bus cycle in advance and send a bus cycle end signal to the logic LSI side.

FIG. 2 shows an example of a timing chart for bus control using this type of system, and FIG. 3 shows the configuration columns around logic L and 8114. In FIG.
ess "ia"d) signal indicates that the address output by the logic LSI has become valid, and 1) C (data
Kongry-1-: f)atB Complete)
The signal is a bus cycle end signal by a peripheral device.

This first device may be a 16-bit microcomputer 68000 or the like (problem to be solved by the invention).
! There was no consideration given to the generation delay of the signal, and even if the access time of the external device was speeded up, there was a problem that the bus cycle could not be speeded up due to the generation delay of the bus cycle end signal.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the extension of a bus cycle due to a delay in the generation of a bus cycle end signal, and to make it possible to realize a system configuration that takes advantage of the characteristics of a device that can be accessed at high speed.

[Handover to solve problems]

The above object is achieved by generating a bus cycle end signal within the chip when accessing a device capable of high-speed access.

[Effect]

It is common to place devices that can be accessed at high speed in a specific address space. Therefore, depending on whether the access address is within this specific address space, it can be determined whether a bus cycle end signal is generated within the chip. The internally generated bus cycle end signal may be ORed with the bus cycle end signal (generated by a peripheral device) input (from outside the chip) and input to a conventional asynchronous bus control circuit.

Malfunctions can be prevented by notifying the external device that the logic LSI has internally generated the bus cycle end signal.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained using gx diagrams.

The address space in which a bus cycle end signal is generated internally at the time of access is designated by area designation register l. Writing tH constant information to this register 1 is similar to the control registers such as the condition code register of a microprocessor.

Do it by command. The address space designated by register 1 is input to match detection circuit 2. - The number construction circuit 2 checks whether the access address 6 exists in the address space specified by the register 1. The access address 6 is a signal obtained by synchronizing the address 3 output from the chip at the time of memory access through the latch 5 with a control signal from the timing generation circuit 4. An example of the circuit configuration of the area specification register 1 and the match detection circuit 2.

This will be explained using FIG.

The area designation register 1 is composed of a register 7 for designating an address space and a mask register 8 for defining the validity of the valley bit designated by the register 7. If all bits in mask register 8 are set to @l", a signal indicating that the access address is within the specified area no matter what value is entered in address 6 (signal 9 is "1#")
is output. In this case, the bus cycle end signal is automatically generated inside the chip. On the contrary, mask register 8
If all bits in t-"0# are set, unless the access address 6 completely matches the value of the register 7, a signal 9=""0# indicating that it is outside the designated area is output. The area specification register 1 and the coincidence detection circuit 2 can be set in multiple bare sets, and in this case, the output 9 of the coincidence detection circuit 2
t- can be summarized using OR (0 几) logic. Further, this circuit configuration can also be realized with an associative memory.

- The output 9 of the scattering output circuit 2 is used to cause devices around the chip to deny that it is within the specified area.

SC of signal 10 (synchronous cycle 0:5yrxc
A bus cycle end signal (1)C (data complete) which is output as a (chronous cycle) signal to the outside of the chip and is the minimum bus cycle at the same time:
Data (::complete) is output as signal 11 in accordance with the timing of 13.

This signal 11 & 2 bus cycle end signal 13 and 0 logic are taken and input to the bus cycle Mj control circuit. Since the internal bus cycle end signal generating section of the present invention is connected in parallel with the externally configured bus cycle end signal f)C (13) generating section, a system configuration is adopted in which this DC signal 13 is generated only externally. It will not be an obstacle in any case.

FIG. 5 shows a timing chart when the bus cycle end signal is internally generated in this embodiment. The bus cycle is fixed to the minimum bus cycle, and the SC signal 10 indicating that the bus cycle is within the specified area is asserted.

〔Effect of the invention〕

According to the present invention, in communication with a device that can be accessed at a sufficiently high speed, a minimum bus cycle response is possible without externally generating a pass cycle end r signal. This will have the effect of speeding up data transfer, which determines the performance of logic LSIs.

[Brief explanation of the drawing]

jJc1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is an example of a timing chart of a bus cycle using a conventional asynchronous method, and FIG. 3 is an example of a configuration around a step for realizing bus control using a conventional asynchronous method. , FIG. 4 shows the main components of an embodiment of the present invention, and FIG. 5 is a timing chart of bus control according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Area designation register, 2...Address space single output circuit, 6...Access address, 10...Intra-area display signal, 13...Bus cycle end signal, 14
...Logic LSI, 15...Delay circuit, etc., 16.
17... Decoder, 18... Peripheral control device, etc., 19
...Various memories, 20...-data bus. 2nd mountain 2 coincidence detection circuit Figure 3 Figure 5

Claims (1)

[Scope of Claims] 1. In a logic LSI that performs bus control in an asynchronous manner, means for specifying a fixed address space, means for comparing the specified space with an access address, and access by this comparison. A bus control method characterized by having means for terminating a bus cycle in a minimum bus cycle only when an address is within a specified space, and means for notifying an outside of the chip that an access address is within a specified space. . 2. The bus control method according to item 1, wherein the address space is specified by an instruction executed by a logic LSI. 3. The bus control method according to item 1, characterized in that a plurality of designated address spaces can be set.