JPS59168547A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the conflict of a main memory by extending the machine cycle time of a microinstruction if said instruction which performs new start of the main memory during operation of the main memory is outputted. CONSTITUTION:An FF15 and an FF16 store only the reading start and the writing start respectively. The outputs 17 and 18 of the FF15 and 16 and an access start signal 19 produce a control input 7 through an AND gate 20 and an NOR gate 21. The input 7 is set at logic 0 by the gate 21 when the output 17 is set at logic 1, i.e., in a reading start mode. Thus a synchronizing signal 6 is extended. While the output 18 is set at logic 1 in a writing start mode. At the same time, the input 7 is set at 0 to extend the signal 6 only in case a start request for main memory is delivered (i.e., the access start signal 19 is se at 1) after a microinstruction which started the writing. Then the processing is advanced for the microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device using a microprogram control method.

[Prior art]

In conventional microprogram-based information processing devices, when writing data to the main memory, a microinstruction immediately after starting the write or after a specified step finishes the actual write to the main memory. Until then, the machine cycle time was extended and the machine was in a waiting state.

This occurs when the main memory is configured using a mixture of storage elements with different response times, and the response time varies depending on the address, or when the response time may vary each time a cache memory device is accessed. was noticeable.

[Purpose of the invention]

The purpose of the present invention is to continue microinstruction processing beyond the end of the main memory operation when writing data to the main memory, and if a microinstruction that starts a new main memory appears while the main memory is operating. For example, an object of the present invention is to provide a processing method that extends the machine cycle time and avoids main memory contention.

[Summary of the invention]

The present invention allows the execution of microinstructions to proceed regardless of the operating state of the main memory if the microinstruction after the microinstruction that starts writing to the main memory does not newly refer to the main memory. When a new reference is made to the main memory, the machine cycle of the microinstruction that is about to be activated is extended until the operation of the main memory ends, thereby avoiding main memory contention.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a microinstruction execution control circuit in a conventional information processing device.

Microinstructions are stored in microinstruction memory 1.

The address indicated by the micro-address register 2 is read from the micro-instruction memory 1 and set in the micro-instruction register 3. The micro address register 2 is set to address 1 by the adder 4. The microaddress register 2 and microinstruction register 3 are updated by a synchronization signal 6 generated by a clock control circuit 5.

If the input cuff of the clock control circuit is at logic "IN", it outputs the synchronization signal 6 at a constant cycle. When the input cuff becomes logic "0", the synchronization signal 6 is not output and the circuit goes into a waiting state. Here, the period from the rise of the synchronization signal 6 to the rise of the synchronization signal 6 is called machine cycle time.

The microinstruction register 3 has a read activation bit 8 and a write activation bit 9. The outputs of these bits are ORed by the OFL gate 10 and input to the flip 70 tube 11. The flip 70 knob 11 outputs an activation signal for the main storage device 13 to the signal line 12 using the synchronization signal 6 as a trigger.

Access to the main memory device 13 is activated via the signal line 12, and when the access is completed, an end signal is output to the signal line 14. Signal @14 is connected to the reset input of flip 70 knob 11 and resets the activation signal on signal line 12.

Since the control input cuff signal line 12 is inverted, the controller cuff is at logic "0" while the main memory 13 is being accessed, thereby extending the machine cycle time.

The relationship between these signals is shown in FIG.

In this way, in the conventional system, once the main memory is activated, the machine cycle time is extended until the access is completed, regardless of whether the next microinstruction refers to the main memory.

FIG. 3 shows an embodiment of the invention. 7 lip flop 1
5 stores only that it is a read activation, and the flip-flop 16 stores only that it is a write activation. The outputs 17 and 18 of the respective flip-flops and the access activation signal 19 are used to create a control cuff by an AND gate 20 and a NOR gate 21. When the output 17 is at logic "1#", ie, in the case of a read activation, the NOR gate 21 causes the locking cuff to go to logic "0", extending the synchronization signal 6. However, in the case of write start, during write start (output 18 is logic"
1"), and there is a request to start the main memory after the microinstruction that started writing (access start signal 19).
only when the signal is logic "1"), the input cuff becomes logic "0" and the synchronization signal 6 is extended.

In other words, if it is a write activation, the processing of the microinstruction can proceed as long as subsequent microinstructions do not attempt to activate the main memory.

FIG. 4 shows an example of a time chart when this embodiment is used.

If the main memory is activated by writing in this manner, processing of microinstructions unrelated to the activation of the main memory can proceed without delay.

Also, the microinstruction 1' that started the write during the write start
J. When there is a request to start main memory later, the machine cycle time of the microinstruction attempting to start main memory is extended until the main memory operation currently being executed is completed. can avoid conflicts.

〔Effect of the invention〕

According to the present invention, even if a microinstruction starts writing data to the main memory and the main memory does not finish writing, microinstructions subsequent to the activated microinstruction do not attempt to start the main memory. The process can continue for a limited time.

In addition, even if a microinstruction tries to newly start the main memory before the started write is finished, the machine cycle time of the microinstruction itself that is about to start will be extended, and the process will wait until the currently executing write ends. state, and there is no conflict in main memory access.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional microinstruction execution control circuit, FIG. 2 shows a timing chart of the conventional example, FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows a timing chart of the embodiment. 15...Flip-flop, 16...Flip-flop γ4 Ward

Claims (1)

[Claims] A microinstruction memory constituting a microinstruction execution circuit of a microprogram control system, a microaddress register that indicates the address of a predetermined microinstruction in the microinstruction memory, and a microinstruction instructed by the microinstruction register. A microinstruction register, a synchronous clock generation circuit that can suppress the generation of a synchronous clock based on a control input, a circuit that decodes a main storage activation request field in the microinstruction and outputs an activation request to the main storage device; In an information processing device comprising a main memory device that is activated by a activation request and outputs a termination signal when a predetermined access is completed, a flip-flop that separately stores successive activation requests and write activation requests of the main storage device; If reading is activated, the synchronous clock generation is inhibited by the control input of the synchronous clock generation circuit, and if writing is activated, the microinstructions after the microinstruction that requested the writing request main memory activation. An information processing apparatus comprising: a combinational circuit that does not input a clock suppression request to a side diagonal input of the synchronous clock generation circuit unless the synchronization clock generation circuit outputs a clock suppression request.