JP2002319281A - Magnetic memory and drive method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic memory and its drive method, in which data at the middle of processing can be saved easily and processing which is suspended can be restarted in a short time. SOLUTION: The magnetic memory, in which a magnetic resistance element storing and holding information utilizing variations of an electrical resistance value which depends on the magnetization direction of a magnetic material is included in a memory cell, has an address buffer circuit generating respectively a low address and a column address from an address signal for selecting a memory cell performing write-in or read-out of information, a row address latching circuit a row decoder provided with first non-volatile memory for temporarily holding a row address, and a column address latch circuit or a column decoder provided with second non-volatile memory for temporarily holding a column address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device having a plurality of memory cells for storing and holding information, and more particularly to a magnetic storage device having a magnetoresistive element whose electric resistance changes according to the magnetization direction of a ferromagnetic material. The present invention relates to a memory and a driving method thereof.

[0002]

2. Description of the Related Art Generally, a ferromagnetic material is magnetized by a magnetic field applied from the outside, and has a characteristic that magnetization remains even after the external magnetic field is removed (referred to as residual magnetization). The electric resistance of a ferromagnetic material changes depending on the direction of magnetization, the presence or absence of magnetization, and the like. Such a characteristic is called a magnetoresistance effect, and a change rate of the electric resistance value at this time is called a magnetoresistance ratio (Magneto-resistance ratio: MR ratio).

As a material having a large magnetoresistance ratio, GMR (Giant Magneto-Re
sistance) element and CMR (Colossal Magneto-Resista)
nce) elements are known. Specifically, Fe, Ni,
Co, Gd, Tb, or an alloy thereof, or La _X Sr
Complex oxides such as _1-X MnO ₉ and La _X Ca _1-X MnO ₉ are used.

By utilizing the residual magnetization of such a ferromagnetic material, it is possible to configure a nonvolatile memory that stores information depending on the magnetization direction and the presence or absence of magnetization. Such a nonvolatile memory is a magnetic memory ( MRAM: Magnetic Rando
m Access Memory).

In recent years, many magnetic memories that are being developed store information by utilizing the residual magnetization of the above-described ferromagnetic material, and detect and store a change in electric resistance value caused by a difference in magnetization direction. The method of reading the information obtained is adopted. As a method of magnetizing a ferromagnetic material, for example,
A write line through which a write current for generating a magnetic field flows is arranged near the ferromagnetic material, and information is stored and rewritten by changing the magnetization direction according to the direction in which the write current flows.

[0006] Recently, TMR (Tunnel Magneto-R) having a structure in which a tunnel insulating film is sandwiched between two ferromagnetic films is used.
esistance) element or MTJ (Magnetic Tunnel J)
Since the element has a high magnetoresistance ratio (MR ratio), it is expected to be the most practical device.

A magnetic memory having such a ferromagnetic material in a memory cell is expected to be used as a program memory for storing a program or a work memory for exchanging data with an MPU (Micro Processing Unit). Have been.

[0008]

When reading / writing information from / to the conventional magnetic memory as described above, usually,
As in the case of reading / writing information from / to a DRAM (Dynamic Random Access Memory), a driving method of randomly accessing a memory cell for storing information is employed. In such a driving method, when the arithmetic processing by the MPU or the like is stopped, the processing for temporarily saving the data being calculated to the memory cell array is performed, and then the operation is completed. That is, when the arithmetic processing is stopped, it is necessary to store the data to be saved and its address information in the memory cell array.

Therefore, when restarting the arithmetic processing,
Since data stored in the memory cell array and its address information need to be read from the memory cell array,
There is a problem that it takes a long time to restart the processing from the time of stopping.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and can easily save data in the middle of processing, and can shorten the stopped processing. It is an object of the present invention to provide a magnetic memory that can be restarted in time and a driving method thereof.

[0011]

In order to achieve the above object, a magnetic memory according to the present invention comprises a memory cell having a magnetoresistive element for storing and holding information by utilizing a change in an electric resistance value according to a magnetization direction of a magnetic material. An address buffer circuit for respectively generating a row address and a column address from an address signal for selecting a memory cell for writing or reading information, and a second memory for temporarily holding the row address. The configuration includes a row address latch circuit including one nonvolatile memory and a column address latch circuit including a second nonvolatile memory for temporarily holding the column address.

[0012] Alternatively, a magnetic memory provided with a magnetoresistive element for storing and holding information by utilizing a change in electric resistance depending on the magnetization direction of a magnetic material, wherein the memory cell for writing or reading information is used. An address buffer circuit for generating a row address and a column address from an address signal for selection, respectively, and a first nonvolatile memory for temporarily holding the row address are provided. A row decoder for generating a signal for supplying a predetermined voltage or current to the memory cell, and a second nonvolatile memory for temporarily holding the column address, and decoding and selecting the column address. And a column decoder for generating a signal for supplying a predetermined current to the selected memory cell. It is.

At this time, the first nonvolatile memory and the second nonvolatile memory store information in a memory cell for storing and holding information by utilizing a change in an electric resistance value according to a magnetization direction of a magnetic material. A magnetoresistive element for storing and holding may be provided.

[0014] Further, an input / output data latch circuit provided with a third non-volatile memory for temporarily storing information to be written or read may be provided. The memory cell for storing and holding information may include a magnetoresistive element for storing and holding information by utilizing a change in electric resistance depending on the magnetization direction of the magnetic material.

In the magnetic memory configured as described above,
A first nonvolatile memory for temporarily storing a row address in a row address latch circuit or a row decoder;
Since the column address latch circuit or the column decoder is provided with the second nonvolatile memory that temporarily holds the column address, it is possible to easily save the address corresponding to the data being processed to the magnetic memory.

Further, since the third non-volatile memory for temporarily storing information to be written or read to the input / output data latch circuit is provided, it is possible to easily save data in the process of being processed to the magnetic memory. become.

On the other hand, the driving method of the magnetic memory of the present invention is as follows.
A method for driving a magnetic memory for writing or reading information to or from a magnetic memory as described above, wherein the row address and the column address are respectively generated from an address to which data being processed is written, The row address is recorded in a memory and the second
The column work is recorded in the non-volatile memory, the processing operation is stopped, and the data corresponding to the addresses recorded in the first non-volatile memory and the second non-volatile memory are first stored when the processing operation is restarted. This is a method of reading data.

Alternatively, there is provided a method for driving a magnetic memory for writing or reading information to or from the above-described magnetic memory, wherein data being processed is recorded in the third nonvolatile memory, and the processing operation is stopped. In this method, data recorded in the third nonvolatile memory is first read out when the processing operation is restarted.

In the method of driving a magnetic memory as described above,
The row address is recorded in the first non-volatile memory and the column address is recorded in the second non-volatile memory to stop the processing operation, and the addresses recorded in the first non-volatile memory and the second non-volatile memory By reading the data corresponding to the first time when the processing operation is restarted, desired data can be immediately accessed when the processing is restarted.

Similarly, the data being processed is recorded in the third non-volatile memory, the processing operation is stopped, and the data recorded in the third non-volatile memory is first read out when the processing operation is resumed. Desired data can be immediately accessed when the processing is restarted.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one configuration example of the magnetic memory of the present invention, and FIG. 2 is a circuit diagram showing one configuration example of the memory cell array shown in FIG. FIG. 3 is a diagram showing the structure of the magnetoresistive element shown in FIG. 2, and FIG. 3 (a) is a cross-sectional view showing an example in which the magnetization direction is horizontal to the magnetic layer surface.
FIG. 2B is a cross-sectional view showing an example in which the magnetization direction is perpendicular to the magnetic layer surface. FIG. 4 is a graph showing an example of the magnetization characteristics of the ferromagnetic material shown in FIG. FIG. 5 is a circuit diagram showing one configuration example of a first nonvolatile memory and a second nonvolatile memory included in the row address latch circuit and the column address latch circuit shown in FIG. 1. FIG. FIG. 11 is a circuit diagram showing a configuration example of a third nonvolatile memory included in the input / output data latch circuit shown in FIG.

As shown in FIG. 1, the magnetic memory of the present invention comprises a memory cell array 1 comprising a plurality of memory cells,
An address buffer circuit 2 that generates a column address and a row address of a memory cell to which data is written / read based on an externally input address signal, and temporarily holds a row address output from the address buffer circuit 2 Row address latch circuit 3
And a column address latch circuit 4 for temporarily holding a column address output from the address buffer circuit 2.
And a row decoder 5 that decodes a row address held in the row address latch circuit 3 and generates a signal for supplying a predetermined voltage or current to a word line and a write line described later. A column decoder 6 that decodes the held column address and generates a signal for supplying a predetermined current to a bit line described later, and a data interface circuit 7 that is an interface for writing / reading data with the outside.
And a data interface circuit 7 or an input / output data latch circuit 8 for temporarily holding data passed from the memory cell array 1.

As shown in FIG. 2, the memory cell array 1
Is a MOS type field effect transistor (hereinafter simply referred to as MOS
For example, the transistors T11 to T44 connected in series to the MOS transistors T11 to T44.
A memory cell is configured by the magnetoresistance elements R11 to R44 formed of MR elements, and the memory cells are arranged in a matrix. Note that FIG.
Although the configuration of the row 4 column is illustrated, the actual memory cell array 1 has a configuration having more memory cells.

As shown in FIG. 2, for each column of memory cells arranged in a matrix, word lines WL1 to WL
4, and write lines WriteL1 to WriteL4 through which a write current flows for magnetizing the ferromagnetic films of the magnetoresistive elements R11 to R44 in a predetermined direction. The gates of the MOS transistors T11 to T44 are connected to the word lines WL1 to WL4, respectively. Further, the write lines WriteL1 to WriteL4 are arranged at positions close to the magnetoresistive elements R11 to R44, respectively.

On the other hand, bit lines BL1 to BL4 are provided for each row of the memory cells arranged in a matrix. One end of each of the magnetoresistance elements R11 to R44 of each memory cell is connected to the bit lines BL1 to BL4, and the other ends of the magnetoresistance elements R11 to R44 are connected to the drains of the MOS transistors T11 to T44, respectively.
The sources of the MOS transistors T11 to T44 are each grounded.

The first switching transistors Tb1 to Tb1 for connecting the bit lines BL1 to BL4 to the ground potential at the time of data writing are connected to the bit lines BL1 to BL4.
Tb4, sense amplifiers SA1 to SA4 for reading data held in the magnetoresistive elements R11 to R44,
The second switching transistors Ts1 to Ts4 for connecting the bit lines BL1 to BL4 and the sense amplifiers SA1 to SA4 when reading data are connected.

When writing information into the memory cell array 1 having such a configuration, the first switch transistor of the bit line corresponding to the memory cell to be written is turned on, and the magnetization of the ferromagnetic film is applied to the bit line. An auxiliary current is supplied in a direction parallel to the easy axis. In such a state, a write current is supplied to the corresponding write line in a direction perpendicular to the easy axis of magnetization of the ferromagnetic film, and the ferromagnetic film of the magnetoresistive element is magnetized in a predetermined direction, so that different binary values are obtained. The information is recorded as binary data by setting one of the resistance values.

On the other hand, when reading information from the memory cell array 1, a predetermined bias voltage is applied to the word line to turn on the MOS transistor, and a current flowing from the corresponding bit line to the magnetoresistive element is detected. Is obtained, and the recorded data is reproduced from that value.

As shown in FIGS. 3A and 3B, the magnetoresistive elements R11 to R44 of the memory cell include a first ferromagnetic film 11 having a large coercive force and a second strong magnetic film having a small coercive force. Magnetic film 13 and tunnel insulating film 1 sandwiched between them
2 and has different electric resistance values depending on whether the magnetization directions of these two ferromagnetic films are the same or opposite. For example, when the magnetization directions of the first ferromagnetic film 11 and the second ferromagnetic film 13 are the same (parallel), the resistance value becomes low, and the first ferromagnetic film 11 and the second ferromagnetic film 13 have the same resistance. When the magnetization direction of the film 13 is opposite (anti-parallel), the resistance value becomes high.

The first ferromagnetic film 11 and the second ferromagnetic film 13 are magnetized by a magnetic field H applied from the outside, and their coercive force M has a hysteresis characteristic curve as shown in FIG. Becomes Because of having such magnetization characteristics, the first ferromagnetic film 11 and the second ferromagnetic film 13
Can maintain one of the two magnetization directions even when the external magnetic field H is zero.

Therefore, the memory cell array 1 shown in FIG. 2 has "1", depending on the two magnetization directions of the ferromagnetic film.
The present invention can be used for a nonvolatile memory capable of recording binary data “0”. Note that the magnetization direction of the ferromagnetic film is a horizontal magnetization element oriented in a direction parallel to the magnetic layer surface as shown in FIG. 3A and a direction perpendicular to the magnetic layer as shown in FIG. And a perpendicular magnetization element facing the same.

Further, in the magnetic memory of the present invention, as shown in FIG. 1, the row address latch circuit 3 and the column address latch circuit 4 include a nonvolatile memory cell having the number of bits of the column address or the row address. 1 of the non-volatile memory 9 _1, a configuration having a second non-volatile memory 9 _2. Further, the input / output data latch circuit 8 includes a third nonvolatile memory 10 composed of nonvolatile memory cells for the number of bits of data to be written / read. The first nonvolatile memory 9 ₁ and the second non-volatile memory 9 _2, the row address latch circuit 3 and the column address latch circuit rather than 4, may have a row decoder 5 and the column decoder 6.

As shown in FIG. 5, the row address latch circuit 3 and the column address latch circuit 4 first non-volatile memory 9 ₁ and the second non-volatile memory 9 ₂ included in, for example, shown in FIG. 2 memory This is a configuration using a magnetoresistive element as in the cell array 1, and has MOS transistors T1 to T1.
A memory cell including T4 and magnetoresistive elements R1 to R4 connected in series to the MOS transistors T1 to T4;
A word line WL10 provided in the column direction of the memory cell shown in FIG.
And a write line Wr through which a write current flows for magnetizing the ferromagnetic films of the magnetoresistive elements R1 to R4 in a predetermined direction.
itemL10 and address lines ADD1 to ADD1A provided in the row direction of the memory cell shown in FIG.
DD4 and address lines ADD1 to ADD1 during data writing.
A first switching transistor Tb11 to Tb14 for connecting ADD4 to the ground potential;
To R4, the sense amplifiers SA11 to SA14 for reading the data stored in the address lines ADD1 to ADD4 and the sense amplifiers SA11 to SA1 for reading the data.
4 is connected to the second switching transistor Ts11-Ts11.
Ts14.

The third non-volatile memory 10 included in the input / output data latch circuit 8 shown in FIG. 6 has a configuration using a magnetoresistive element similarly to the memory cell array 1 shown in FIG. T20 and a magnetoresistive element R2 connected in series to the MOS transistor T20
0, a word line WL20 provided in the column direction of the memory cell shown in FIG. 6, to which a predetermined voltage is applied when reading data, and a ferromagnetic film of the magneto-resistance element R20 in a predetermined direction. A write line WriteL20 through which a write current for magnetizing the memory cell flows, a data line DT1 provided in the row direction of the memory cell shown in FIG. 6 through which a data signal flows, and the data line DT1 are connected to the ground potential at the time of data writing. A switching transistor Tb20 for reading the data stored in the magnetoresistive element R20, a second switching transistor Ts20 for connecting the data line DT1 and the sense amplifier SA20 when reading data. It is a structure which has.

The _first to third nonvolatile memories 9 ₁ to 10 shown in FIGS. 5 and 6 correspond to the memory cell array 1 composed of the memory cells of four rows and four columns shown in FIG.
Is shown, the actual nonvolatile memory has a configuration having more memory cells.

As described above, the magnetic memory of the present invention
Then, the row address latch circuit 3 or the row decoder 5
Non-volatile memo that temporarily holds the row address
Re 9 ₁And the column address latch circuit 4 or the color
A second temporarily storing the column address in the memory decoder 6.
Non-volatile memory 9_TwoData, the data being processed is
Address corresponding to data is easily saved to magnetic memory.
It becomes possible.

Similarly, a third memory for temporarily storing information to be written to or read from the input / output data latch circuit 8
, It is possible to easily save data in the process of being processed to the magnetic memory.

Therefore, when the processing operation is restarted, desired data is read and written immediately, and the processing operation can be restarted in a short time.

Next, a procedure for writing / reading information to / from the magnetic memory according to the present invention will be described with reference to FIGS.

FIG. 7 is a circuit diagram showing how data is written into the memory cell array shown in FIG. 2, and FIG. 8 is a circuit diagram showing how data is read from the memory cell array shown in FIG.

For example, when data is stored in the memory cell array 1 composed of memory cells of four rows and four columns shown in FIG. 2, an address for selecting a memory cell can be represented by a 4-digit binary number. That is, in the case of the memory cell array 1 shown in FIG. 2, a memory cell C11 composed of a MOS transistor T11 and a magnetoresistive element R11 (hereinafter, each memory cell is similarly matched to the reference numerals assigned to the MOS transistor and the magnetoresistive element). C11 to C44) are (0000). Similarly, memory cells C12, C13, C14, C21, C22, C2
3, C24, C31, C32, C33, C34, C4
The addresses of 1, C42, C43, and C44 are (000
0), (0001), (0010), (0011),
(0100), (0101), (0110), (011)
1), (1000), (1001), (1010),
(1011), (1100), (1101), (111)
0) and (1111).

First, the operation when data is input to the magnetic memory shown in FIG. 1 (writing to a memory cell) will be described. In the following, a case where data “1” is written to the memory cell C23 among a plurality of memory cells will be described as an example.

As described above, the address of the memory cell C23 is (0101).

The magnetic memory having the memory cell array 1 shown in FIG. 2 has four address terminals corresponding to four-digit addresses. Therefore, in this example, voltages (0, Vdd, 0, Vdd) corresponding to the address (0101) are supplied to the four address terminals. Further, a voltage of Vdd corresponding to the write data “1” is supplied to the data terminal in synchronization with the input of the address signal.

The address signal input from the address terminal is input to the address buffer circuit 2, and the address buffer circuit 2 generates a row address and a column address. The row address output from the address buffer circuit 2 is held by a row address latch circuit 3, and the column address output from the address buffer circuit 2 is held by a column address latch circuit 4. The write data input from the data terminal is transferred to the input / output data latch circuit 8 via the data interface circuit 7 and is held by the input / output data latch circuit 8.

The row address and the column address output from the address buffer circuit 2 are information for designating a memory cell into which data is to be written. In this case, the row address is a four-digit two-digit number for selecting the write line WriteL3.
Base number (0010) and the column address is bit line B
It is a 4-digit binary number (0100) for selecting L2.

The row address latch circuit 3 and the column address latch circuit 4 includes a first nonvolatile memory 9 ₁ and the second non-volatile memory 9 ₂ shown in FIG. 5, the row address and the column address is first Non-volatile memory 9 ₁
And they are respectively held in the second non-volatile memory 9 _2.
Further, the input / output data latch circuit 8 is provided with the third
The write data transferred from the data interface circuit 7 is held in the third nonvolatile memory 10.

The row address and the write data held in the row address latch circuit 3 and the input / output data latch circuit 8 are transferred to the row decoder 5, respectively. Also,
In synchronization with this, the column address held in the column address latch circuit 4 is transferred to the column decoder 6.

As shown in FIG. 7, the row decoder 5 selects a write line WriteL3 connected to the memory cell C23 to be written, and supplies the write line WriteL3 with a polarity corresponding to the write data via a buffer circuit (not shown). Supply write current. The column decoder 6 selects the bit line BL2 connected to the memory cell C23 to be written, and supplies a predetermined auxiliary current for writing information from one end of the bit line BL2 via a buffer circuit (not shown). At this time, the first switching transistor Tb2 is turned on, and the other end of the bit line BL2 is grounded.

Data "1" is written to memory cell C23 by a series of operations described above. The addresses and write data held in the row address latch circuit 3, the column address latch circuit 4, and the input / output data latch circuit 8 are not erased even when the power supply is stopped. Even if this is done, the information being accessed is retained.

Next, the operation when data is output from the magnetic memory shown in FIG. 1 (read from the memory cell) will be described. Hereinafter, a case where data is read from the memory cell C23 among a plurality of memory cells will be described as an example.

As described above, the address of the memory cell C23 is (0101).

The magnetic memory having the memory cell array 1 shown in FIG. 2 has four address terminals corresponding to four-digit addresses. Therefore, in this example, voltages (0, Vdd, 0, Vdd) corresponding to the address (0101) are supplied to the four address terminals.

The address signal input from the address terminal is input to the address buffer circuit 2, and the address buffer circuit 2 generates a row address and a column address. The row address output from the address buffer circuit 2 is held by a row address latch circuit 3, and the column address output from the address buffer circuit 2 is held by a column address latch circuit 4.

The row address and the column address output from the address buffer circuit 2 are information for specifying a memory cell from which data is read. In this case, the row address is a 4-digit binary number (00) for selecting the word line WL3.
10), and the column address is a 4-digit binary number (0100) for selecting the bit line BL2.

[0057] The row address latch circuit 3 and the column address latch circuit 4 includes a first nonvolatile memory 9 ₁ and the second non-volatile memory 9 ₂ shown in FIG. 5, the row address and the column address is first They are respectively held in the nonvolatile memory 9 ₁ and the second non-volatile memory 9 _2.

The row address held in the row address latch circuit 3 is transferred to the row decoder 5. In addition, the column address held in the column address latch circuit 4 is transferred to the column decoder 6 in synchronism therewith.

As shown in FIG. 8, the row decoder 5 includes a word line W connected to a memory cell C23 to be read.
L3 is selected, a predetermined bias voltage is supplied to the word line WL3 via a buffer circuit (not shown), and the MOS transistor T23 is turned on. Further, the column decoder 6
A bit line BL2 connected to the memory cell C23 to be read is selected, and a predetermined read current for reading information is supplied from one end of the bit line BL2 via a buffer circuit (not shown). At this time, the second switching transistor Ts2 connected to the bit line BL2 is turned on.
Let it. The sense amplifier SA2 compares the potential of the bit line BL2 with the reference voltage V _Ref . For example, when the potential of the bit line BL2 is higher than the reference voltage V _Ref , the sense amplifier SA2 outputs Vdd (power supply voltage). When the potential is lower than the reference voltage _VRef , 0 [V] (ground potential) is output. The output voltages Vdd and 0 [V] correspond to “1” and “0” of the binary data.

The voltage output from the sense amplifier SA2 is temporarily held by the input / output data latch circuit 8, and then output to the outside via the data interface circuit 7.

The data held in the memory cell C23 is read out by a series of operations described above. Further, since the addresses and write data held in the row address latch circuit 3, the column address latch circuit 4, and the input / output data latch circuit 8 are not erased even when the power supply is stopped, the operation is stopped during the read operation. Even if this is done, the information being accessed is retained.

Next, an embodiment of the magnetic memory of the present invention will be described. (First Embodiment) FIG. 9 is a side sectional view showing the structure of a memory cell of a first embodiment of the magnetic memory according to the present invention.

The magnetic memory of the first embodiment uses a TMR element having a structure in which a tunnel insulating film is sandwiched between two ferromagnetic films as a magnetoresistive element included in a memory cell. The TMR element uses a horizontal magnetization element in which the magnetization direction shown in FIG. 3A is parallel to the surface of the magnetic layer.

As shown in FIG. 9, in the memory cell of the first embodiment, a buried type element isolation region 20 made of SiO ₂ is formed on the surface of a p-type semiconductor substrate 19, and a switching element is provided between the element isolation regions 20. Is a structure in which a MOS transistor is formed.

The MOS transistor is a p-type semiconductor substrate 1
9, a source 21 and a drain 22, which are n-type diffusion layers, a gate insulating film 23 made of SiO ₂ formed between the source 21 and the drain 22, and a gate insulating film 23 formed on the gate insulating film 23. And a gate electrode 24 made of polysilicon. Note that a word line (not shown) is connected to the gate electrode 24.

The source 21 of the MOS transistor is connected to a ground line 27 made of AlSiCu via a contact plug 26 in which tungsten is embedded.
In addition, the drain 22 of the MOS transistor is connected to the drain transistor 22 through a contact plug 25 in which tungsten is embedded.
TM, which is connected to a local wiring 29 made of iN and has a laminated structure of Co / Al ₂ O ₃ / NiFe on the local wiring 29 via a lower electrode 30 made of AlSiCu.
An R element 31 is formed. A bit line 32 made of Ti / AlSiCu / Ti is formed on the TMR element 31 in the horizontal direction of FIG.
A protective layer 33 made of O ₂ is formed. Also, TM
Below the R element 31, a write line 28 through which a write current for horizontally magnetizing the TMR element 31 flows is provided in a direction orthogonal to the bit line 32.

A memory cell array 1 in which memory cells having such a structure are formed in 4 rows and 4 columns, and as peripheral circuits, an address buffer circuit 2, a row address latch circuit 3, a column address latch circuit 4, a row decoder 5, a column A magnetic memory having a decoder 6, a data interface circuit 7, and an input / output data latch circuit 8 is designed based on the 0.5 μm rule (the minimum possible dimension is 0.5 μm);
A test chip was prepared.

As a result of applying 0 V (ground potential) and 3.3 V (power supply voltage Vdd) from the outside to the fabricated test chip and inputting a 1 MHz clock signal to operate, 1-bit data is input. Output was confirmed.
In addition, it was confirmed that data input / output was possible immediately when the power was turned off and then restarted.

(Second Embodiment) FIG. 10 is a side sectional view showing the structure of a memory cell of a magnetic memory according to a second embodiment of the present invention.

As shown in FIG. 10, the memory cell of the magnetic memory of the second embodiment is GdFe / Al ₂ O ₃ / Gd
This is a configuration including a TMR element 34 which is made of a Fe laminated film and is a perpendicular magnetization element as shown in FIG. Further, the write line 28 is provided in the lateral direction of the TMR element 34, and has a structure in which a magnetic field is applied to the TMR element 34 in a vertical direction. The other configuration is the same as that of the first embodiment, and a description thereof will be omitted.

An operation test similar to that of the first embodiment was performed on the magnetic memory of the second embodiment having the memory cells shown in FIG. 10, and it was confirmed that both the read operation and the write operation were normal. .

[0072]

Since the present invention is configured as described above, the following effects can be obtained.

A second nonvolatile memory for temporarily holding a row address in a row address latch circuit or a row decoder and a second nonvolatile memory for temporarily holding a column address in a column address latch circuit or a column decoder , It is possible to easily save the address corresponding to the data being processed in the magnetic memory.

Further, since the third nonvolatile memory for temporarily storing information to be written or read to the input / output data latch circuit is provided, data in the middle of processing can be easily saved to the magnetic memory. become.

Therefore, when the processing operation is resumed, desired data is read and written immediately, and the processing operation can be resumed in a short time.

The row address is recorded in the first non-volatile memory and the column address is recorded in the second non-volatile memory to stop the processing, and the first non-volatile memory and the second non-volatile memory By reading out the data corresponding to the address recorded in the first time when the processing operation is restarted, desired data can be immediately accessed when the processing is restarted.

Similarly, the data being processed is recorded in the third non-volatile memory, the processing operation is stopped, and the data recorded in the third non-volatile memory is read out first when the processing operation is resumed. Desired data can be immediately accessed when the processing is restarted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a magnetic memory according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a memory cell array illustrated in FIG. 1;

3A and 3B are diagrams showing the structure of the magnetoresistive element shown in FIG. 2, wherein FIG. 3A is a cross-sectional view showing an example in which the magnetization direction is horizontal to the surface of a magnetic layer, and FIG. FIG. 4 is a cross-sectional view illustrating an example in which a magnetization direction is perpendicular to a layer surface.

FIG. 4 is a graph showing an example of the magnetization characteristics of the ferromagnetic material shown in FIG.

FIG. 5 is a circuit diagram illustrating a configuration example of a first nonvolatile memory and a second nonvolatile memory included in the row address latch circuit and the column address latch circuit illustrated in FIG. 1;

FIG. 6 is a circuit diagram showing a configuration example of a third nonvolatile memory included in the input / output data latch circuit shown in FIG. 1;

FIG. 7 is a circuit diagram showing how data is written in the memory cell array shown in FIG. 2;

FIG. 8 is a circuit diagram showing how data is read from the memory cell array shown in FIG. 2;

FIG. 9 is a side sectional view showing the structure of a memory cell included in the first embodiment of the magnetic memory of the present invention.

FIG. 10 is a side sectional view showing a structure of a memory cell included in a magnetic memory according to a second embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 memory cell array 2 address buffer circuit 3 row address latch circuit 4 column address latch circuit 5 row decoder 6 column decoder 7 data interface circuit 8 input / output data latch circuit 9 ₁ first nonvolatile memory 9 ₂ second nonvolatile memory 10 Third non-volatile memory 11 First ferromagnetic film 12 Tunnel insulating film 13 Second ferromagnetic film 19 P-type semiconductor substrate 20 Element isolation region 21 Source 22 Drain 23 Gate insulating film 24 Gate electrode 25, 26 Contact Plug 27 Ground line 28, WriteL1 to WriteL4 Write line 29 Local wiring 30 Lower electrode 31, 34 TMR element 32, BL1 to BL4 Bit line 33 Protective layer ADD1 to ADD4 Address line DT1 Data line R1 to R4, R11 to R44, R2 Magnetoresistance element SA1 to SA4, SA11 to SA14, SA20 Sense amplifier T1 to T4, T11 to T44, T20 MOS transistor Tb1 to Tb4, Tb11 to Tb14, Tb20 First switching transistor Ts1 to Ts4, Ts11 to Ts14, Ts20 2 switching transistors WL1 to WL4 Word line

Claims (7)

[Claims] 1. A magnetic memory having a magnetoresistive element in a memory cell for storing and holding information by utilizing a change in an electric resistance value according to a magnetization direction of a magnetic body, wherein the memory cell for writing or reading information is provided. An address buffer circuit for respectively generating a row address and a column address from an address signal for selection; a row address latch circuit including a first nonvolatile memory for temporarily holding the row address; And a column address latch circuit including a second non-volatile memory for temporarily storing data. 2. A magnetic memory comprising: a memory cell having a magnetoresistive element for storing and holding information by utilizing a change in an electric resistance value according to a magnetization direction of a magnetic material, wherein the memory cell for writing or reading information is provided. An address buffer circuit for respectively generating a row address and a column address from an address signal for selection; and a first nonvolatile memory for temporarily holding the row address. A row decoder for generating a signal for supplying a predetermined voltage or current to the memory cell, and a second nonvolatile memory for temporarily holding the column address, and decoding and selecting the column address. And a column decoder for generating a signal for supplying a predetermined current to the selected memory cell. Ri. 3. The first non-volatile memory and the second non-volatile memory store information in a memory cell for storing and holding information by using a change in an electric resistance value according to a magnetization direction of a magnetic material. 3. The magnetic memory according to claim 1, further comprising a holding magnetoresistive element. 4. The magnetic memory according to claim 1, further comprising an input / output data latch circuit including a third nonvolatile memory for temporarily storing information to be written or read. 5. The memory according to claim 3, wherein the memory cell for storing and holding information includes a magnetoresistive element for storing and holding information by using a change in an electric resistance value according to a magnetization direction of a magnetic material. The magnetic memory according to claim 4. 6. A method of driving a magnetic memory for writing or reading information to or from a magnetic memory according to claim 1, wherein the method comprises: Generating an address and a column address, recording the row address in the first non-volatile memory, and recording the column address in the second non-volatile memory, and stopping the processing operation; A method for driving a magnetic memory in which data corresponding to an address recorded in the volatile memory and the second nonvolatile memory is first read out when the processing operation is restarted. 7. A method for driving a magnetic memory for writing or reading information to or from a magnetic memory according to claim 4, wherein data being processed is recorded in the third nonvolatile memory. A method of driving a magnetic memory in which the processing operation is stopped to read the data recorded in the third nonvolatile memory first when the processing operation is restarted.