JP2006294178A - Nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory device which can simplify the read circuit configuration and read the data at high-speed. <P>SOLUTION: The data read circuit RDC has a current generator 191 to generate a reference current of 10% smaller based on the pass current which flows when reading the initial data, and a comparator 192 to compare the reference current generated by the current generator 191 and the pass current when writing the predetermined data in the memory cell. Since it is possible to decide the read data based on the comparison results of the comparator 192, it is not required to temporarily store the data in a memory area, such as in a register, and the circuit configuration can be simply built for the data read circuit RDC, and also the data can be read at high speed because there is no storing area. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device, and more specifically to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  In recent years, MRAM (Magnetic Random Access Memory) devices have attracted attention as a new generation of nonvolatile storage devices. An MRAM device is a non-volatile memory device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and can randomly access each of the thin film magnetic bodies. In particular, in recent years, it has been announced that the performance of MRAM devices will be dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell.

  In general, when reading data from a memory cell used as a memory element of these nonvolatile memory devices, the current flowing through the tunnel magnetoresistive element (TMR) and the voltage across the tunnel magnetoresistive element (TMR) are measured. This can be realized by indirectly measuring the resistance value of the tunnel magnetoresistive element (TMR).

  Here, when the resistance value of the tunnel magnetoresistive element (TMR) in the storage state with the data level “1” is R, and the resistance value of the tunnel magnetoresistive element (TMR) in the storage state of “0” is “R + ΔR”. The MR ratio defined by MR ratio = ΔR / R × 100 (%) is an index representing the operation margin of TMR, and preferably has a value of 10 to 20%.

  As an example of a read method of an MRAM device using such a tunnel magnetoresistive element (TMR) as a memory cell, a reference cell serving as a reference is arranged in a memory cell array in addition to a normal memory cell, and a comparison is made between the two. And a method of reading stored data. Specifically, the resistance value of the reference cell is fixed, and the resistance value in the storage state where the data level of the tunnel magnetoresistive element (TMR) constituting the memory cell is “1” and the resistance value in the storage state “0”. It is set to have an intermediate value. Reading of the stored data is performed by amplifying and converting the current flowing through the selected memory cell and the reference cell into a voltage and comparing the magnitudes of the voltages. If the voltage obtained from the memory cell is smaller than the voltage obtained from the reference cell, the memory state, ie, the data level, of the memory cell is “0”, and if it is greater, the memory state, ie, the data level, of the memory cell is “1”. In this example, the resistance value of the tunnel magnetoresistive element is described in relation to the storage state of the memory cell, that is, the data level corresponding to “0” and “1” for the high resistance state and the low resistance state. However, the data levels can be described in association with “1” and “0”, respectively.

  However, the tunnel magnetoresistive element (TMR) used for the memory element of the MRAM is composed of a very thin insulating film and a magnetic layer. Here, when the applied voltage is constant, the tunnel current passing through the insulating film, that is, the resistance value of the tunnel magnetoresistive element (TMR) varies exponentially with respect to its thickness. For example, if the thickness of the insulating film is increased or decreased by one atomic layer (2 to 3 mm), resistance value variation of 20 to 30% occurs.

  The variation in resistance value of the tunnel magnetoresistive element (TMR) becomes more prominent as the area of the tunnel magnetoresistive element (TMR) becomes smaller. Therefore, in the MRAM device described above, the memory cell storage state is “0”, for example, the tunnel magnetoresistive element has a high resistance state, but the voltage obtained from the memory cell is higher than the voltage obtained from the reference cell. There can be a growing problem. On the contrary, the memory state of the memory cell is “1”. For example, the resistance value of the tunnel magnetoresistive element is low, but the voltage obtained from the memory cell is smaller than the voltage obtained from the reference cell. May occur, which is a major factor that deteriorates the cell yield. That is, it is difficult to accurately set the reference voltage generated using the reference cell, and there is a problem that the data reading accuracy is lowered.

  In order to solve these problems, it is necessary to improve the tunnel film thickness manufacturing process in the memory cell and the reference cell.

  However, if tunnel film thickness accuracy in the manufacturing process is tightened, there is a concern about an increase in manufacturing cost due to a decrease in manufacturing yield. Against this background, there is a demand for a configuration for executing data reading based on the above-described resistance difference ΔR in the memory cell with high accuracy without causing a strict manufacturing process in the MRAM device.

  In order to solve such problems, a configuration has been proposed in which data reading is performed by a so-called self-reference method in which data reading is performed only by accessing a selected memory cell without using a reference cell.

  As a general self-reference read, one data read operation is continuously executed, (1) reading stored data from the selected memory cell, and (2) compulsory writing of “0” data to the selected memory cell. Data read after loading, (3) data read after forced writing to “1” data in the selected memory cell, (4) read data generation based on the read results of (1) to (3) above, And (5) read data rewrite (restore) to the selected memory cell. According to such a data reading operation, data reading can be executed only by accessing the selected memory cell, so that high-precision data reading can be executed regardless of manufacturing variations of the reference cell and the like.

In Japanese Patent Laid-Open No. 2003-257173, a current flowing through a selected memory cell selected in the first (first) data reading is detected, and a voltage controlled oscillator (VCO) generated corresponding to the current value is detected. Count the number of pulses at the pulse frequency. Then, the current flowing through the selected memory cell is detected in the second data reading after the forced writing of predetermined data, and the number of VCO pulses generated corresponding to the current value is counted. A self-reference MRAM device that generates read data by comparing the measurement results, that is, based on the comparison of the number of pulses measured by the first read and the second read is disclosed.
JP 2003-257173 A

  However, in the above self-reference method, the information read in the first data read is held in a register, and the information read in the second data read is held in another register, so that reading based on the comparison is performed. A method for generating data is shown.

  Therefore, in such a self-reference method, it is necessary to provide a register, a counter, and the like in the read circuit for generating read data, which complicates the configuration of the read circuit and is an obstacle to high-speed data reading. Become.

  The present invention has been made to solve the above-described problems, and provides a nonvolatile memory device capable of simplifying the circuit configuration of a reading circuit and executing high-speed data reading. For the purpose.

  Each of the nonvolatile memory devices according to the present invention includes a plurality of memory cells through which a passing current corresponding to stored data flows during data reading, and a selection selected as a data reading target among the plurality of memory cells during data reading. A current generation circuit that detects a passing current that flows in accordance with stored data through a memory cell and generates a reference current in which the ratio of the passing current is changed, a reference current generated by the current generation circuit, and a selection at the time of data reading And a comparison circuit that generates read data of the selected memory cell based on a comparison with a passing current that changes in accordance with stored data in the memory cell.

  Other nonvolatile memory devices according to the present invention each include a plurality of memory cells in which a passing current corresponding to stored data flows during data reading, and a selected memory cell selected as a data reading target among the plurality of memory cells. A data write circuit for applying a data write magnetic field to the memory and a selection that changes before and after the application based on the application of the data write magnetic field executed at least once in one data read operation A data read circuit for detecting a change in the state of the passing current flowing through the memory cell and generating read data based on the detected change in the state of the passing current;

  In another nonvolatile memory device according to the present invention, each of a plurality of memory cells through which a passing current corresponding to stored data flows at the time of data reading and a data reading target among the plurality of memory cells at the time of data reading are selected. A data line electrically coupled to a fixed voltage through the selected memory cell, a current supply circuit for coupling the data line with a predetermined voltage at least at the time of data reading and supplying a passing current to the selected memory cell, and a selection Data write circuit for applying data write magnetic field to memory cell and storage of selected memory cell before and after application of data write magnetic field executed at least once in one data read operation A data read circuit for generating read data based on the data. The data read circuit includes a reference current generation unit that generates a reference current by changing a predetermined ratio of a passing current that flows by data reading of a selected memory cell before application of a data write magnetic field, and after application of a predetermined data write magnetic field. A comparison unit that generates read data based on a comparison between a passing current that flows when data is read from the selected memory cell and a reference current.

  The nonvolatile memory device according to the present invention detects a passing current flowing according to stored data, generates a reference current in which the ratio of the passing current is changed, and a reference current generated by the current generating circuit. And a comparison circuit for generating read data of the selected memory cell based on a comparison with a passing current that changes in accordance with the stored data in the selected memory cell during data reading. Therefore, since the reference current is generated based on the passing current of the selected memory cell, it is possible to cope with the variation of the memory cell, and the read margin can be improved. Furthermore, since the comparison circuit generates read data based on the current comparison, it is not necessary to provide a register or the like for temporarily storing the read data obtained by data reading, and a simple read circuit can be configured. In addition, high-speed data reading can be performed.

  In addition, the nonvolatile memory device according to the present invention detects a state change of the passing current flowing through the selected memory cell that changes before and after the application based on the application of the data write magnetic field, and detects the state of the detected passing current. A data read circuit for generating read data based on the change. Therefore, the data read circuit generates read data in accordance with the passing current that flows based on the MR ratio of the selected memory cell, and therefore can perform data reading with a high read margin.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device shown as a representative example of a nonvolatile memory device according to Embodiment 1 of the present invention.

  As will be apparent from the following description, the application of the present invention is not limited to an MRAM device having an MTJ memory cell, but a memory cell in which a passing current (data read current) flows during data read. The present invention can also be applied to a nonvolatile storage device provided. In particular, this is effective for a device having a memory cell structure in which the resistance value variation among a plurality of memory cells is severe, that is, it is difficult to make the memory cells uniform.

  Referring to FIG. 1, an MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and MTJ memory cells MC (hereinafter simply referred to as memory cells) arranged in a matrix. A memory array 10 including an MC), a row selection circuit 20, and a column decoder 25. The row selection circuit 20 performs a row selection operation in the memory array 10 to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 performs a column selection operation of the memory array 10 to be accessed based on the column address CA included in the address signal ADD.

  The MRAM device 1 further includes read / write control circuits 30 and 35 provided on both sides of the memory array 10 for executing data writing based on input data DIN or data reading output to the outside as output data DOUT. Prepare. In the following, the binary high voltage state and low voltage state of signals, signal lines, data, etc. are also referred to as “H” level and “L” level, respectively.

  In addition, the rows and columns of the plurality of memory cells MC that are integrated and arranged in a matrix of the memory array 10 are also referred to as memory cell rows and memory cell columns, respectively.

  Memory array 10 further includes a plurality of word lines WL and digit lines DL provided corresponding to the memory cell rows, and a plurality of bit lines and a plurality of source lines SL provided corresponding to the memory cell columns, respectively. . Here, a bit line RBL used at the time of data reading and a bit line WBL used at the time of data writing are provided as the plurality of bit lines provided corresponding to the memory cell columns, respectively. FIG. 1 representatively shows one memory cell MC, and shows one word line WL and one digit line DL corresponding to each memory cell row of the memory cells MC. Also, bit lines RBL, WBL and source line SL are typically shown one by one corresponding to the memory cell column of memory cells MC.

  A transistor 95 for pulling down the digit line DL is provided in a region opposite to the row selection circuit 20 across the memory array 10. Note that the gate of the transistor 95 is electrically coupled to the power supply voltage Vcc. Based on the row selection instruction of the row selection circuit 20, the digit line DL is supplied with current from the fixed voltage Vss via the transistor 95. A path is formed.

  Here, the structure of the memory cell and the data storage operation will be described.

  FIG. 2 is a schematic diagram showing a configuration of a memory cell having a tunnel junction.

  Referring to FIG. 2, the memory cell includes a tunnel magnetoresistive element TMR whose electric resistance changes according to the data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between bit line BL and source line SL. Typically, a field effect transistor formed on a semiconductor substrate is applied as access transistor ATR.

  For memory cells, there are provided bit line WBL and digit line DL for flowing data write currents in different directions at the time of data writing, and word line WL for instructing data reading. At the time of data reading, in response to turn-on of access transistor ATR, tunneling magneto-resistance element TMR is electrically coupled between source line SL set to fixed voltage Vss and bit line RBL.

  FIG. 3 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.

  Referring to FIG. 3, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. A ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that is magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite (antiparallel) direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB and free magnetic layer VL.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electrical resistance of the tunnel magnetoresistive element TMR becomes the minimum value Rmin when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are parallel, and the magnetization directions of both are opposite (reverse) In the case of the (parallel) direction, the maximum value Rmax is obtained.

  At the time of data writing, word line WL is deactivated and access transistor ATR is turned off. In this state, a data write current (± Iw) for magnetizing free magnetic layer VL flows in a direction corresponding to the level of write data in each of bit line BL and digit line DL.

  FIG. 4 is a conceptual diagram showing the relationship between the data write current and the magnetization direction of the tunnel magnetoresistive element in data write.

  Referring to FIG. 4, the horizontal axis H (EA) represents a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and digit line DL, respectively.

  In the memory cell, the fixed magnetization direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL, and free magnetic layer VL is at the level of stored data (“1” and “0”). Accordingly, it is magnetized in the direction parallel to the fixed magnetization layer FL or in the antiparallel (opposite) direction along the easy axis direction. The memory cell can store 1-bit data (“1” and “0”) corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in the figure. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As indicated by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold required to change the magnetization direction along the easy axis is lowered. be able to.

  In order to rewrite the data stored in the memory cell, that is, the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to pass a data write current of a predetermined level or more to both digit line DL and bit line BL. Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is parallel to fixed magnetic layer FL or in the opposite (anti-parallel) direction according to the direction of the data write magnetic field along the easy axis (EA). Magnetized. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the memory cell is held in a nonvolatile manner until new data writing is executed.

  FIG. 5 is a conceptual diagram illustrating data reading from the MTJ memory cell.

  Referring to FIG. 5, at the time of data reading, access transistor ATR is turned on in response to activation of word line WL. The source line SL is set to a fixed voltage Vss. Thereby, tunneling magneto-resistance element TMR is electrically coupled to bit line RBL while being pulled down with fixed voltage Vss.

  Further, the bit line RBL is pulled up to a predetermined voltage, and the current path including the bit line RBL and the tunnel magnetoresistive element TMR is set to a level corresponding to the electric resistance of the tunnel magnetoresistive element TMR, that is, the data stored in the memory cell. The corresponding memory cell current Icell passes. Using this memory cell current Icell, that is, a passing current, stored data can be read from the memory cell as will be described later.

  FIG. 6 is a diagram showing the relationship (hysteresis characteristics) between the current for applying a magnetic field to the MTJ memory cell and the electrical resistance of the MTJ memory cell.

  Referring to FIG. 6, the horizontal axis indicates the bit line current I (BL) flowing through the bit line, and the vertical axis indicates the electrical resistance Rcell of the MTJ memory cell. The magnetic field generated by the bit line current I (BL) has a direction along the easy axis direction (EA) in the free magnetic layer VL shown in FIG. On the other hand, the magnetic field generated by the digit line current I (DL) flowing through the digit line DL has a direction along the hard axis direction (HA) in the free magnetization layer VL.

  Therefore, when the bit line current I (BL) exceeds the threshold value for reversing the magnetization direction of the free magnetic layer VL, the magnetization direction of the free magnetic layer VL is reversed and the memory cell resistance Rcell changes. In FIG. 2, when the bit line current I (BL) in the plus direction exceeds the threshold value, the memory cell resistance Rcell becomes the maximum value Rmax, and the bit line current I (BL) in the minus direction is reduced. When flowing beyond the threshold value, the memory cell resistance Rcell becomes the minimum value Rmin. The threshold value of the bit line current I (BL) varies depending on the current I (DL) flowing through the digit line DL.

  First, the hysteresis characteristic of the memory cell resistance Rcell when the digit line current I (DL) = 0 flowing through the digit line DL is shown by a dotted line in FIG. In this case, the threshold values of the bit line current I (BL) in the positive direction and the negative direction are respectively It0 and -It0.

  On the other hand, when a current flows through digit line DL, the threshold value of bit line current I (BL) decreases. In FIG. 6, the hysteresis characteristic of the memory cell resistance Rcell when the digit line current I (DL) = Ip is shown by a solid line. Due to the influence of the magnetic field in the hard axis direction caused by the digit line current I (DL), the threshold values in the positive direction and the negative direction of the bit line current I (BL) are It1 (It1 <It0) and −It1 (− It1> -It0). This hysteresis characteristic indicates the behavior of the memory cell resistance Rcell during the data write operation. Therefore, the bit line current I (BL) during the data write operation, that is, the data write currents + Iw and −Iw are set in the range of It1 <+ Iw <It0 and −It0 <−Iw <−It1.

  On the other hand, the bit line current I (BL) in the data read operation, that is, the data read current Is flows as a charge current for the data line DIO connected with the selected memory cell, parasitic capacitance, etc. as the RC load. Compared with the bit line current I (BL) at, that is, the data write current ± Iw, it is generally a level that is two to three orders of magnitude smaller. Therefore, in FIG. 6, it can be considered that the data read current Is≈0.

  In the state before data reading, the state (a) or (c) in FIG. 6, that is, the free magnetic layer in tunneling magneto-resistance element TMR so that the selected memory cell has either electric resistance Rmin or Rmax. The magnetization direction is set.

  FIG. 7 is a conceptual diagram illustrating the magnetization direction of the tunneling magneto-resistance element in each state shown in FIG. Here, the magnetization direction of the free magnetic layer VL is shown, and the relationship with the magnetization direction of the fixed magnetic layer FL is shown.

  FIG. 7A shows the magnetization direction in the state shown in FIG. In this state, since the magnetization direction of the free magnetic layer VL and the magnetization direction of the fixed magnetic layer FL are parallel, the memory cell resistance Rcell is set to the minimum value Rmin.

  FIG.7 (c) has shown the magnetization direction of the state in FIG.6 (c). In this state, since the magnetization direction of the free magnetic layer VL and the magnetization direction of the fixed magnetic layer FL are antiparallel (reverse direction), the memory cell resistance Rcell is set to the maximum value Rmax.

  From this state, when a predetermined current (for example, data write current Ip) is passed through digit line DL, the magnetization direction of free magnetic layer VL is not reversed, but is rotated to some extent, and tunnel magnetism is achieved. The electric resistance Rcell of the resistance element TMR changes.

  For example, as shown in FIG. 7B, when a predetermined bias magnetic field in the hard axis (HA) direction by the digit line current I (DL) is further applied from the magnetization state of FIG. 7A. The magnetization direction of the free magnetic layer VL is somewhat rotated to form a predetermined angle with the magnetization direction of the fixed magnetic layer FL. Thereby, in the magnetization state corresponding to FIG. 7B, the memory cell resistance Rcell increases from the minimum value Rmin to Rm0.

  Similarly, when the same predetermined bias magnetic field is further applied from the magnetization state of FIG. 7C, the magnetization direction of the free magnetic layer VL is somewhat rotated, and the magnetization direction of the fixed magnetic layer FL and the predetermined magnetic field Make an angle. Thereby, in the magnetization state corresponding to FIG. 7D, the memory cell resistance Rcell drops from the maximum value Rmax to Rm1.

  As described above, by applying a bias magnetic field in the hard axis (HA) direction, the memory cell resistance Rcell of the MTJ memory cell storing data corresponding to the maximum value Rmax is lowered, while corresponding to the minimum value Rmin. The memory cell resistance Rcell of the MTJ memory cell that stores data increases.

  As described above, the resistance value is changed from the maximum value Rmax by applying a predetermined bias magnetic field. Specifically, by applying a bias magnetic field in the hard axis (HA) direction, the memory cell resistance Rcell of the MTJ memory cell that stores data corresponding to the maximum value Rmax decreases from the maximum value Rmax to Rm1. . On the other hand, the memory cell resistance Rcell of the MTJ memory cell that stores data corresponding to the minimum value Rmin rises from the minimum value Rmin to Rm0 as described above.

  In this way, if a bias magnetic field in the hard axis direction is applied to an MTJ memory cell in which certain storage data is written, a change in electrical resistance having a polarity corresponding to the storage data is caused in the memory cell resistance Rcell. be able to. That is, the change in the memory cell resistance Rcell that occurs in response to the application of the bias magnetic field has a different polarity according to the stored data level.

  As described above, tunnel magnetoresistive element TMR changes its electric resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field. Therefore, tunnel magnetoresistive element TMR has an electric resistance Rmax / Rmin and a stored data By associating each level (“0” / “1”) with each other, nonvolatile data storage can be executed.

  FIG. 8 is a schematic configuration diagram of the memory array and its peripheral circuits according to the first embodiment of the present invention.

  Referring to FIG. 8, the memory array includes a plurality of divided memory blocks. In this example, a case where the memory block is divided into two memory blocks BK1 and BK2 will be described. Since the configurations of the two memory blocks are almost the same, the memory block BK1 will be mainly described here as a representative.

  Memory block BK1 includes a memory region 10a including memory cells MC arranged in a matrix. Memory region 10a includes a plurality of word lines WL and a plurality of digit lines DL provided corresponding to the memory cell rows as described above. In addition, it includes a plurality of bit lines RBL, WBL provided corresponding to the memory cell columns and a plurality of source lines SL, respectively. Bit line RBL is a bit line used for data reading, and bit line WBL is a bit line used for data writing.

  Memory cell MC includes a tunnel magnetoresistive element TMR whose electrical resistance changes according to the data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is directly connected to tunneling magneto-resistance element TMR between bit line RBL and source line SL. Typically, a field effect transistor formed on a semiconductor substrate is applied as access transistor ATR. For memory cell MC, there are provided bit line WBL and digit line DL for flowing data write currents in different directions at the time of data writing, and word line WL activated at the time of data reading. . In data reading, tunnel magnetoresistive element TMR is electrically coupled between fixed voltage Vss and bit line RBL in response to activation of word line WL, that is, in response to turn-on of access transistor ATR.

  Column decoder 25 includes an address signal line group ADL for transmitting an address signal, specifically column address CA, and a decode unit DCU provided corresponding to each memory cell column. The decode unit outputs a decode signal as a column selection result based on the transmitted column address CA. The column selection result is also input to the write driver control circuit 180.

  The row selection circuit 20 includes a row driver 80 arranged for each memory cell row, a transistor 90 provided between the word line WL and the row driver 80, and a transistor provided between the digit line DL and the row driver 80. 85. The gate of transistor 85 receives control signal WE. Transistor 90 has its gate receiving control signal RE. The row driver 80 is provided on one end side of the memory cell row and controls activation of the corresponding word line WL or digit line DL based on a row decode signal Rd indicating a decoding result of the memory cell row.

  Specifically, in response to a control signal RE (“H” level) output from control circuit 5 at the time of data reading, transistor 90 is turned on, and row driver 80 and word line WL are electrically connected. . Then, activation of the corresponding word line WL is controlled based on the row decode signal Rd. The row decode signal Rd is output as a row selection result based on the row address RA by the decode circuit of the row selection circuit 20 (not shown).

  On the other hand, in response to control signal WE (“H” level) output from control circuit 5 at the time of data writing, transistor 85 is turned on, and row driver 80 and digit line DL are electrically connected. The corresponding digit line DL is driven based on the row decode signal Rd. As described above, the other end side of the digit line DL is pulled down to the fixed voltage Vss by the transistor 95 being supplied with the power supply voltage Vcc. Therefore, data write current Ip is supplied to digit line DL based on row decode signal Rd.

  Read / write control circuit 30 includes a write driver control circuit 180. The write driver control circuit 180 operates in response to an operation instruction from the control circuit 5.

  In operation, the write driver control circuit 180 writes the write control signals WDTa and WDTb for each memory cell column in accordance with the input data DIN input to the data input terminal 4a via the latch 149 and the column selection result from the column decoder 25. Set. Further, write driver control circuit 180 receives read data from data read circuit RDC, which will be described later, and sets write control signals WDTa and WDTb within one data read operation period.

  Read / write control circuit 30 further includes a write driver WDVa provided for each memory cell column. Similarly, read / write control circuit 35 includes a write driver WDVb provided for each memory cell column.

  In each memory cell column, write driver WDVa drives one end side of corresponding write bit line WBL with either power supply voltage Vcc or fixed voltage Vss in accordance with corresponding write control signals WDTa and WDTb. Similarly, write driver WDVb drives the other end side of corresponding bit line WBL with either power supply voltage Vcc or fixed voltage Vss in accordance with corresponding write control signals WDTa, WDTb.

  At the time of data writing, write control signals WDTa and WDTb corresponding to the selected column are set to either “H” level or “L” level according to the level of write data. For example, write control signal WDTa is set to “H” level and WDTb is set to “L” level in order to flow data write current −Iw in the direction from write driver WDVa to WDVb. On the other hand, in order to flow data write current + Iw in the direction from write driver WDVb to WDVa, write control signal WDTb is set to “H” level, and WDTa is set to “L” level. In the following, data write currents + Iw and -Iw in different directions are collectively referred to as data write currents ± Iw.

  In the non-selected column, each of write control signals WDTa and WDTb is set to the “L” level.

  Therefore, in tunneling magneto-resistance element TMR in which data write currents Ip and ± Iw flow in both corresponding digit line DL and bit line WBL, the write data corresponding to the direction of data write current ± Iw is magnetic Written in. A similar configuration is similarly provided corresponding to the bit line WBL of each memory cell column. As will be described later, in the configuration of the present application, since the bit line WBL used at the time of data writing and the bit line RBL used at the time of data reading are independent from each other, data writing and data reading can be executed in parallel. Is possible.

  Next, a circuit group for performing a data read operation from the memory area 10a will be described.

  Read / write control circuit 30 is further provided corresponding to a data line DIO for forming a current path corresponding to the electric resistance of the selected memory cell, and a memory cell column, respectively. Data line DIO and each bit line And a read selection gate RCSG provided between RBLs. The gate of read selection gate RCSG receives input of read selection signal RCSL which is a decode signal which is a selection result of the memory cell column from corresponding decode unit DCU.

  When the corresponding memory cell column is selected, read select gate RCSG is turned on in response to read select signal RCSL ("H" level), and bit line RBL and data line DIO are electrically coupled. . A similar configuration is provided corresponding to each memory cell column. That is, the data line DIO is shared by each bit line RBL on the memory area 10a.

  With such a configuration, the selected memory cell is electrically coupled to data line DIO via bit line RBL of the selected column and corresponding read selection gate RCSG during data reading.

  Read / write control circuit 30 further includes a data read circuit RDC. Data read circuit RDC includes a current generation unit 191, a comparison unit 192, an amplifier 190, a latch 148, and an output buffer 193.

  The current generator 191 generates a predetermined constant current based on the current flowing through the data line DIO. The comparison unit 192 compares the predetermined constant current generated by the current generation unit 191 with the current flowing through the data line DIO, and outputs the comparison result.

  The amplifier 190 amplifies the signal output from the comparison unit 192 and outputs the amplified signal. The latch 148 holds the data amplified from the amplification unit 190. The output buffer 193 outputs the data held in the latch 148 as output data DOUT to the output terminal 4b.

  FIG. 9 is a circuit configuration diagram of current generation unit 191 and comparison unit 192 according to the first embodiment of the present invention.

  Referring to FIG. 9, current generation unit 191 according to the first embodiment of the present invention includes transistors 120 to 125 and switches 131 and 132.

  Transistors 120 and 121 are connected in series between power supply voltage Vcc and data line DIO. Transistor 120 has its gate receiving reference voltage Vref. Transistor 121 has a source electrically coupled to power supply voltage Vcc, and a gate and a drain electrically coupled to node N0. Transistor 122 is connected between node N0 and power supply voltage Vcc, and has its gate receiving control signal / PC. Transistor 123 is connected between power supply voltage Vcc and node N1, and has its gate connected to node N0. The transistor 124 is connected between the node N1 and the fixed voltage Vss, and its gate is connected to the node N1. Transistor 125 is connected in parallel with transistor 124 between node N1 and fixed voltage Vss, and has its gate connected to node N3. The nodes N1 and N3 are connected via the switch 132. The switch 131 is disposed between the node N0 and the node N2. The reference voltage Vref is a control voltage for adjusting the voltage level of the data line DIO to a predetermined voltage. Control signal / PC is set to “L” level before data reading, that is, when current generation unit 191 and comparison unit 192 are inactive. Thus, transistors 122 and 129 are turned on, and an “H” level voltage is applied to the gates of transistors 121, 123, and 129 in order to reduce leakage current, and transistors 121, 123, and 129 are turned off. Is set. On the other hand, at the time of data reading, control signal / PC is set to “H” level. As a result, the transistors 122 and 129 are turned off, and the current generator 191 and the comparator 192 are activated.

  Here, the transistors 121 and 123 form a current mirror circuit. The sizes of the transistors 124 and 125 are set to 1 W and 9 W, respectively. Therefore, the size ratio is 1 to 9.

  Comparison unit 192 includes transistors 127 to 129 and capacitors 126 and 130. The capacitor 130 is connected between the node N2 and the fixed voltage Vss. Transistor 129 is connected between node N2 and power supply voltage Vcc, and has its gate receiving control signal / PC. Transistor 128 is connected between power supply voltage Vcc and node N4, and its gate is connected to node N2. Transistor 127 is connected between node N4 and fixed voltage Vss, and its gate is connected to node N3. The capacitor 126 is connected between the node N3 and the fixed voltage Vss. The signal transmitted to node N4 is amplified by amplifier 190 and transmitted to latch 148.

  FIG. 10 shows that when reading data from a memory cell, when the tunnel magnetoresistive element TMR has a high resistance, the current is 10% smaller than the passing current flowing through the tunnel magnetoresistive element TMR (hereinafter also simply referred to as 10% smaller current) FIG. In the following description, the resistance value R + ΔR (Rmax) of the tunnel magnetoresistive element TMR will be described as a high resistance RH, and the resistance value R (Rmin) will be described as a low resistance RL.

  Referring to FIG. 10, when tunneling magneto-resistance element TMR has a high resistance (RH), for example, between power supply voltage Vcc and fixed voltage Vss via transistors 121 and 120, read selection gate RCSG and access transistor ATR. A current path is formed. If the current flowing through tunneling magneto-resistance element TMR at that time is I0, the current flowing through transistor 122 by the current mirror circuit is I0. Since the size ratio of the transistors 124 and 125 is 1: 9, the ratio of the currents flowing through them is 1: 9. Accordingly, 0.1I0 flows through the transistor 124. On the other hand, 0.9I0 flows through the transistor 125. The electric charge corresponding to the current amount of 0.9I0 is accumulated in the capacitor 126.

  FIG. 11 is a diagram illustrating a case where a current that is 10% smaller is generated when the tunnel magnetoresistive element TMR has a low resistance in reading data from a memory cell.

  In this case as well, if the current flowing through tunneling magneto-resistance element TMR is current I1, 0.1I1 flows through transistor 124. On the other hand, 0.9I1 flows through the transistor 125. Charge corresponding to the charge amount of 0.9I1 is accumulated in the capacitor 126.

  FIG. 12 is a flowchart illustrating a data read operation according to the first embodiment of the present invention.

  Referring to FIG. 12, in the configuration according to the first embodiment of the present invention, first, when the data read operation is started (step S1), the magnetization direction of the selected memory cell is set as the initial data read operation before the data read operation. The data reading is executed in the same state as that in FIG. 1, that is, in the state where the selected memory cell holds the storage data to be originally read (step S2).

  Next, current generation unit 191 detects a current flowing through data line DIO during the initial data read operation, and generates a current that is 10% smaller than the detected current (step S2 #). Specifically, the current 0.9I0 or 0.9I1 is generated as described in FIGS.

  Next, data ("0" data in this example) is written to the selected memory cell as a predetermined write operation (step S3). The resistance value of tunneling magneto-resistance element TMR is RH. Specifically, the selected memory cell receives a data write magnetic field for writing data of a predetermined level.

  Then, as a predetermined read operation, data reading for the selected memory cell is executed while writing data of the predetermined level “0” to the selected memory cell (step S4). In data reading according to the first embodiment of the present invention, data writing and data reading are executed in parallel in this case, so that high-speed data reading can be executed.

  Next, as a read confirmation operation, a 10% smaller current generated by reading stored data from the selected memory cell in the initial data read operation, and a current read in a state where “0” data is written by a predetermined write operation Based on the comparison, the read data RDT is determined (step S5).

  Next, it is determined whether or not the read data RDT determined in step S5 is the same as the data “0” written by the predetermined write operation (step S6).

  In step S6, when the data stored in the currently selected memory cell and the determined read data RDT do not match, the read data RDT is rewritten to the selected memory cell as a data rewrite operation. It is executed (step S7).

  As a result, for the selected memory cell that has received the predetermined data write in the read operation sequence, the stored data can be reproduced and restored to the state before the data read.

  On the other hand, if the data stored in the selected memory cell and the determined read data RDT are the same in step S6, the next data rewrite operation (step S7) is skipped and the data read operation is terminated. (Step S8). If both levels are the same, the data stored in the selected memory cell is already at the same level as the data (read data RDT) to be rewritten in the subsequent step S6 before the data rewrite operation is executed. Therefore, it is not necessary to execute the data rewriting operation. As a result, unnecessary rewrite operation can be omitted, and power consumption during data read operation can be reduced.

  FIG. 13 is a diagram illustrating the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “1” data. When “1” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RL.

  Referring to FIG. 13B, first, in the data read operation, current I1 flows through data line DIO based on resistance value RL as described in step S2. In this case, current generation unit 191 performs step S2 As described in #, −10% reference current is generated. Next, when “0” data is written by the predetermined write operation as described in step S3, the resistance value of the tunnel magnetoresistive element changes from RL to RH as shown in FIG. To do. On the other hand, in the predetermined data read operation described in step S4, as shown in FIG. 13B, the current value decreases from the current I1 to the current I0 as described above.

  Therefore, when the tunnel magnetoresistive element stores “1” data, the current value is set to a current I0 smaller than the reference current of −10%.

  FIG. 14 is a diagram illustrating the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. When “0” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RH.

  Referring to FIG. 14B, first, in the data read operation, current I0 flows through data line DIO based on resistance value RH as described in step S2. In this case, current generation unit 191 performs step S2 As described in #, a reference current of −10% is generated. Next, when “0” data is written by the predetermined write operation as described in step S3, the resistance value of the tunnel magnetoresistive element maintains the state of RH as shown in FIG. To do. Similarly, in the predetermined data read operation described in step S4, the current value maintains the state of current I0 as shown in FIG. Note that when the “0” data is written, the resistance value fluctuates because the data magnetic field (bias magnetic field) is applied to the free magnetic layer as described with reference to FIGS. This is because the magnetization direction is slightly inclined.

  Therefore, when the tunnel magnetoresistive element stores “0” data, the current value always takes a value larger than the reference current of −10% and does not become smaller.

  Therefore, by using this characteristic, read data can be determined using a reference current of -10% current. That is, as described in step S5, a current value that is −10% smaller generated by the initial initial data read operation is compared with the current from which “0” data is read. As a result, if the current for reading “0” data is smaller than the current value generated by the initial initial data read operation by −10%, the resistance value during the initial initial data read operation is RL, that is, the tunnel. That is, “1” data is stored in the magnetoresistive element. That is, the read data RDT is “1” data. On the other hand, if the current from which “0” data is read is larger than the current value that is −10% smaller generated by the initial initial data read operation, the resistance value at the initial initial data read operation is RH, that is, tunneling magnetism. That is, “0” data is stored in the resistance element. That is, the read data RDT is “0” data.

  Therefore, when read data RDT is “1” data, read data RDT (“1” data) and the write level (“0” data) of the predetermined write operation are not the same in step S6. In step S7, a data rewriting operation (write back) is executed. FIG. 13 and FIG. 14 also show the change when the write back is executed. As shown in FIG. 14, when the read data RDT is “0” data, it is not necessary to perform the data rewrite operation, so that the write operation is not actually performed and the current consumption can be reduced. .

  FIG. 15 is a timing chart diagram of the data read operation according to the first embodiment of the present invention.

  Referring to FIG. 15, in synchronization with the rise of clock signal CLK, data read operation is executed when control signals CS, WT, RD are set to “H” level at time T1. Then, the word line WL is activated and an initial data read operation is performed. Specifically, row decode signal Rd is input, and control signal RE is set to the “H” level. Along with this, the transistor 90 is turned on to activate the selected word line WL. Further, read selection signal RCSL is set to “H” level, selected read selection gate RCSG is turned on, and bit line RBL and data line DIO are electrically coupled. Accordingly, the bit line RBL is discharged to the fixed voltage Vss through the tunnel magnetoresistive element TMR while being precharged to the level of the reference voltage Vref−Vth (the threshold voltage of the transistor 120). Although not shown, the control signal / PC changes from the “H” level to the “L” level, and the current generation unit 191 and the comparison unit 192 are activated. Accordingly, a current path from the data read circuit RDC to the selected memory cell MC is formed. That is, as described above, the current (I0 or I1) corresponding to the resistance value (RH or RL) of the tunnel magnetoresistive element of the selected memory cell flows through the bit line RBL and the data line DIO.

  Then, the control signal EN1 is set to the “H” level. In response to this, in the current generator 191, the switch 132 is turned on, and a reference current of −10% flows through the transistor 125 as described above. Charge corresponding to this current is accumulated in capacitor 126, that is, the potential of node N3 is set to a potential corresponding to this current.

  Then, in synchronization with the next rise of the clock signal CLK, a predetermined write operation is executed at time T2. Specifically, a predetermined data write current for writing “0” data is applied to digit line DL and bit line WBL. At that time, the word line WL is activated and data reading is still executed. Therefore, data writing is executed in parallel while data reading is being executed. That is, control signal RE is set to “H” level and control signal WE is also set to “H” level. Therefore, transistor 85 is turned on in response to control signal WE (“H” level), and a data write current flows through selected digit line DL.

  Then, the control signal EN2 is set to the “H” level. On the other hand, the control signal EN1 is set to the “L” level. Therefore, the switch 132 is in the off state. In response to control signal EN2 (“H” level), switch 131 is turned on, and node N0 and node N2 are electrically coupled. In other words, the charge that causes the current I 0 to flow through the transistor 128 by the current mirror circuit is accumulated in the capacitor 130.

  On the other hand, as described above, the capacitor 126 stores the charge to flow the reference current of −10% to the transistor 127. The driving force to flow the current I0 and the reference current of −10% The potential of the node N4 is set based on the comparison with the driving force that tries to flow the current. Specifically, when the current of the initial data read operation is I1 due to amplification, the potential level of node N4 is set lower than when the current is I0. This is amplified by the subsequent amplifier 190 and latched by the latch 148 as read data RDT.

  When necessary as described above, that is, when the read data RDT is “1” data in the initial data read, the above-described write back is executed at time T4.

  The lower part is a diagram for explaining the operation of the block BK2. In this example, a data read operation similar to that of the block BK1 described above is performed from time T4. The details are not repeated.

  As described above, by using the method of the first embodiment of the present application, data reading in the self-reference method can be executed. Specifically, using the passing current based on the storage data read by the initial data reading operation, the reference current is generated by changing the ratio of the passing current, and the reading data is based on the comparison with the reference current. Is a method for determining Therefore, since the reference current is defined with reference to the passing current generated by the resistance value of its own memory cell, highly accurate data reading can be executed even when the resistance value of the memory cell varies. . In the data read circuit, the read data can be determined based on a comparison between the generated reference current and a passing current when predetermined data is written to the memory cell. It is not necessary to provide a storage area such as a register to store data. That is, the circuit configuration of the data read circuit can be easily configured and high-speed data read can be performed.

  In the configuration of the present application, a method has been described in which read data is determined based on comparison with a reference current that is −10% smaller than the passing current. However, the present invention is not limited to this. Of course, it is possible to determine the read data based on the comparison with the reference current as the current from the relationship between the resistance value and the passing current in FIGS.

  In the method of the present application, the case where the reference current is set to a current that is −10% smaller than the passing current has been described as an example. However, the present invention is not limited to this and can be changed to other ratios. However, since the MR ratio is 10% to 20% as described above, the ratio is adjusted so that the intermediate value of the passing current that changes with the high resistance and the low resistance becomes the reference current with the fluctuation of the MR ratio. Can do. For example, when the MR ratio is 30% and a passing current of about −15% is set, the size ratio of the transistors 124 and 125 is set to 3 to 17 in FIG. 9 described above. Is possible. Further, when setting the passing current of about −50% when the MR ratio is 50%, it is set by adjusting the size ratio of the transistors 124 and 125 in FIG. 9 described above. Is possible. In this example, the passing current of −10% is described as an example. However, the present invention is not limited to this, and the passing current may be set to −9% or −11% smaller by adjusting the transistor size ratio. Is possible.

(Embodiment 2)
FIG. 16 is a schematic block diagram of a memory array and its peripheral circuits according to the second embodiment of the present invention.

  Referring to FIG. 16, the difference from the configuration described in FIG. 8 is that write driver control circuit 180 is changed to write driver control circuit 180 #, and not read data RDT transmitted from latch 148. The difference is that the read data RDT transmitted from the amplifier 190 is input. Since the other points are the same as the configuration described in FIG. 8, detailed description thereof will not be repeated.

  In the second embodiment of the present invention, a data read operation that is faster than the data read operation described in the first embodiment will be described.

  FIG. 17 is a flowchart illustrating a data read operation according to the second embodiment of the present invention.

  Referring to FIG. 17, in the data read operation according to the second embodiment of the present invention, the data read operation is started (step S1), the initial data read operation (step S2) is performed in the same manner as described in FIG. A write operation (step S3) and a data read operation (step S4) are executed. Next, a read data determination operation is executed (step S5 #). Specifically, a comparison is made between a current that is 10% smaller generated by reading stored data from a selected memory cell in an initial data read operation and a current read in a state where “0” data is written by a predetermined write operation. Based on this, the read data RDT is determined. Specific determination operation will be described later. Then, it is determined whether or not the read data RDT determined in step S5 # is the same as the data “0” written by the predetermined write operation (step S6).

  In step S6, when read data RDT does not match data “0” written by the predetermined write operation, current inversion operation is performed so that “1” data is written to the selected memory cell. The direction is reversed (step S7 #).

  As a result, for the selected memory cell that has received the predetermined data write in the read operation sequence, the stored data can be reproduced and restored to the state before the data read.

  On the other hand, if the read data RDT is the same as the data “0” written in the predetermined write operation in step S6, the next current inversion operation (step S7 #) is skipped and the data read operation is performed. Is finished (step S8). If both levels are the same, the data stored in the selected memory cell is already at the same level as the data (read data RDT) to be rewritten in the subsequent step S6 before the data rewrite operation is executed. Therefore, it is not necessary to execute the current reversal operation. As a result, unnecessary write operations can be omitted and power consumption during data read operations can be reduced.

  FIG. 18 is a diagram illustrating the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “1” data. When “1” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RL.

  Referring to FIG. 18B, first, in the data read operation, current I1 flows through data line DIO based on resistance value RL as described in step S2. In this case, current generator 191 includes step S2 As described in #, a reference current of −10% is generated. Next, when “0” data is written by the predetermined write operation as described in step S3, the resistance value of the tunnel magnetoresistive element changes from RL to RH as shown in FIG. To do. On the other hand, in the predetermined data read operation described in step S4, as shown in FIG. 13B, the current value decreases from the current I1 to the current I0 as described above.

  FIG. 19 is a diagram illustrating the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. When “0” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RH.

  Referring to FIG. 19B, first, in the data read operation, current I0 flows through data line DIO based on resistance value RH as described in step S2. In this case, current generator 191 includes step S2 As described in #, a reference current of −10% is generated. Next, when “0” data is written by the predetermined write operation as described in step S3, the resistance value of the tunnel magnetoresistive element maintains the state of RH as shown in FIG. To do. Similarly, in the predetermined data read operation described in step S4, the current value maintains the state of current I0 as shown in FIG.

  Therefore, when the tunnel magnetoresistive element stores “0” data, the current value is always larger than the reference current of −10% and never decreases.

  Therefore, read data can be determined by using this characteristic as described above. In this regard, in the data read operation of the second embodiment, read data is determined using a reference current of −10% current. Specifically, the reference current of −10% current and the current from which “0” data is read are monitored. As a result, if the current from which “0” data is read is smaller than the current value generated by the initial initial data read operation, which is -10% smaller, the resistance value at the initial initial data read operation is RL, It can be determined that “1” data is stored in the tunnel magnetoresistive element.

  On the other hand, if the current from which the “0” data is read remains larger than the current value generated by the initial initial data read operation, which is smaller by −10%, the resistance value during the initial initial data read operation is RH. That is, it can be determined that “0” data is stored in the tunnel magnetoresistive element.

  In this regard, in the data read operation according to the first embodiment, after the predetermined write operation is completely completed, the read data determining operation, that is, the comparison operation between the current that is 10% smaller current and the current that has read the “0” data, that is, the read data RDT determination was being performed.

  In the second embodiment of the present application, this determination is performed while a predetermined write operation is being performed. Specifically, in step S6, if it is determined that the read data RDT is not the same as the write level (“0”) of the predetermined write operation, that is, the “0” data is smaller than the reference current smaller by −10%. If the read current is smaller, based on the determination result, the current reversal operation is executed as described in step S7 #. Specifically, the write driver control circuit 180 is instructed to reverse the direction of the current so as to write “1” data to the selected memory cell.

  FIG. 18 shows the change even when the current reversal operation (write back) is executed. As shown in FIG. 19, when the read data RDT is “0” data, it is not necessary to perform write back, so that the write operation is not actually performed, and the current consumption can be reduced.

  FIG. 20 is a timing chart diagram of a data read operation according to the second embodiment of the present invention.

  Referring to FIG. 20, data read operation is executed when control signals CS, WT, RD are set to “H” level at time T10 in synchronization with the rise of clock signal CLK. Then, the word line WL is activated and an initial data read operation is performed. Specifically, row decode signal Rd is input, and control signal RE is set to the “H” level. Along with this, the transistor 90 is turned on to activate the selected word line WL. Further, read selection signal RCSL is set to “H” level, selected read selection gate RCSG is turned on, and bit line RBL and data line DIO are electrically coupled. Along with this, a current path is formed from the data read circuit RDC to the selected memory cell MC. That is, as described above, the current (I0 or I1) corresponding to the resistance value (RH or RL) of the tunnel magnetoresistive element of the selected memory cell flows through the bit line RBL and the data line DIO.

  Then, control signals EN1 and EN2 are set to “H” level, respectively. Since the operation of current generator 191 is the same as described above, detailed description thereof will not be repeated.

  Then, in synchronization with the fall of the next clock signal CLK, a predetermined write operation is executed at time T11. Specifically, a predetermined data write current for writing “0” data is applied to digit line DL and bit line WBL. At that time, the word line WL is activated and data reading is still executed. Therefore, data writing is executed in parallel while data reading is being executed. That is, control signal RE is set to “H” level and control signal WE is also set to “H” level. Therefore, transistor 85 is turned on in response to control signal WE (“H” level), and a data write current flows through selected digit line DL.

  Further, as described above, the determination operation is also performed in parallel with this. When read data RDT is determined to determine that current inversion is necessary, that is, when read data RDT is “1” data in the initial data read, the inverted data write current is applied to bit line WBL. To be supplied. At the same time, the read data RDT is determined and output.

  The lower part is a diagram for explaining the operation of the block BK2. In this example, a data read operation similar to that of the block BK1 described above is performed from time T13. The details are the same as block BK1, and will not be repeated.

  In the configuration according to the second embodiment of the present invention, the determination operation is also performed earlier than the configuration according to the first embodiment, and the write back is also performed in parallel with the determination of the read data. Therefore, data reading can be performed at a higher speed than the configuration according to the first embodiment. In addition, the data read operation can be completed from time T10 to time T12, that is, during one clock cycle period, and the number of cycles is higher than that of the data read method according to the first embodiment. Can be executed.

(Embodiment 3)
In the third embodiment of the present invention, a data read operation using a so-called toggle cell will be described.

  FIG. 21 is a schematic block diagram of a memory array and its peripheral circuits according to the third embodiment of the present invention.

  Referring to FIG. 21, as compared with the configuration described with reference to FIG. 8, the write drivers WDVa and WDVb provided corresponding to the points where memory region 10a is replaced with memory region 10 # and the memory cell columns are written. The difference is that the drivers WDVa # and WDVb # are replaced. Since the other points are the same as the configuration described in FIG. 8, detailed description thereof will not be repeated.

  The memory area 10 # is different from the memory area 10a in that the memory cells MC integrated and arranged in a matrix are replaced with the memory cells MC #. Memory cell MC # is provided as a so-called toggle cell.

  The write driver WDVa # is different from the write driver WDVa in that the transistor Tr2 is deleted. The write driver WDVb # is different from the write driver WDVb in that the transistor Tr3 is deleted. Specifically, write driver WDVa # and write driver WDVb # operate in response to write control signal WDTa, and current Iw flows only in the direction from one end to the other end of bit line WBL.

  Here, the toggle cell MC # will be described.

  FIG. 22 is a diagram schematically illustrating toggle cell MC # according to the third embodiment of the present invention.

  Referring to FIG. 22, toggle cell MC # has thin film magnetic body 100 sandwiched between bit line 220 and digit line 230. Bit line 220 and digit line 230 include a conductive material capable of conducting current. In this figure, the bit line 220 is positioned above the thin film magnetic body 100, and the digit line 230 is positioned below the thin film magnetic body 100. The digit line 230 is oriented at an angle of 90 ° with respect to the bit line 220.

  The thin film magnetic body 100 includes a first magnetic part 115, a tunnel barrier 116, and a second magnetic part 17. The tunnel barrier 116 is sandwiched between the first magnetic region 115 and the second magnetic region 117.

  In the present example, the first magnetic part 115 has a three-layer structure, and is composed of two ferromagnetic layers 145 and 155 and an antiferromagnetic material sandwiched between the two ferromagnetic layers 145 and 155. A bonding spacer layer 165. Further, the second magnetic part 117 is formed of a three-layer structure, and is formed of two ferromagnetic layers 146 and 156 and an antiferromagnetic coupling spacer layer sandwiched between the two ferromagnetic layers 146 and 156. 166.

  Generally, antiferromagnetically coupled spacer layers 165 and 166 include at least one of the elements Ru, Os, Re, Cr, Rh, Cu, or combinations thereof. Further, the ferromagnetic layers 145, 155, 146 and 156 include at least one of the elements Ni, Fe, Mn, Co, or combinations thereof. Also, the first magnetic portions 115 and 117 may include a synthetic antiferromagnetic layer material structure other than a three-layer structure, for example, one such synthetic antiferromagnetic layer material structure may include a ferromagnetic layer / It is also possible to have a laminated structure of five layers formed of an antiferromagnetic coupling spacer layer / ferromagnetic layer / antiferromagnetic coupling spacer layer / ferromagnetic layer structure.

  The ferromagnetic layers 145 and 155 have magnetic moment vectors 157 and 153, respectively, that are normally kept antiparallel due to the coupling of the antiferromagnetic coupling spacer layer 165, respectively. The first magnetic unit 115 has a resultant magnetic moment vector 140, and the second magnetic unit 117 has a resultant magnetic moment vector 150.

  It is assumed that resultant magnetic moment vectors 140 and 150 are oriented at a predetermined angle between the bit line 220 and the digit line 230 along the easy magnetization axis. It is preferably oriented in the directions of 45 °, 135 °, 225 °, and 315 °. This is different from the memory cell MC described above. In memory cell MC, the easy magnetization axis is arranged so as to be in the bit line direction. However, for toggle cell MC #, the easy magnetization axis is located at a position shifted by a predetermined angle from both the bit line and the digit line. It is because it is arranged in.

  Further, the first magnetic unit 115 is a free ferromagnetic material region, that is, a free magnetic layer, that is, the resultant magnetic moment vector 140 freely rotates in the presence of an applied magnetic field. The second magnetic unit 117 is a ferromagnetic region having a fixed constant magnetization direction, that is, a fixed magnetization layer. That is, the resultant magnetic moment vector 150 is freely rotated in the presence of a moderately applied magnetic field. Rather, it is used as a reference layer.

  Although the antiferromagnetic coupling layer 165 is shown between the two ferromagnetic layers 145, 155 of the first magnetic portion 118, the ferromagnetic layer can be passed through other means such as a static magnetic field or other feature. And can be antiferromagnetically coupled.

  Note that a magnetic field is provided to set a preferred easy axis of magnetization (inductive anisotropy) at least in the formation of the ferromagnetic layers 145 and 155. The provided magnetic field creates an anisotropic axis that is favorable for magnetic moment vectors 153 and 157. A preferable axis is set so as to form an angle of 45 ° between the bit line 220 and the digit line 230 as an example.

  FIG. 23 is a diagram illustrating the magnetization direction of the toggle cell according to the third embodiment of the present invention.

  Referring to FIG. 23, thin film magnetic body 100 of toggle cell MC # is provided at a portion where bit line 220 and digit line 230 intersect each other at an angle of 90 °. For the sake of simplicity, reference will be made to an xy coordinate system 100 as shown, and a clockwise rotation direction 94 and a counterclockwise rotation direction 96.

  The preferred anisotropic axes for the magnetic moment vectors 153 and 157 are oriented at an angle of 45 ° with respect to the −x and −y directions and at an angle of 45 ° with respect to the + x and + y directions. As an example, FIG. 23 shows that the magnetic moment vector 153 is oriented at an angle of 45 ° with respect to the −x and −y directions. Since the magnetic moment vector 157 is generally oriented antiparallel to the magnetic moment vector 153, it is oriented at an angle of 45 ° with respect to the + x and + y directions.

The bit line current I _W induces a circumferential magnetic field H _W , and the digit line current I _p induces a circumferential digit magnetic field H _D.

Since the bit line 220 is above the thin film magnetic body 100, H _W is applied in the + y direction with respect to the bit line current I _W in the plane of the element. Similarly, digit line 230, since the bottom of the thin film magnetic elements 100, in the plane of the element, H _D is applied in the + x direction with respect to the digit line current I _p.

  Next, a toggle cell writing method according to the third embodiment of the present invention will be described.

  When using the toggle write method, as long as the same polarity current pulse is selected for both the bit line 220 and the digit line 230, regardless of the direction of the current, the state will change each time the MRAM device is written. Switched. For example, if “1” is initially stored, one current pulse sequence is switched to “0” after flowing through the bit and digit lines. Then, if “0” is stored, repeating the current pulse sequence returns it to “1”.

  Therefore, the data level always changes from the stored data level to the inverted data level by one writing sequence.

  FIG. 24 shows a current pulse sequence at the time of writing in the toggle cell according to the third embodiment of the present invention.

Here, the bit line current I _W and the digit line current I _p are shown, and the phases thereof are shown as waveforms in which the digit line current I _p is delayed by 90 °.

  The toggle cell data writing will be described with reference to FIG. 25 using the pulse sequence shown in FIG.

  Referring to FIG. 25, in this example, a toggle write mode for writing “1” to “0” using the pulse sequence 100 is shown.

In this figure, at time t ₀ , the magnetic moment vectors 153 and 157 are oriented in a preferred direction as shown in FIG. This orientation is defined as “1”.

At time t ₁ , the bit line current I _W is turned on, which induces the magnetic field H _W to be directed in the + y direction. The effect of the magnetic field H _W is such that the nearly balanced, anti-aligned three-layer structure of the first magnetic part 115 is “flopped” and directed to about 90 ° with respect to the direction of the applied magnetic field. Is to do. Due to the finite antiferromagnetic exchange interaction between the ferromagnetic layers 145 and 155, the magnetic moment vectors 153 and 157 now deviate by a small angle toward the direction of the magnetic field and the resultant magnetic moment vector 140. Delimits the angle between magnetic moment vectors 153 and 157 and aligns with magnetic field H _W. For this reason, the magnetic moment vector 153 rotates in the clockwise direction 94. Since the resultant magnetic moment vector 140 is a vector addition of the magnetic moment vectors 153 and 157, the magnetic moment vector 157 also rotates in the clockwise direction 94.

In time t _2, the digit current I _p turns on, it induces a magnetic field H _D. Thus, the resultant magnetic moment vector 140 is simultaneously directed in the + y direction by the magnetic field H _W and in the + x direction by the magnetic field H _{D, which} causes the resultant magnetic moment vector 140 to be generally between the + x and + y directions. It has the effect of further rotating clockwise 94 until it is oriented at an angle of 45 °. Therefore, the magnetic moment vectors 153 and 157 are further rotated in the clockwise direction 94.

At time t _3, the bit line current I _W is turned off, therefore direct the magnetic field H _D only force magnetic moment vector 140 where it is here directed in the + x direction. Both magnetic moment vectors 153 and 157 are here generally oriented at an angle through their hard axis instability points.

At time t ₄ , the digit current I _p is turned off, so that no magnetic force is acting on the resultant magnetic moment vector 140. Thus, magnetic moment vectors 153 and 157 are directed in their closest preferred direction to minimize anisotropic energy. In this case, a preferable direction for the magnetic moment vector 153 is an angle of 45 ° with respect to the + y direction and the + x direction. This preferred direction is also 180 ° from the initial direction of the magnetic moment vector 153 at time t ₀ and is defined as “0”. For this reason, the thin film magnetic body 100 has already been switched to “0”.

  26, another data writing of the toggle cell will be described using the pulse sequence shown in FIG.

  Referring now to FIG. 26, this example shows a toggle write mode for writing “0” to “1” using the pulse sequence 100.

Shown are magnetic moment vectors 153 and 157 and resultant magnetic moment vector 140 at times t ₀ , t ₁ , t ₂ , t ₃ and t ₄ as described above, and the state of the memory cell is shown as follows. It shows that switching can be performed from “0” to “1” with the same current and magnetic field direction.

  As a data reading method according to the third embodiment of the present invention, a method of executing self-reference using the above-described toggle cell will be described.

  FIG. 27 is a flowchart illustrating a data read operation according to the third embodiment of the present invention. Since specific operations other than the data write operation are substantially the same as those described in the flowchart of FIG. 12, detailed description thereof will not be repeated.

  Referring to FIG. 27, in the configuration according to the third embodiment of the present invention, first, when the data read operation is started (step S11), the magnetization direction of the selected memory cell is set as the initial data read operation before the data read operation. The data reading is executed in the same state as that in FIG. 1, that is, in the state where the selected memory cell holds the storage data to be originally read (step S12).

  Next, current generation unit 191 detects a current flowing through data line DIO during the initial data read operation, and generates a current that is 10% smaller than the detected current (step S12 #). Specifically, the current 0.9I0 or 0.9I1 is generated as described in FIGS.

  Next, data is written to the selected memory cell as a write operation (step S13). Specifically, the inverted data of the first stored data is written using the pulse sequence described in FIG.

  Then, as a data read operation, data read for the selected memory cell is executed while writing inverted data to the selected memory cell (step S14). In data reading according to the third embodiment of the present invention, since data writing and data reading are executed in parallel in this case, high-speed data reading can be executed.

  Next, as a read confirmation operation, a current that is 10% smaller generated by reading stored data from the selected memory cell in the initial data read operation, and a current that has been read this time with inverted data written by the write operation, Based on the comparison, the read data RDT is determined (step S15).

  Next, as a write operation, data is written to the selected memory cell (step S16). In the data read operation of the first and second embodiments, the case where rewriting is executed based on the comparison between read data RDT and initial data has been described. However, in the case of a toggle cell, one write operation is performed. This is because the inverted data is always rewritten, so that the write operation is required twice to restore the initial data.

  As a result, for the selected memory cell that has received the predetermined data write in the read operation sequence, the stored data can be reproduced and restored to the state before the data read.

  Then, the data reading operation is finished (step S17).

  FIG. 28 is a diagram for explaining the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “1” data. When “1” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RL.

  Referring to FIG. 28B, first, in the data read operation, current I1 flows through data line DIO based on resistance value RL as described in step S2. In this case, current generation unit 191 performs step S12. As described in #, a reference current of −10% is generated. Next, when the inverted data is written by the write operation as described in step S13, the resistance value of the tunnel magnetoresistive element changes from RL to RH as shown in FIG. On the other hand, in the data read operation described in step S14, as shown in FIG. 28B, the current value decreases from the current I1 to the current I0 as described above.

  Therefore, when the tunnel magnetoresistive element stores “1” data, the current value is set to a current I0 smaller than the reference current of −10%.

  FIG. 29 is a diagram illustrating the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. When “0” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RH.

  Referring to FIG. 29B, first, in the data read operation, current I0 flows through data line DIO based on resistance value RH as described in step S12. In this case, current generation unit 191 performs step S2 As described in #, a reference current of −10% is generated. Next, when the inverted data is written by the write operation as described in step S13, the resistance value of the tunnel magnetoresistive element changes from RH to RL as shown in FIG. On the other hand, in the data read operation described in step S14, the current value increases from the current I0 to the current I1 as shown in FIG.

  Therefore, when the tunnel magnetoresistive element stores “0” data, the current value becomes larger than the reference current of −10%. On the other hand, when the tunnel magnetoresistive element stores “1” data, the current ground is smaller than the reference current of −10% current.

  Therefore, by using this characteristic, read data can be determined using a reference current of -10% current. That is, as described in step S15, a current value that is −10% smaller generated by the initial initial data read operation is compared with the current from which “0” data is read. As a result, if the current for reading “0” data is smaller than the current value generated by the initial initial data read operation by −10%, the resistance value during the initial initial data read operation is RL, that is, the tunnel. That is, “1” data is stored in the magnetoresistive element. That is, the read data RDT is “1” data. On the other hand, if the current from which “0” data is read is larger than the current value that is −10% smaller generated by the initial initial data read operation, the resistance value at the initial initial data read operation is RH, that is, tunneling magnetism. That is, “0” data is stored in the resistance element. That is, the read data RDT is “0” data.

  FIG. 28 and FIG. 29 also show the change when the write operation (write back) is executed.

  Therefore, by performing the data read operation according to the third embodiment of the present invention described with reference to FIG. 27, it is possible to execute self-reference with high speed and high read margin even in the toggle cell.

(Modification of Embodiment 3)
FIG. 30 is a schematic block diagram of a memory array and its peripheral circuits according to a modification of the third embodiment of the present invention.

  Referring to FIG. 30, it differs from the configuration described in FIG. 21 in that data read circuit RDC is replaced with data read circuit RDC #.

  In the modification according to the third embodiment of the present invention, a method of executing data reading at a higher speed than the data reading according to the third embodiment will be described.

  Data read circuit RDC # is different in that a current generation unit 191a, a comparison unit 192a, and an amplifier 190a are further provided. The output signal of the amplifier 190a is input to the write driver control circuit 180 # a.

  FIG. 31 is a circuit configuration diagram of current generation units 191 and 191a and comparison units 192 and 192a according to the third embodiment of the present invention. Since current generation unit 191 and comparison unit 192 are the same as those described with reference to FIG. 9, detailed description thereof will not be repeated.

  The current generator 191a generates a current that is approximately 10% larger than the passing current flowing through the data line DIO.

  Referring to FIG. 31, current generation unit 191a according to the third embodiment of the present invention includes transistors 122a to 125a and switches 131a and 132a.

  Transistor 122a is connected between node N0 and power supply voltage Vcc, and has its gate receiving control signal / PC. Transistor 123a is connected between power supply voltage Vcc and node N5, and has its gate connected to node N0. Transistor 125a is connected between node N5 and fixed voltage Vss, and has its gate connected to node N7. Nodes N5 and N7 are connected via a switch 132a. The switch 131a is disposed between the node N0 and the node N6.

  Here, the transistors 121 and 123a form a current mirror circuit. The size of the transistor 125a is set to 8W. Strictly speaking, since the transistor size ratio of the transistor 125a and the transistor 127a is 8: 9, the current passing through the transistor 127a is not set to + 10% by the current mirror circuit. Therefore, for the sake of simplification of explanation, it will be treated in the following as almost the same thing.

  Comparison unit 192a includes transistors 127a to 129a and capacitors 126a and 130a. The capacitor 130a is connected between the node N6 and the fixed voltage Vss. Transistor 129a is connected between node N6 and power supply voltage Vcc, and its gate receives control signal / PC. Transistor 128a is connected between power supply voltage Vcc and node N8, and has its gate connected to node N6. Transistor 127a is connected between node N8 and fixed voltage Vss, and its gate is connected to node N7. The capacitor 126a is connected between the node N7 and the fixed voltage Vss. The signal transmitted to node N8 is amplified by amplifier 190a and transmitted to write driver control circuit 180 # a.

  Since operations of current generation unit 191 and comparison unit 192 are the same as those described in FIGS. 10 and 11, detailed description thereof will not be repeated. The same applies to the current generation unit 191a and the comparison unit 192a. In other words, current generator 191a passes a current that is approximately 10% larger than the passing current by adjusting the transistor size ratio in response to the input of control signal EN1 ("H" level). Then, a charge corresponding to the 10% larger passing current is accumulated in the capacitor 126a. Similarly, a charge corresponding to the passing current flowing through the data line DIO is stored in the capacitor 130a in response to the control signal EN2 (“H” level). Comparing portion 192a sets the potential level of node N8 by an amplifying action based on the charges accumulated in capacitors 126a and 130a. That is, a signal based on a reference current that is + 10% larger is output from the node N8. Then, it is further amplified by the amplifier 190a and output to the write driver control circuit 180 # a.

  FIG. 32 is a flowchart illustrating a data read method according to the modification of the third embodiment of the present invention.

  Referring to FIG. 32, the difference from the flowchart of FIG. 27 is that step S12 # is changed to step S12 # a and step S15 is changed to step S15a. Other points are the same as those described in the flowchart of FIG.

  Specifically, in step S12 # a, a current that is 10% smaller and 10% larger than the current read in current generators 191 and 191a described above are generated.

  Then, in the read data determination operation in step S15, the read data RDT is determined based on a comparison between each of the 10% smaller current and the 10% larger current and the current read data.

  Then, step S16 and step S17 are executed, and the data reading operation is terminated.

  FIG. 33 is a diagram for explaining the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “1” data. When “1” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RL.

  Referring to FIG. 33B, first, in the data read operation, current I1 flows through data line DIO based on resistance value RL as described in step S2. In this case, current generation unit 191 performs step S12. As described in #a, −10% and + 10% reference currents are generated. Next, when the inverted data is written by the write operation as described in step S13, the resistance value of the tunnel magnetoresistive element changes from RL to RH as shown in FIG. On the other hand, in the data read operation described in step S14, as shown in FIG. 33B, the current value decreases from the current I1 to the current I0 as described above.

  Therefore, when the tunnel magnetoresistive element stores “1” data, the current value is set to a current I0 smaller than the reference current of −10%.

  FIG. 34 is a diagram illustrating the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. When “0” data is stored in the tunnel magnetoresistive element, the resistance value of the tunnel magnetoresistive element is RH.

  Referring to FIG. 34B, first, in the data read operation, current I0 flows through data line DIO based on resistance value RH as described in step S12. In this case, current generation unit 191 performs step S2 As described in #a, −10% and + 10% reference currents are generated. Next, when the inverted data is written by the write operation as described in step S13, the resistance value of the tunnel magnetoresistive element changes from RH to RL as shown in FIG. On the other hand, in the data read operation described in step S14, the current value increases from the current I0 to the current I1, as shown in FIG.

  Therefore, when the tunnel magnetoresistive element stores “0” data, the current value becomes larger than the reference current of −10%. On the other hand, when the tunnel magnetoresistive element stores “1” data, the current ground is smaller than the reference current of −10% current.

  Therefore, by using this characteristic, read data can be determined using a reference current of -10% current. That is, as described in step S15, a current value that is −10% smaller generated by the initial initial data read operation is compared with the current from which “0” data is read. As a result, if the current for reading “0” data is smaller than the current value generated by the initial initial data read operation by −10%, the resistance value during the initial initial data read operation is RL, that is, the tunnel. That is, “1” data is stored in the magnetoresistive element. That is, the read data RDT is “1” data. On the other hand, if the current from which “0” data is read is larger than the current value that is −10% smaller generated by the initial initial data read operation, the resistance value at the initial initial data read operation is RH, that is, tunneling magnetism. That is, “0” data is stored in the resistance element. That is, the read data RDT is “0” data.

  In this regard, in the data read operation according to the modification of the third embodiment of the present application, read data is determined using a reference current of −10% current and + 10% current. Specifically, the reference current of −10% and + 10% and the current from which data is read are monitored. As a result, the boundary between the -10% smaller current and the + 10% larger current generated by the initial initial data read operation is surely exceeded. Therefore, the read data RDT can be determined by monitoring this boundary point. Specifically, write driver control circuit 180 # a determines the read data RDT by monitoring the boundary points from the output results of amplifiers 190 and 190a.

  In this regard, in the data read operation according to the third embodiment, after the write operation is completely completed, the read data determination operation, that is, the comparison operation between the current that is 10% smaller and the current that reads the “0” data, that is, read data RDT The judgment was executed.

  In the modification of Embodiment 3 of the present application, this determination is performed while the write operation is being performed. Therefore, as compared with the third embodiment, the period for determining data read RDT can be shortened, and higher-speed data read can be executed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device shown as a representative example of a nonvolatile memory device according to a first embodiment of the present invention. It is the schematic which shows the structure of the memory cell which has a tunnel junction part. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram which shows the relationship between the data write current in data writing, and the magnetization direction of a tunnel magnetoresistive element. It is a conceptual diagram explaining the data reading from an MTJ memory cell. It is a figure which shows the relationship (hysteresis characteristic) of the electric current for applying a magnetic field with respect to an MTJ memory cell, and the electrical resistance of an MTJ memory cell. It is a conceptual diagram explaining the magnetization direction of the tunnel magnetoresistive element in each state shown in FIG. 1 is a schematic configuration diagram of a memory array and its peripheral circuits according to a first embodiment of the present invention. It is a circuit block diagram of the electric current generation part 191 and the comparison part 192 according to Embodiment 1 of this invention. FIG. 10 is a diagram for explaining a case where a current that is 10% smaller is generated when the tunnel magnetoresistive element TMR has a high resistance in data reading of a memory cell. FIG. 10 is a diagram for explaining a case where a current that is 10% smaller is generated when the tunnel magnetoresistive element TMR has a low resistance in reading data from a memory cell. FIG. 7 is a flowchart illustrating a data read operation according to the first embodiment of the present invention. It is a figure explaining the relationship between resistance value and current value when a tunnel magnetoresistive element has memorized “1” data. It is a figure explaining the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. FIG. 7 is a timing chart diagram of a data read operation according to the first embodiment of the present invention. FIG. 7 is a schematic block diagram of a memory array and its peripheral circuits according to a second embodiment of the present invention. It is a flowchart figure explaining the data read-out operation according to Embodiment 2 of this invention. It is a figure explaining the relationship between resistance value and current value when a tunnel magnetoresistive element has memorized “1” data. It is a figure explaining the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. FIG. 11 is a timing chart diagram of a data read operation according to the second embodiment of the present invention. FIG. 10 is a schematic block diagram of a memory array and its peripheral circuits according to a third embodiment of the present invention. It is a figure which illustrates typically toggle cell MC # according to Embodiment 3 of this invention. It is a figure explaining the magnetization direction of the toggle cell according to Embodiment 3 of the present invention. It is a current pulse sequence at the time of writing of the toggle cell according to the third embodiment of the present invention. It is a figure explaining the data writing of a toggle cell using the pulse sequence shown by FIG. FIG. 25 is a diagram illustrating another data writing of the toggle cell using the pulse sequence shown in FIG. 24. It is a flowchart figure explaining the data read-out operation according to Embodiment 3 of this invention. It is a figure explaining the relationship between resistance value and current value when a tunnel magnetoresistive element has memorized “1” data. It is a figure explaining the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data. FIG. 16 is a schematic block diagram of a memory array and its peripheral circuits according to a modification of the third embodiment of the present invention. It is a circuit block diagram of the electric current generation parts 191 and 191a and the comparison parts 192 and 192a according to Embodiment 3 of the present invention. It is a flowchart figure explaining the data reading system according to the modification of Embodiment 3 of this invention. It is a figure explaining the relationship between resistance value and current value when a tunnel magnetoresistive element has memorized “1” data. It is a figure explaining the relationship between the resistance value and the current value when the tunnel magnetoresistive element stores “0” data.

Explanation of symbols

  1 MRAM device, 5 control circuit, 10 memory array, 10a, 10 # memory area, 20 row selection circuit, 25 column decoder, 30, 35 read / write control circuit, 180, 180 #, 180 # a write driver control circuit , 191, 191 a Current generation unit, 192, 192 a comparison unit, 190, 190 a amplification unit, RDC, RDC # data readout circuit.

Claims (9)

In each of the above, a plurality of memory cells through which a passing current corresponding to stored data flows during data reading;
A reference in which a ratio of the passing current is changed by detecting a passing current flowing according to the stored data through a selected memory cell selected as a data reading target among the plurality of memory cells during the data reading. A current generation circuit for generating a current;
A data read circuit for generating read data of the selected memory cell based on a comparison between the reference current generated by the current generation circuit and a passing current that changes in the selected memory cell according to the stored data at the time of data reading A nonvolatile storage device. The current generation circuit includes a first current path through which the passing current flows, and a second current path that is provided corresponding to the first current path and flows a current mirror current of the passing current. Configure the current mirror circuit,
The second current path includes first and second transistors provided in parallel with each other for adjusting a current amount of the passing current,
The nonvolatile memory device according to claim 1, wherein channel widths of the first and second transistors are different from each other. A data write circuit for applying a data write magnetic field to a selected memory cell selected as a data read target of the plurality of memory cells;
The data read circuit includes the passing current flowing through the selected memory cell, which changes respectively before and after application based on the application of the data write magnetic field executed once in one data read operation, and the reference current The non-volatile memory device according to claim 1, wherein read data is generated based on a comparison with.   The data read circuit performs the determination of the read data based on whether or not the passing current flowing through the selected memory cell that changes based on application of the data write magnetic field exceeds a predetermined reference value. 3. The nonvolatile memory device according to 3. The data writing circuit includes:
Data is applied to the selected memory cell in one of a first direction and a second direction opposite to the first direction to apply the data write magnetic field in response to an instruction. A current supply for supplying a write current;
In the data read operation, the data write current is supplied from the current supply unit to the other one of the first and second directions based on a determination result of the read data from the data read circuit. The nonvolatile memory device according to claim 4, further comprising a control unit that instructs the current supply unit to supply the current. The nonvolatile memory device operates in synchronization with a clock signal,
In the one data read operation, data reading for detecting the passing current before application of the data writing magnetic field, application of the data writing magnetic field and detection of the passing current after application of the data writing magnetic field are performed. 4. The nonvolatile memory device according to claim 3, wherein the data reading to be performed is continuously executed during one clock cycle. Each of a plurality of memory cells through which a passing current corresponding to stored data flows during data reading,
A data line electrically coupled to a fixed voltage via a selected memory cell selected as a data read target of the plurality of memory cells during data reading;
A current supply circuit for coupling the data line to a predetermined voltage and supplying the passing current to a selected memory cell during the data reading;
A data write circuit for applying a data write magnetic field to the selected memory cell;
A data read circuit for generating read data based on data stored in the selected memory cell before and after application of the data write magnetic field executed once in one data read operation,
The data read circuit includes:
A reference current generation unit that generates a reference current by changing a predetermined ratio of a passing current flowing by data reading of the selected memory cell before application of the data write magnetic field;
A non-volatile memory device comprising: a passing current that flows due to data reading of the selected memory cell after application of a predetermined data write magnetic field; and a comparator that generates the read data based on a comparison with the reference current. The plurality of memory cells are integrated and arranged in a matrix,
A plurality of first write current lines provided respectively corresponding to the memory cell rows;
A plurality of second write current lines provided corresponding to the memory cell columns,
The data write circuit applies a predetermined data write magnetic field according to a predetermined pulse sequence to the first and second write current lines corresponding to the selected memory cell during the data write,
Each of the memory cells
A pinned magnetic layer disposed along an easy axis of magnetization between the corresponding first and second write current lines;
The nonvolatile memory device according to claim 7, further comprising: a free magnetic layer whose magnetization direction is reversed by applying the predetermined data write magnetic field during the data write.   9. The non-volatile memory according to claim 8, wherein the predetermined pulse sequence is set such that a data write current that is 90 degrees out of phase with respect to the corresponding first and second write current lines flows. apparatus.

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