JP2003109375A - Read-out circuit for magnetic memory device - Google Patents
Read-out circuit for magnetic memory deviceInfo
- Publication number
- JP2003109375A JP2003109375A JP2001301551A JP2001301551A JP2003109375A JP 2003109375 A JP2003109375 A JP 2003109375A JP 2001301551 A JP2001301551 A JP 2001301551A JP 2001301551 A JP2001301551 A JP 2001301551A JP 2003109375 A JP2003109375 A JP 2003109375A
- Authority
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- Japan
- Prior art keywords
- potential
- magnetoresistive element
- memory device
- read circuit
- magnetic memory
- Prior art date
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Abstract
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【発明の属する技術分野】本発明は、不揮発性メモリ装
置の読み出し回路に関し、特に、磁気抵抗素子を用いた
メモリセルを有する磁気メモリ装置に適した読み出し回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit of a nonvolatile memory device, and more particularly to a read circuit suitable for a magnetic memory device having a memory cell using a magnetoresistive element.
【０００２】[0002]
【従来の技術】強磁性体などの磁性体において、その磁
化の方向や磁化の有無などによってその電気抵抗が変化
する磁気抵抗効果が知られており、そのときの電気抵抗
値の変化率を磁気抵抗比（ＭＲ比；Magneto-Resistance
Ratio）という。磁気抵抗比が大きい材料としては、巨
大磁気抵抗（ＧＭＲ；Giant Magneto-Resistance）材料
や超巨大磁気抵抗（ＣＭＲ；Colossal Magneto-Resista
nce）材料があり、これらは一般に、金属、合金、複合
酸化物などである。例えば、Ｆｅ，Ｎｉ，Ｃｏ，Ｇｄ，
Ｔｂおよびこれらの合金や、ＬａXＳｒ1-XＭｎＯ9，Ｌ
ａXＣａ1-XＭｎＯ9などの複合酸化物などの材料があ
る。また一般に、強磁性体は、外部から印加された磁場
によってその強磁性体内に発生した磁化が外部磁場を取
り除いた後にも残留する（これを残留磁化という）、と
いう特性を有している。2. Description of the Related Art In a magnetic material such as a ferromagnetic material, a magnetoresistive effect is known in which the electric resistance changes depending on the direction of magnetization and the presence or absence of magnetization. Resistance ratio (MR ratio; Magneto-Resistance)
Ratio). Giant Magneto-Resistance (GMR) materials and Colossal Magneto-Resista (CMR) materials are used as materials having a large magnetic resistance ratio.
nce) materials, which are generally metals, alloys, complex oxides, and the like. For example, Fe, Ni, Co, Gd,
Tb and their alloys, La X Sr 1-X MnO 9 , L
There are materials such as composite oxide such as a X Ca 1-X MnO 9 . In general, a ferromagnetic substance has a characteristic that the magnetization generated in the ferromagnetic substance by an externally applied magnetic field remains even after the external magnetic field is removed (this is called remanent magnetization).
【０００３】そこで、磁気抵抗材料として強磁性体を用
いてその強磁性体の残留磁化を利用すれば、磁化方向や
磁化の有無により電気抵抗値を選択して情報を記憶する
不揮発性メモリを構成することができる。このような不
揮発性メモリは、磁気メモリ（ＭＲＡＭ（磁気ランダム
アクセスメモリ）；Magnetic Random Access Memory）
と呼ばれている。Therefore, if a ferromagnetic material is used as the magnetoresistive material and the residual magnetization of the ferromagnetic material is utilized, a non-volatile memory for storing information by selecting an electric resistance value depending on the magnetization direction and the presence / absence of magnetization is constructed. can do. Such a nonvolatile memory is a magnetic memory (MRAM: Magnetic Random Access Memory).
is called.
【０００４】近年、開発が進められているＭＲＡＭの多
くは、巨大磁気抵抗材料の強磁性体の残留磁化で情報を
記憶しており、磁化方向の違いによって生じる電気抵抗
値の変化を検出することにより、記憶した情報を読み出
す方式を採用している。また、書込み用配線に電流を流
して誘起される磁場により強磁性体メモリセルの磁化方
向を変化させることで、メモリセルに情報を書き込み、
また、その情報を書き換えることができる。Most of the MRAMs that have been developed in recent years store information by the residual magnetization of a ferromagnetic material of a giant magnetoresistive material, and can detect a change in electric resistance value caused by a difference in magnetization direction. Therefore, a method of reading the stored information is adopted. In addition, by writing a current in the memory cell by changing the magnetization direction of the ferromagnetic memory cell by a magnetic field induced by applying a current to the write wiring,
Also, the information can be rewritten.
【０００５】ＭＲＡＭのメモリセルとしては、トンネル
絶縁膜（トンネル電流が流れる程度の厚さの電気絶縁
膜）を２つの強磁性体層で挟んだ構造をもつトンネル磁
気抵抗素子（ＴＭＲ；Tunnel Magneto-Resistance、あ
るいはＭＴＪ；Magnetic TunnelJunction）が、高い磁
気抵抗変化率（ＭＲ比）を備えており、もっとも実用化
に近いデバイスとして期待されている。このようなメモ
リセルとして、従来、２つの面内磁化膜の間にトンネル
絶縁膜を挟み込んだ構成のものが検討されていた。しか
しながら、面内磁化膜を使用したメモリセルの場合、メ
モリセルの微小化に伴って、ＭＲ比が低下し、必要な書
き込み電流が増加し、また、動作点（メモリセルの磁気
特性を示すヒステリシスループ）の移動が起こるなど
の、解決すべき課題があることが分かっている。これに
対し、本願出願人は、特開平１１−２１３６５０号公報
において、２枚の垂直磁化膜の間にトンネル絶縁膜であ
る非磁性層を挟み込んだ構成のものを提案した。垂直磁
化膜を使用することにより、メモリセルを微小化した場
合であっても、ＭＲ比の低下や書き込み電流の増加が抑
えられ、また、ヒステリシスループにおけるシフトも抑
えられ、優れた特性を有するメモリセルが得られるよう
になる。As a memory cell of an MRAM, a tunnel magnetoresistive element (TMR; Tunnel Magneto-) having a structure in which a tunnel insulating film (an electric insulating film having a thickness such that a tunnel current flows) is sandwiched between two ferromagnetic layers. Resistance, or MTJ (Magnetic Tunnel Junction), has a high rate of change in magnetoresistance (MR ratio), and is expected as a device that is most practical. As such a memory cell, one having a structure in which a tunnel insulating film is sandwiched between two in-plane magnetized films has been conventionally studied. However, in the case of a memory cell using an in-plane magnetized film, the MR ratio is reduced and the required write current is increased with the miniaturization of the memory cell, and the operating point (hysteresis indicating the magnetic characteristics of the memory cell is It is known that there are issues that need to be solved, such as movement of loops). On the other hand, the applicant of the present application has proposed a structure in which a nonmagnetic layer, which is a tunnel insulating film, is sandwiched between two perpendicularly magnetized films in Japanese Patent Laid-Open No. 11-213650. By using the perpendicular magnetization film, even if the memory cell is miniaturized, a decrease in MR ratio and an increase in write current can be suppressed, and a shift in a hysteresis loop can also be suppressed. You can get cells.
【０００６】図２は、ＭＲＡＭのメモリセルアレイの構
成の一例を示す回路図である。FIG. 2 is a circuit diagram showing an example of the configuration of the memory cell array of the MRAM.
【０００７】１個のメモリセルは、可変抵抗として表現
された磁気抵抗素子（メモリ素子）１１と、磁気抵抗素
子１１に一端が接続するスイッチ素子１２とを備えてい
る。スイッチ素子１２は、典型的にはＭＯＳ(Metal-Oxi
de-Semiconductor)電界効果トランジスタによって構成
されており、その他端は接地されている。このようなメ
モリセルが複数個、２次元にマトリクス状に配置するこ
とにより、メモリセルアレイを構成している。ここで図
示横方向の並びを行、縦方向の並びを列と呼ぶことにす
ると、図示したものでは、メモリセルアレイにおける３
行×３列分の領域が示されている。各行ごとに行方向に
延びるビット線ＢＬ１〜ＢＬ３が設けられ、各列ごとに
列方向に延びるワード線ＷＬ１〜ＷＬ３が設けられてい
る。各メモリセルにおいて、磁気抵抗素子１１の一端は
対応する行のビット線に接続し、スイッチ素子１２のゲ
ートは対応する列のワード線に接続する。One memory cell includes a magnetoresistive element (memory element) 11 represented as a variable resistance, and a switch element 12 having one end connected to the magnetoresistive element 11. The switch element 12 is typically a MOS (Metal-Oxi).
de-Semiconductor) field effect transistor, and the other end is grounded. A plurality of such memory cells are two-dimensionally arranged in a matrix to form a memory cell array. Here, when the arrangement in the horizontal direction in the drawing is called a row and the arrangement in the vertical direction is called a column, in the illustrated arrangement, 3 in the memory cell array are used.
A region of rows × 3 columns is shown. Bit lines BL1 to BL3 extending in the row direction are provided for each row, and word lines WL1 to WL3 extending in the column direction are provided for each column. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line of the corresponding row, and the gate of the switch element 12 is connected to the word line of the corresponding column.
【０００８】図示破線で示すのは、各メモリセルへのデ
ータの書き込みを行うための書き込み線ＷＷＬ１〜ＷＷ
Ｌ３であり、この書き込み線は、列ごとに設けられてい
る。図示した例では書き込み線ＷＷＬ１〜ＷＷＬ３は列
の他端で折り返す構成となっており、列ごとに設けられ
た書き込み回路１３により、所定の書き込み電流が流さ
れるようになっている。各書き込み回路１３には、電源
回路１４から、書き込み電流を生成するための電流が供
給される。The broken lines shown in the figure indicate write lines WWL1 to WW for writing data to each memory cell.
L3, and the write line is provided for each column. In the illustrated example, the write lines WWL1 to WWL3 are folded back at the other end of the column, and a predetermined write current is supplied by the write circuit 13 provided for each column. A current for generating a write current is supplied to each write circuit 13 from the power supply circuit 14.
【０００９】図３は、メモリセルの構成の一例を示す断
面図である。図では、列方向に並ぶ２個のメモリセルが
示されている。FIG. 3 is a sectional view showing an example of the structure of a memory cell. In the figure, two memory cells arranged in the column direction are shown.
【００１０】半導体基板３０上に素子分離領域３１が形
成されるとともに、スイッチ素子１２のドレイン領域３
２及びソース領域３３が設けられ、ドレイン領域３２及
びソース領域３３に挟まれた領域において、ゲート絶縁
膜３４を介して、スイッチ素子１２のゲート電極を兼ね
るワード線３５（図２におけるワード線ＷＬ１〜ＷＬ３
に対応）が形成されている。図示した例では、２個のス
イッチ素子１２がソース領域３３を兼用する形態となっ
ており、このようなスイッチ素子１２を覆うように、層
間絶縁膜３６，３７及び３８がこの順で設けられてい
る。層間絶縁膜３８は、特に薄く形成されている。ソー
ス領域３３は、プラグ３９を介して、層間絶縁膜３６上
に形成された接地線４０に接続し、ドレイン領域３２
は、プラグ４１を介して、層間絶縁膜３８上に形成され
た磁気抵抗素子１１に下面に接続している。磁気抵抗素
子１１は、図示した例では、特開平１１−２１３６５０
号公報に記載されたような、２層の垂直磁化膜の間に非
磁性層であるトンネル絶縁膜を挟持した構成のものであ
る。また、層間絶縁膜３８の下には、層間絶縁膜３７に
彫り込まれるように、書き込み線４２（図２における書
き込み線ＷＷＬ１〜ＷＷＬ３に対応）が形成されてい
る。隣接する磁気抵抗素子１１間の領域を埋めるように
層間絶縁膜４３が形成されており、磁気抵抗素子１１の
上面は、層間絶縁膜４３上に形成されて図示左右方向に
延びるビット線４４（図２におけるビット線ＢＬ１〜Ｂ
Ｌ３に対応）に接続している。さらに、層間絶縁膜４３
やビット線４４を覆うように、保護膜を兼ねる層間絶縁
膜４５が形成されている。The element isolation region 31 is formed on the semiconductor substrate 30, and the drain region 3 of the switch element 12 is formed.
2 and the source region 33 are provided, and in the region sandwiched by the drain region 32 and the source region 33, the word line 35 (the word lines WL1 to WL1 in FIG. 2 also serving as the gate electrode of the switch element 12 is provided via the gate insulating film 34. WL3
Corresponding to) is formed. In the illustrated example, the two switch elements 12 also serve as the source region 33, and the interlayer insulating films 36, 37, and 38 are provided in this order so as to cover the switch elements 12. There is. The interlayer insulating film 38 is formed particularly thin. The source region 33 is connected to the ground line 40 formed on the interlayer insulating film 36 via the plug 39, and the drain region 32.
Is connected to the lower surface of the magnetoresistive element 11 formed on the interlayer insulating film 38 via the plug 41. In the illustrated example, the magnetoresistive element 11 is disclosed in JP-A-11-213650.
As described in Japanese Unexamined Patent Publication (Kokai), a tunnel insulating film which is a non-magnetic layer is sandwiched between two layers of perpendicularly magnetized films. A write line 42 (corresponding to the write lines WWL1 to WWL3 in FIG. 2) is formed below the interlayer insulating film 38 so as to be engraved in the interlayer insulating film 37. An interlayer insulating film 43 is formed so as to fill the region between the adjacent magnetoresistive elements 11, and the upper surface of the magnetoresistive element 11 is formed on the interlayer insulating film 43 and extends in the left-right direction in the drawing (see FIG. 2 bit lines BL1 to B
It corresponds to L3). Further, the interlayer insulating film 43
An interlayer insulating film 45 that also serves as a protective film is formed so as to cover the bit line 44 and the bit line 44.
【００１１】図２に示したメモリセルアレイにおけるメ
モリセルへのデータの書き込みは、データを書き込もう
とするメモリセル（選択されたメモリセル）が属する列
の書き込み線に、書き込み値（“０”または“１”）に
応じた極性の書き込み電流を流して書き込み磁界を発生
するとともに、そのメモリセルが属する行のビット線に
アシスト電流を流してアシスト磁界を発生させ、書き込
み磁界とアシスト磁界との和磁界によって、選択された
メモリセルのみにデータが書き込まれるようにして行わ
れる。選択された行のビット線にアシスト電流を流すた
めに、各ビット線の一端には、電源回路１４とそのビッ
ト線を接続するためのスイッチ素子１５が設けられ、他
端には、その他端でビット線を接地するためのスイッチ
素子１６が設けられている。スイッチ素子１５，１６
は、典型的には、ＭＯＳ電界効果トランジスタによって
構成される。When writing data to a memory cell in the memory cell array shown in FIG. 2, a write value ("0" or "0" is written to the write line of the column to which the memory cell (selected memory cell) to which the data is to be written belongs. 1 "), a write current having a polarity corresponding to that of 1") is applied to generate a write magnetic field, and an assist current is applied to a bit line of a row to which the memory cell belongs to generate an assist magnetic field, which is a sum magnetic field of the write magnetic field and the assist magnetic field. Thus, the data is written only in the selected memory cell. In order to pass an assist current to the bit line of the selected row, a switch element 15 for connecting the power supply circuit 14 and the bit line is provided at one end of each bit line, and the other end is provided at the other end. A switch element 16 for grounding the bit line is provided. Switch elements 15 and 16
Are typically constituted by MOS field effect transistors.
【００１２】このようなメモリセルアレイにおいて、各
ビット線ＢＬ１〜ＢＬ３の一端には、読み出し回路２０
が設けられている。読み出し回路２０は、ワード線ＷＬ
１〜ＷＬ３によって選択された列のメモリセルからその
メモリセルに書き込まれたデータを読み出すものであ
る。具体的には、スイッチ素子１５，１６の全てをオフ
状態とし、ワード線によって特定の列のスイッチ素子１
２をオン状態とし、読み出し回路２０側から対象とする
メモリセルの磁気抵抗素子１１の抵抗値を読み出し、そ
の結果に基づいて“０”及び“１”のいずれが記録され
ているかを判定する。この場合、磁気抵抗素子１１の抵
抗値の絶対値を測定するのではなく、たとえば読み出し
回路２０内に参照セルを設け、その参照セルと磁気抵抗
素子１１の抵抗との大小を比較して“０”及び“１”の
いずれであるかを判定する。参照セルには、磁気抵抗素
子１１において記録値が“０”のときの抵抗値と記録値
が“１”であるときの抵抗値との中間となる抵抗値が設
定されるようにする。そして、参照セルと磁気抵抗素子
１１の双方に所定電流を流し、そのときに参照セル及び
磁気抵抗素子１１の双方の両端の電圧を検出し、両者の
電圧を比較することによって、参照セルの抵抗値の方が
大きいか、磁気抵抗素子１１の抵抗値の方が大きいかを
判定し、磁気抵抗素子１１に記録されたデータを判別す
る。In such a memory cell array, the read circuit 20 is provided at one end of each of the bit lines BL1 to BL3.
Is provided. The read circuit 20 uses the word line WL
The data written in the memory cell of the column selected by 1 to WL3 is read out. Specifically, all the switch elements 15 and 16 are turned off, and the switch element 1 in a specific column is selected by the word line.
2 is turned on, the resistance value of the magnetoresistive element 11 of the target memory cell is read from the read circuit 20 side, and whether "0" or "1" is recorded is determined based on the result. In this case, instead of measuring the absolute value of the resistance value of the magnetoresistive element 11, for example, a reference cell is provided in the read circuit 20, and the reference cell and the resistance of the magnetoresistive element 11 are compared to determine “0”. It is determined whether it is "" or "1". In the reference cell, a resistance value that is intermediate between the resistance value when the recorded value is “0” and the resistance value when the recorded value is “1” in the magnetoresistive element 11 is set. Then, a predetermined current is made to flow through both the reference cell and the magnetoresistive element 11, the voltages at both ends of the reference cell and the magnetoresistive element 11 are detected at that time, and both voltages are compared to determine the resistance of the reference cell. It is determined whether the value is larger or the resistance value of the magnetoresistive element 11 is larger, and the data recorded in the magnetoresistive element 11 is determined.
【００１３】そのような読み出し回路として、例えば、
米国特許第６２０５０７３号明細書に記載されたものが
ある。この読み出し回路では、定電流回路を用いるとも
に参照セルを流れる電流を電圧値に変換し、また、別の
定電流回路を用いるとともに磁気抵抗素子を流れる電流
を電圧値に変換し、両方の電圧値を比較することによ
り、磁気抵抗素子に記録されたデータを読み出すように
している。As such a readout circuit, for example,
Some are described in US Pat. No. 6,205,073. In this read circuit, a constant current circuit is used and the current flowing through the reference cell is converted into a voltage value.In addition, another constant current circuit is used and the current flowing through the magnetoresistive element is converted into a voltage value. The data recorded in the magnetoresistive element is read by comparing the above.
【００１４】[0014]
【発明が解決しようとする課題】しかしながら、上述し
た従来の読み出し回路では、定電流回路を備えるととも
に電流−電圧（Ｉ−Ｖ）変換を参照セル側及び磁気抵抗
素子側の両方で行っているので回路規模が大きくなりが
ちである。また、電源と接地電位との間に定電流回路が
挿入される構成であるので、動作電圧が高くなりがちで
ある。However, in the above-described conventional read circuit, the constant current circuit is provided and the current-voltage (IV) conversion is performed on both the reference cell side and the magnetoresistive element side. The circuit scale tends to be large. Moreover, since the constant current circuit is inserted between the power supply and the ground potential, the operating voltage tends to increase.
【００１５】そこで本発明の目的は、磁気抵抗素子をメ
モリ素子として用いる磁気メモリ装置に適し、回路規模
を小さくでき、かつ、動作電圧を低くすることができる
読み出し回路を提供することにある。Therefore, an object of the present invention is to provide a read circuit suitable for a magnetic memory device using a magnetoresistive element as a memory element, capable of reducing the circuit scale and lowering the operating voltage.
【００１６】[0016]
【課題を解決するための手段】本発明の磁気メモリ装置
の読み出し回路は、磁気抵抗素子を有するメモリセルに
記録された情報を読み出す磁気メモリ装置の読み出し回
路であって、磁気抵抗素子に対して直列に接続される参
照セルと、磁気抵抗素子と前記参照セルとの接続点の電
位と基準電位とを比較する比較器と、を有する。A read circuit of a magnetic memory device according to the present invention is a read circuit of a magnetic memory device for reading information recorded in a memory cell having a magnetoresistive element, and It has a reference cell connected in series and a comparator for comparing the potential at the connection point between the magnetoresistive element and the reference cell with the reference potential.
【００１７】本発明は、磁気抵抗素子に記録された情報
に応じて、磁気抵抗素子と参照セルとの接続点の第２の
電位が基準電位としての第１の電位よりも大きくなった
り小さくなったりするようにしておいて、比較器によっ
て第１の電位と第２の電位との大小関係を検出すること
により、磁気抵抗素子に記録された情報を読み出そうと
するものである。このような観点から、参照セルとして
は、磁気抵抗素子がとり得る２つの抵抗値の中間の抵抗
値、又は磁気抵抗素子がとり得る２つの抵抗値のいずれ
かを用い、参照セル及び磁気抵抗素子が電源電位と接地
電位との間に直列に設けられるようにする。参照セルの
抵抗値として、磁気抵抗素子がとり得る２つの抵抗値の
中間の抵抗値を用いた場合、電源電位と接地電位との間
の電位の半分の電位を第１の電位とする。又、この場合
基準電位は、電源電位と接地電位との間に直列に挿入さ
れ相互に同じ抵抗値を有する２本の抵抗を用いることで
決定できる。また、比較器としては、第１の電位が入力
する第１の入力端子と第２の電位が入力する第２の入力
端子とを有し、第１の電位及び第２の電位の大小関係に
応じて“０”及び“１”に対応する論理レベルのいずれ
かを出力するコンパレータを用いることができる。According to the present invention, the second potential at the connection point between the magnetoresistive element and the reference cell becomes larger or smaller than the first potential as the reference potential according to the information recorded in the magnetoresistive element. In such a case, the comparator detects the magnitude relationship between the first potential and the second potential to read the information recorded in the magnetoresistive element. From this point of view, as the reference cell, either the intermediate resistance value of the two resistance values that the magnetoresistive element can take or the two resistance values that the magnetoresistive element can take is used, and the reference cell and the magnetoresistive element are used. Are provided in series between the power supply potential and the ground potential. When the resistance value of the reference cell is an intermediate resistance value between two possible resistance values of the magnetoresistive element, half the potential between the power supply potential and the ground potential is set as the first potential. Further, in this case, the reference potential can be determined by using two resistors which are inserted in series between the power source potential and the ground potential and have the same resistance value to each other. In addition, the comparator has a first input terminal to which the first potential is input and a second input terminal to which the second potential is input, and has a magnitude relation between the first potential and the second potential. Accordingly, a comparator that outputs any of the logic levels corresponding to "0" and "1" can be used.
【００１８】このような本発明の構成では、抵抗分割に
よって決定される電圧を検出するので、定電流回路を用
いるとともに参照電流側及びセル電流側の両方で電流−
電圧変換を行う従来の構成に比べ、回路規模を小さくす
ることができる。また、電圧降下が大きい定電流回路を
用いなく済むので、動作電圧を低くすることが可能であ
る。具体的には、磁気抵抗素子の読み出し電圧（読み出
し時に磁気抵抗素子に印加される電圧）の２倍程度の電
源電圧で済む。In such a structure of the present invention, since the voltage determined by the resistance division is detected, a constant current circuit is used and the current-
The circuit scale can be reduced as compared with the conventional configuration in which voltage conversion is performed. Further, since it is not necessary to use a constant current circuit having a large voltage drop, it is possible to reduce the operating voltage. Specifically, a power supply voltage about twice the read voltage of the magnetoresistive element (voltage applied to the magnetoresistive element at the time of reading) is sufficient.
【００１９】[0019]
【発明の実施の形態】次に、本発明の好ましい実施の形
態について、図面を参照して説明する。図１は本発明の
実施の一形態の読み出し回路の構成を示す回路図であ
る。ここでは、図２に示した構成においてメモリセルア
レイの１行分のメモリセルからビット線４４を介してデ
ータを読み出す読み出し回路２０として、本実施の形態
の読み出し回路を説明する。BEST MODE FOR CARRYING OUT THE INVENTION Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a read circuit according to an embodiment of the present invention. Here, the read circuit of this embodiment will be described as the read circuit 20 which reads data from the memory cells of one row of the memory cell array through the bit lines 44 in the configuration shown in FIG.
【００２０】ここでメモリセルアレイのビット線４４に
は、複数のメモリセルが接続しており、各メモリセルに
おいて、磁気抵抗素子１１の一端がビット線４４に接続
し、磁気抵抗素子１１の他端とスイッチ素子１２の一端
が相互に接続し、スイッチ素子１２の他端が接地されて
いる。この実施の形態において、磁気抵抗素子１１とし
ては、２層の強磁性体層間に非磁性層を挟み込んだもの
であって、強磁性体層における磁化の方向に応じて二値
の情報（“０”，“１”）を記録し、記録された情報に
応じて電気抵抗値が変化するものが使用される。特に、
非磁性層がトンネル絶縁膜であるものが好ましく使用さ
れる。各強磁性体層は、面内磁化膜であってもよいが、
垂直磁化膜であることが好ましい。Here, a plurality of memory cells are connected to the bit line 44 of the memory cell array. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line 44 and the other end of the magnetoresistive element 11 is connected. And one end of the switch element 12 are connected to each other, and the other end of the switch element 12 is grounded. In this embodiment, as the magnetoresistive element 11, a nonmagnetic layer is sandwiched between two ferromagnetic layers, and binary information (“0” is set according to the direction of magnetization in the ferromagnetic layers). "," 1 ") is recorded, and the electric resistance value changes according to the recorded information. In particular,
The nonmagnetic layer is preferably a tunnel insulating film. Each ferromagnetic layer may be an in-plane magnetized film,
It is preferably a perpendicular magnetization film.
【００２１】読み出し回路２０には、参照セル５０が設
けられている。参照セル５０は、磁気抵抗素子１１にお
いて記録値が“０”のときの抵抗値と記録値が“１”で
あるときの抵抗値との中間となる抵抗値を有するもので
ある。例えば、メモリセルの各磁気抵抗素子１１と同一
プロセスで参照用の磁気抵抗素子を４個形成し、このう
ち２個を直列に接続して一方に“１”を他方に“０”を
記録し、残りの２個も直列に接続して一方に“１”を他
方に“０”を記録し、このように直列接続されたものを
相互に並列に接続することによって、ここで使用できる
参照セル５０を得ることができる。参照セル５０の一端
はビット線４４に接続し、参照セル５０の他端には電源
電圧Ｖccが供給されている。参照セル５０の抵抗値をＲ
REFとする。The read circuit 20 is provided with a reference cell 50. The reference cell 50 has a resistance value that is intermediate between the resistance value when the recorded value is “0” and the resistance value when the recorded value is “1” in the magnetoresistive element 11. For example, four magnetoresistive elements for reference are formed in the same process as the magnetoresistive elements 11 of the memory cell, two of these are connected in series, and "1" is recorded on one side and "0" is recorded on the other side. , Reference cells that can be used here by connecting the remaining two in series and recording “1” in one and “0” in the other, and connecting those connected in series in parallel with each other 50 can be obtained. One end of the reference cell 50 is connected to the bit line 44, and the power supply voltage V cc is supplied to the other end of the reference cell 50. The resistance value of the reference cell 50 is R
REF .
【００２２】読み出し回路２０は、さらに、２本の抵抗
５１，５２とコンパレータ（比較器）５３を備えてい
る。抵抗５１，５２は同じ抵抗値であり相互に直列に接
続されて電源Ｖccと接地点との間に挿入されている。コ
ンパレータ５３の一方の入力端子ａは、ビット線４４と
参照セル５０との接続点に接続し、コンパレータ５３の
他方の入力端子ｂは、抵抗５１，５２の中点（相互接続
点）に接続している。コンパレータ５３の出力はこの読
み出し回路２０の出力端子５４に接続している。コンパ
レータ５３は、その２つの入力端子ａ，ｂへの入力電圧
の大小関係に応じて、“０”または“１”に対応する論
理レベルの信号を出力するものである。The read circuit 20 further includes two resistors 51 and 52 and a comparator (comparator) 53. The resistors 51 and 52 have the same resistance value, are connected in series with each other, and are inserted between the power source Vcc and the ground point. One input terminal a of the comparator 53 is connected to the connection point between the bit line 44 and the reference cell 50, and the other input terminal b of the comparator 53 is connected to the middle point (interconnection point) of the resistors 51 and 52. ing. The output of the comparator 53 is connected to the output terminal 54 of the read circuit 20. The comparator 53 outputs a signal of a logic level corresponding to "0" or "1" according to the magnitude relationship between the input voltages to the two input terminals a and b.
【００２３】抵抗５１，５２には、個別部品としての抵
抗器、通常の半導体集積回路製造プロセスにより拡散抵
抗として形成されるものを使用することができるほか、
上述した参照セル５０と同じ構成のものを使用すること
ができる。As the resistors 51 and 52, resistors as individual parts, resistors formed as diffused resistors by a normal semiconductor integrated circuit manufacturing process can be used.
The same structure as the reference cell 50 described above can be used.
【００２４】次に、この読み出し回路の動作を説明す
る。ここでは、ビット線４４につながるメモリセルのう
ちの１つのメモリセルにおいてスイッチ素子１２がオン
状態となり、そのオン状態となったメモリセルの磁気抵
抗素子１１に記録されたデータ（“０”または“１”）
を読み出すものとする。読み出し対象の磁気抵抗素子１
１の抵抗値をＲMTJで表す。Next, the operation of this read circuit will be described. Here, the switch element 12 is turned on in one of the memory cells connected to the bit line 44, and the data (“0” or “0” recorded in the magnetoresistive element 11 of the turned on memory cell). 1 ")
Should be read. Magnetoresistive element 1 to be read
The resistance value of 1 is represented by R MTJ .
【００２５】参照セル５０と選択された磁気抵抗素子１
１とは、電源Ｖccと接地電位との間に直列に挿入される
こととなるので、コンパレータ５３の入力端子ａの電位
は、電源電圧Ｖccを直列接続の抵抗ＲMTJと抵抗ＲREFと
によって分圧した値となる。一方、抵抗５１，５２の抵
抗値が等しいことにより、これら抵抗５１，５２の中点
すなわちコンパレータ５３の入力端子ｂの電位は、電源
電圧Ｖccのちょうど半分の電位すなわちＶcc／２となっ
ている。Reference cell 50 and selected magnetoresistive element 1
Since 1 is inserted in series between the power supply V cc and the ground potential, the potential of the input terminal a of the comparator 53 is the resistance R MTJ and the resistance R REF connected in series with the power supply voltage V cc. It becomes the value divided by. On the other hand, since the resistance values of the resistors 51 and 52 are equal, the potential of the midpoint of the resistors 51 and 52, that is, the potential of the input terminal b of the comparator 53 is just half the power source voltage Vcc , that is, Vcc / 2. There is.
【００２６】参照セル５０の抵抗値ＲREFは、上述した
ように、“０”が記録されたときの磁気抵抗素子１１の
抵抗値と“１”が記録されたときの磁気抵抗素子１１の
抵抗値の中間の値とされている。ここで、磁気抵抗素子
１１がとり得る２つの抵抗値のうち高い方を“０”に低
い方を“１”に割り当てたものとする。選択された磁気
抵抗素子１１に“０”が記録されていれば、その抵抗値
ＲMTJは参照セル５０の抵抗値ＲREFよりも大きくなるの
で、コンパレータ５３の入力端子ａの電位はＶcc／２よ
り大きくなる。逆に、選択された磁気抵抗素子１１に
“１”が記録されていれば、その抵抗値ＲMTJは参照セ
ル５０の抵抗値ＲREFよりも小さくなるので、コンパレ
ータ５３の入力端子ａの電位はＶcc／２より小さくな
る。コンパレータ５３のもう１つの入力端子ｂの電位は
Ｖcc／２に固定されているから、結局、選択された磁気
抵抗素子１１に“０”が記録されていればコンパレータ
５３において入力端子ａの方が入力端子ｂより電位が高
くなり、“１”が記録されていれば入力端子ｂの方が入
力端子ａより電位が高くなる。コンパレータ５３は、入
力端子ａと入力端子ｂの電位の大小関係に応じて“０”
または“１”を出力するから、出力端子５４には、選択
された磁気抵抗素子１１に記録された情報が読み出され
ることになる。As described above, the resistance value R REF of the reference cell 50 is the resistance value of the magnetoresistive element 11 when "0" is recorded and the resistance value of the magnetoresistive element 11 when "1" is recorded. It is considered to be an intermediate value. Here, of the two possible resistance values of the magnetoresistive element 11, the higher one is assigned to "0" and the lower one is assigned to "1". If "0" is recorded in the selected magnetoresistive element 11, its resistance value R MTJ becomes larger than the resistance value R REF of the reference cell 50, so the potential of the input terminal a of the comparator 53 is V cc / Greater than 2. On the contrary, if "1" is recorded in the selected magnetoresistive element 11, the resistance value R MTJ becomes smaller than the resistance value R REF of the reference cell 50, so that the potential of the input terminal a of the comparator 53 is It is smaller than Vcc / 2. Since the potential of the other input terminal b of the comparator 53 is fixed at V cc / 2, after all, if “0” is recorded in the selected magnetoresistive element 11, the input terminal a of the comparator 53 will be the one. Has a higher potential than the input terminal b, and if "1" is recorded, the input terminal b has a higher potential than the input terminal a. The comparator 53 is "0" according to the magnitude relation between the potentials of the input terminal a and the input terminal b.
Alternatively, since "1" is output, the information recorded in the selected magnetoresistive element 11 is read out to the output terminal 54.
【００２７】以上の説明においては、磁気抵抗素子１１
がとり得る２つの抵抗値のうち高い方を“０”に低い方
を“１”に割り当てるものとしたが、磁気抵抗素子１１
がとり得る２つの抵抗値のうち高い方を“１”に低い方
を“０”に割り当てた場合であっても、上述と同様の動
作により、選択された磁気抵抗素子１１に記録された情
報が出力端子５４から読み出されることになる。In the above description, the magnetoresistive element 11 is used.
The higher one of the two possible resistance values is assigned to “0” and the lower one is assigned to “1”.
Even when the higher one of the two possible resistance values is assigned to “1” and the lower one is assigned to “0”, the information recorded in the selected magnetoresistive element 11 is obtained by the same operation as described above. Will be read from the output terminal 54.
【００２８】また、当業者には自明のことであるが、電
源Ｖccと接地電位とは相対的なものであるので、メモリ
セルにおいて磁気抵抗素子１１が接地電位でなく電源電
位に接続するようにしてもよい。その場合は、参照セル
５０は電源でなく接地電位に接続されることになる。As will be apparent to those skilled in the art, since the power supply V cc and the ground potential are relative to each other, the magnetoresistive element 11 in the memory cell should be connected to the power supply potential instead of the ground potential. You may In that case, the reference cell 50 is connected to the ground potential instead of the power supply.
【００２９】以上、本発明の好ましい実施の形態につい
て説明した。本発明の読み出し回路は、面内磁化膜を用
いた磁気抵抗素子をメモリ素子として用いる磁気メモリ
装置にも、垂直磁化膜を用いた磁気抵抗素子をメモリ素
子として用いる磁気メモリ装置にも、等しく適用できる
ものである。The preferred embodiment of the present invention has been described above. The read circuit of the present invention is equally applicable to a magnetic memory device using a magnetoresistive element using an in-plane magnetized film as a memory element and a magnetic memory device using a magnetoresistive element using a perpendicular magnetized film as a memory element. It is possible.
【００３０】[0030]
【発明の効果】以上説明したように本発明は、参照セル
と磁気抵抗素子との抵抗分割によって決定される電圧を
検出するので、定電流回路を用いるとともに参照電流側
及びセル電流側の両方で電流−電圧変換を行う従来の構
成に比べ、回路規模を小さくすることができるととも
に、動作電圧を低くすることができるという効果があ
る。As described above, the present invention detects the voltage determined by the resistance division of the reference cell and the magnetoresistive element. Therefore, a constant current circuit is used and both the reference current side and the cell current side are used. As compared with the conventional configuration that performs current-voltage conversion, the circuit scale can be reduced and the operating voltage can be reduced.
【図１】本発明の実施の一形態の読み出し回路の構成を
示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a read circuit according to an embodiment of the present invention.
【図２】ＭＲＡＭのメモリセルアレイの構成の一例を示
す回路図である。FIG. 2 is a circuit diagram showing an example of a configuration of a memory cell array of MRAM.
【図３】メモリセルの構成の一例を示す断面図である。FIG. 3 is a cross-sectional view showing an example of the configuration of a memory cell.
１１ 磁気抵抗素子 １２，１５，１６ スイッチ素子 １３ 書き込み回路 １４ 電源回路 ２０ 読み出し回路 ３０ 半導体基板 ３１ 素子分離領域 ３２ ドレイン領域 ３３ ソース領域 ３４ ゲート絶縁膜 ３５，ＷＬ１〜ＷＬ３ ワード線 ３６〜３８，４３，４５ 層間絶縁膜 ３９，４１ プラグ ４０ 接地線 ４２，ＷＷＬ１〜ＷＷＬ３ 書き込み線 ４４，ＢＬ１〜ＢＬ３ ビット線 ５０ 参照セル ５１，５２ 抵抗 ５３ コンパレータ ５４ 出力端子 ａ，ｂ 入力端子 11 Magnetoresistive element 12,15,16 switch element 13 Writing circuit 14 power supply circuit 20 readout circuit 30 Semiconductor substrate 31 element isolation region 32 drain region 33 Source Area 34 Gate insulating film 35, WL1-WL3 word lines 36-38, 43, 45 Interlayer insulating film 39, 41 plug 40 ground wire 42, WWL1 to WWL3 write line 44, BL1 to BL3 bit lines 50 reference cells 51,52 resistance 53 Comparator 54 output terminals a, b input terminals
Claims (9)
された情報を読み出す磁気メモリ装置の読み出し回路で
あって、 前記磁気抵抗素子に対して直列に接続される参照セル
と、 前記磁気抵抗素子と前記参照セルとの接続点の電位と基
準電位とを比較する比較器と、 を有する磁気メモリ装置の読み出し回路。1. A read circuit of a magnetic memory device for reading information recorded in a memory cell having a magnetoresistive element, the reference cell being connected in series to the magnetoresistive element, and the magnetoresistive element. A read circuit of a magnetic memory device, comprising: a comparator that compares a potential at a connection point with the reference cell with a reference potential.
り得る２つの抵抗値の中間の抵抗値を有する、請求項１
に記載の磁気メモリ装置の読み出し回路。2. The reference cell has a resistance value intermediate between two resistance values that the magnetoresistive element can have.
A read circuit of the magnetic memory device according to 1.
間の電位の半分の電位であり、 前記参照セル及び前記磁気抵抗素子が、前記電源電位と
前記接地電位との間に直列に設けられる請求項１または
２に記載の磁気メモリ装置の読み出し回路。3. The reference potential is half the potential between a power supply potential and a ground potential, and the reference cell and the magnetoresistive element are provided in series between the power supply potential and the ground potential. The read circuit of the magnetic memory device according to claim 1 or 2.
地電位との間に直列に挿入され相互に同じ抵抗値を有す
る２本の抵抗によって決定される、請求項３に記載の磁
気メモリ装置の読み出し回路。4. The magnetic memory device according to claim 3, wherein the reference potential is determined by two resistors that are inserted in series between the power source potential and the ground potential and have the same resistance value. Read circuit.
第１の入力端子と、前記磁気抵抗素子と前記参照セルと
の接続点の電位を第２の電位とすると、前記第２の電位
が入力する第２の入力端子とを有し、前記基準電位と前
記第２の電位との大小関係に応じて、“０”及び“１”
に対応する論理レベルのいずれかを出力するコンパレー
タである、請求項１乃至４いずれか１項に記載の磁気メ
モリ装置の読み出し回路5. The second potential, wherein the comparator has a first input terminal to which the reference potential is input and a potential at a connection point between the magnetoresistive element and the reference cell as a second potential. Has a second input terminal for inputting, and "0" and "1" according to the magnitude relation between the reference potential and the second potential.
5. The read circuit of the magnetic memory device according to claim 1, wherein the read circuit is a comparator that outputs any of the logic levels corresponding to.
数のメモリセルとを備え、 前記各メモリセルごとに、前記磁気抵抗素子と当該メモ
リセルを選択するためのスイッチ素子とが、一端が前記
ビット線に接続し他端が接地されあるいは電源に接続す
るように、直列に設けられ、 前記参照セルは前記ビット線に接続することにより前記
磁気抵抗素子に直列に接続する、請求項１乃至５のいず
れか１項に記載の磁気メモリ装置の読み出し回路。6. The magnetic memory device comprises a bit line and a plurality of memory cells, and one end of the magnetic resistance element and a switch element for selecting the memory cell are provided for each memory cell. 2. The reference cell is connected in series so as to be connected to the bit line and grounded at the other end or connected to a power supply, and the reference cell is connected to the magnetoresistive element in series by connecting to the bit line. 6. The read circuit of the magnetic memory device according to claim 5.
間に非磁性層を挟み込んだものであり、前記強磁性体層
における磁化の方向に応じて二値の情報を記録し、記録
された情報に応じて電気抵抗値が変化するものである、
請求項１乃至６のいずれか１項に記載の磁気メモリ装置
の読み出し回路。7. The magnetoresistive element is one in which a non-magnetic layer is sandwiched between two ferromagnetic layers, and binary information is recorded according to the direction of magnetization in the ferromagnetic layer. The electrical resistance value changes according to the information given,
A read circuit of the magnetic memory device according to claim 1.
求項７に記載の磁気メモリ装置の読み出し回路。8. The read circuit of the magnetic memory device according to claim 7, wherein the non-magnetic layer is a tunnel insulating film.
求項７または８に記載の磁気メモリ装置の読み出し回
路。9. The read circuit of the magnetic memory device according to claim 7, wherein each of the ferromagnetic layers is a perpendicular magnetization film.
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|---|---|---|---|---|
| WO2006064559A1 (en) * | 2004-12-15 | 2006-06-22 | Fujitsu Limited | Magnetic memory and its reading method |
| KR100884301B1 (en) * | 2007-05-14 | 2009-02-18 | 후지쯔 가부시끼가이샤 | Magnetic memory and its reading method |
| JP2010009711A (en) * | 2008-06-30 | 2010-01-14 | Toshiba Corp | Semiconductor memory device |
| JP2013191873A (en) * | 2013-05-21 | 2013-09-26 | Nec Corp | Magnetic random access memory |
| JP2014010885A (en) * | 2012-06-29 | 2014-01-20 | Samsung Electronics Co Ltd | Sense amplifier circuit of resistive memory |
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|---|---|---|---|---|
| KR102169681B1 (en) | 2013-12-16 | 2020-10-26 | 삼성전자주식회사 | Sense amplifier, nonvolatile memory device and sensing method using thereof |
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| JPH11213650A (en) * | 1998-01-28 | 1999-08-06 | Canon Inc | Magnetic thin film device and magnetic thin film memory device and recording and reproducing method for the same |
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| KR100884301B1 (en) * | 2007-05-14 | 2009-02-18 | 후지쯔 가부시끼가이샤 | Magnetic memory and its reading method |
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