JP4775926B2 - Read circuit of magnetic memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a read circuit for a nonvolatile memory device, and more particularly to a read circuit suitable for a magnetic memory device having memory cells using magnetoresistive elements.
[0002]
[Prior art]
In a magnetic material such as a ferromagnetic material, a magnetoresistive effect is known in which the electric resistance changes depending on the direction of magnetization, the presence or absence of magnetization, and the rate of change of the electric resistance value at that time is expressed as a magnetoresistance ratio (MR ratio). ; Magneto-Resistance Ratio). Materials having a large magnetoresistance ratio include giant magnetoresistive (GMR) materials and super magnetoresistive (CMR) materials, which are generally metals, alloys, composite oxides, etc. It is. For example, Fe, Ni, Co, Gd, or Tb, and alloys, there are materials such as composite oxide such as _{La X Sr 1-X MnO 9} , La X Ca 1-X MnO 9. In general, a ferromagnetic material has a characteristic that magnetization generated in the ferromagnetic material by a magnetic field applied from the outside remains even after the external magnetic field is removed (this is called residual magnetization).
[0003]
Therefore, if a ferromagnetic material is used as a magnetoresistive material and the residual magnetization of the ferromagnetic material is used, a nonvolatile memory that stores information by selecting an electrical resistance value depending on the magnetization direction and the presence or absence of magnetization can be configured. it can. Such a non-volatile memory is called a magnetic memory (MRAM (Magnetic Random Access Memory)).
[0004]
In recent years, many MRAMs that are being developed store information by the remanent magnetization of a ferromagnetic material of a giant magnetoresistive material. By detecting changes in electrical resistance values caused by differences in the magnetization direction, The method of reading out the information is adopted. Further, by changing the magnetization direction of the ferromagnetic memory cell by a magnetic field induced by passing a current through the write wiring, information can be written to the memory cell and the information can be rewritten.
[0005]
As a memory cell of the MRAM, a tunnel magnetoresistive element (TMR; Tunnel Magneto-Resistance) having a structure in which a tunnel insulating film (an electrical insulating film having a thickness that allows a tunnel current to flow) is sandwiched between two ferromagnetic layers is used. MTJ (Magnetic Tunnel Junction) has a high rate of change in magnetoresistance (MR ratio) and is expected to be the device most practical. As such a memory cell, a configuration in which a tunnel insulating film is sandwiched between two in-plane magnetization films has been studied. However, in the case of a memory cell using an in-plane magnetic film, the MR ratio decreases, the required write current increases as the memory cell becomes smaller, and the operating point (hysteresis indicating the magnetic characteristics of the memory cell) is increased. It is known that there is a problem to be solved such as a movement of a loop. On the other hand, the applicant of the present application has proposed a configuration in which a nonmagnetic layer as a tunnel insulating film is sandwiched between two perpendicular magnetization films in Japanese Patent Application Laid-Open No. 11-213650. Even when the memory cell is miniaturized by using the perpendicular magnetization film, the reduction in MR ratio and the increase in the write current are suppressed, and the shift in the hysteresis loop is also suppressed, and the memory has excellent characteristics. A cell is obtained.
[0006]
FIG. 2 is a circuit diagram showing an example of the configuration of an MRAM memory cell array.
[0007]
One memory cell includes a magnetoresistive element (memory element) 11 expressed as a variable resistor, and a switch element 12 having one end connected to the magnetoresistive element 11. The switch element 12 is typically composed of a MOS (Metal-Oxide-Semiconductor) field effect transistor, and the other end is grounded. A memory cell array is configured by arranging a plurality of such memory cells in a two-dimensional matrix. Here, assuming that the horizontal arrangement in the figure is called a row and the vertical arrangement is called a column, in the figure, an area of 3 rows × 3 columns in the memory cell array is shown. Bit lines BL1 to BL3 extending in the row direction are provided for each row, and word lines WL1 to WL3 extending in the column direction are provided for each column. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line of the corresponding row, and the gate of the switch element 12 is connected to the word line of the corresponding column.
[0008]
The broken lines in the figure indicate write lines WWL1 to WWL3 for writing data to each memory cell, and these write lines are provided for each column. In the illustrated example, the write lines WWL1 to WWL3 are folded at the other end of the column, and a predetermined write current is caused to flow by the write circuit 13 provided for each column. Each write circuit 13 is supplied with a current for generating a write current from the power supply circuit 14.
[0009]
FIG. 3 is a cross-sectional view showing an example of the configuration of the memory cell. In the figure, two memory cells arranged in the column direction are shown.
[0010]
An element isolation region 31 is formed on the semiconductor substrate 30, and a drain region 32 and a source region 33 of the switch element 12 are provided. A region sandwiched between the drain region 32 and the source region 33 is interposed via a gate insulating film 34. Thus, a word line 35 (corresponding to the word lines WL1 to WL3 in FIG. 2) also serving as the gate electrode of the switch element 12 is formed. In the illustrated example, the two switch elements 12 also serve as the source region 33, and interlayer insulating films 36, 37 and 38 are provided in this order so as to cover such switch elements 12. Yes. The interlayer insulating film 38 is formed particularly thin. The source region 33 is connected to a ground line 40 formed on the interlayer insulating film 36 via a plug 39, and the drain region 32 is connected to a magnetoresistive element formed on the interlayer insulating film 38 via a plug 41. 11 is connected to the lower surface. In the illustrated example, the magnetoresistive element 11 has a configuration in which a tunnel insulating film, which is a nonmagnetic layer, is sandwiched between two perpendicular magnetization films as described in Japanese Patent Application Laid-Open No. 11-213650. . A write line 42 (corresponding to the write lines WWL1 to WWL3 in FIG. 2) is formed below the interlayer insulating film 38 so as to be engraved in the interlayer insulating film 37. An interlayer insulating film 43 is formed so as to fill a region between the adjacent magnetoresistive elements 11, and the upper surface of the magnetoresistive element 11 is formed on the interlayer insulating film 43 and extends in the horizontal direction in the figure. 2 corresponding to the bit lines BL1 to BL3 in FIG. Further, an interlayer insulating film 45 that also serves as a protective film is formed so as to cover the interlayer insulating film 43 and the bit line 44.
[0011]
Data is written into the memory cell in the memory cell array shown in FIG. 2 by writing the write value (“0” or “1”) to the write line of the column to which the memory cell (selected memory cell) to which data is to be written belongs. A write magnetic field is generated by supplying a write current with a polarity corresponding to the current, and an assist magnetic field is generated by flowing an assist current to the bit line of the row to which the memory cell belongs, and the selection is made by the sum of the write magnetic field and the assist magnetic field. Data is written only to the memory cells that have been written. In order to pass an assist current to the bit line of the selected row, a switch element 15 for connecting the power supply circuit 14 and the bit line is provided at one end of each bit line, and the other end at the other end. A switch element 16 for grounding the bit line is provided. The switch elements 15 and 16 are typically configured by MOS field effect transistors.
[0012]
In such a memory cell array, a read circuit 20 is provided at one end of each of the bit lines BL1 to BL3. The read circuit 20 reads data written in the memory cell from the memory cell in the column selected by the word lines WL1 to WL3. Specifically, the switch elements 15 and 16 are all turned off, the switch elements 12 in a specific column are turned on by the word line, and the resistance value of the magnetoresistive element 11 of the target memory cell from the read circuit 20 side. And “0” or “1” is recorded based on the result. In this case, instead of measuring the absolute value of the resistance value of the magnetoresistive element 11, for example, a reference cell is provided in the readout circuit 20, and the reference cell and the resistance of the magnetoresistive element 11 are compared in magnitude. It is determined whether it is “1” or “1”. In the reference cell, a resistance value that is intermediate between the resistance value when the recording value is “0” and the resistance value when the recording value is “1” in the magnetoresistive element 11 is set. Then, a predetermined current is passed through both the reference cell and the magnetoresistive element 11, and then the voltages at both ends of both the reference cell and the magnetoresistive element 11 are detected, and the voltages of both are compared, thereby comparing the resistance of the reference cell. It is determined whether the value is larger or the resistance value of the magnetoresistive element 11 is larger, and data recorded in the magnetoresistive element 11 is determined.
[0013]
An example of such a read circuit is described in US Pat. No. 6,205,073. In this readout circuit, a constant current circuit is used and the current flowing through the reference cell is converted to a voltage value, and another constant current circuit is used and the current flowing through the magnetoresistive element is converted to a voltage value. Are read out, the data recorded in the magnetoresistive element is read out.
[0014]
[Problems to be solved by the invention]
However, the conventional read circuit described above tends to have a large circuit scale because it includes a constant current circuit and performs current-voltage (IV) conversion on both the reference cell side and the magnetoresistive element side. Further, since the constant current circuit is inserted between the power supply and the ground potential, the operating voltage tends to be high.
[0015]
SUMMARY OF THE INVENTION An object of the present invention is to provide a read circuit that is suitable for a magnetic memory device using a magnetoresistive element as a memory element, can reduce the circuit scale, and can reduce the operating voltage.
[0016]
[Means for Solving the Problems]
A read circuit of a magnetic memory device of the present invention is a read circuit of a magnetic memory device that reads information recorded in a memory cell having a magnetoresistive element, and a reference cell connected in series to the magnetoresistive element; possess a comparator for comparing the potential with the reference potential at the connection point between the magnetoresistive element and see the cell, the reference cell will have a intermediate resistance values of the two resistance values magnetoresistive element can take .
[0017]
According to the present invention, the second potential at the connection point between the magnetoresistive element and the reference cell becomes larger or smaller than the first potential as the reference potential according to the information recorded in the magnetoresistive element. The information recorded in the magnetoresistive element is read out by detecting the magnitude relationship between the first potential and the second potential by the comparator. From this point of view, as the reference cell, with intermediate resistance values of the two resistance values magnetoresistive element can take, the reference cells and the magnetoresistive element is a power supply potential to be provided in series between the ground potential To. When a resistance value intermediate between two resistance values that can be taken by the magnetoresistive element is used as the resistance value of the reference cell, a potential that is half of the potential between the power supply potential and the ground potential is set as the first potential. In this case, the reference potential can be determined by using two resistors inserted in series between the power supply potential and the ground potential and having the same resistance value. The comparator has a first input terminal to which the first potential is input and a second input terminal to which the second potential is input, and the magnitude relationship between the first potential and the second potential is determined. Accordingly, a comparator that outputs any one of logic levels corresponding to “0” and “1” can be used.
[0018]
In such a configuration of the present invention, since the voltage determined by resistance division is detected, a circuit is used as compared with the conventional configuration that uses a constant current circuit and performs current-voltage conversion on both the reference current side and the cell current side. The scale can be reduced. In addition, since it is not necessary to use a constant current circuit with a large voltage drop, the operating voltage can be lowered. Specifically, a power supply voltage that is about twice the read voltage of the magnetoresistive element (the voltage applied to the magnetoresistive element at the time of reading) is sufficient.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a readout circuit according to an embodiment of the present invention. Here, the read circuit of this embodiment will be described as the read circuit 20 that reads data from the memory cells for one row of the memory cell array through the bit line 44 in the configuration shown in FIG.
[0020]
Here, a plurality of memory cells are connected to the bit line 44 of the memory cell array. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line 44, and the other end of the magnetoresistive element 11 and a switch element are connected. One end of 12 is connected to each other, and the other end of the switch element 12 is grounded. In this embodiment, the magnetoresistive element 11 has a nonmagnetic layer sandwiched between two ferromagnetic layers, and binary information (“0” depending on the direction of magnetization in the ferromagnetic layer). "," 1 ") is recorded, and the electric resistance value is changed according to the recorded information. In particular, the nonmagnetic layer is preferably a tunnel insulating film. Each ferromagnetic layer may be an in-plane magnetization film, but is preferably a perpendicular magnetization film.
[0021]
A reference cell 50 is provided in the read circuit 20. The reference cell 50 has a resistance value that is intermediate between the resistance value when the recording value is “0” and the resistance value when the recording value is “1” in the magnetoresistive element 11. For example, four magnetoresistive elements for reference are formed in the same process as each magnetoresistive element 11 of the memory cell, and two of them are connected in series, and “1” is recorded on one and “0” is recorded on the other. Reference cell which can be used here by connecting the remaining two in series, recording “1” on one side and “0” on the other, and connecting those connected in series in parallel with each other 50 can be obtained. One end of the reference cell 50 is connected to the bit line 44, and the other end of the reference cell 50 is supplied with the power supply voltage _Vcc . Let the resistance value of the reference cell 50 be R _REF .
[0022]
The readout circuit 20 further includes two resistors 51 and 52 and a comparator (comparator) 53. The resistors 51 and 52 have the same resistance value and are connected in series with each other and inserted between the power source _Vcc and the ground point. One input terminal a of the comparator 53 is connected to the connection point between the bit line 44 and the reference cell 50, and the other input terminal b of the comparator 53 is connected to the middle point (interconnection point) of the resistors 51 and 52. ing. The output of the comparator 53 is connected to the output terminal 54 of the readout circuit 20. The comparator 53 outputs a signal having a logic level corresponding to “0” or “1” in accordance with the magnitude relationship between the input voltages to the two input terminals a and b.
[0023]
As the resistors 51 and 52, resistors as individual components, those formed as diffused resistors by a normal semiconductor integrated circuit manufacturing process can be used, and those having the same configuration as the reference cell 50 described above are used. be able to.
[0024]
Next, the operation of this readout circuit will be described. Here, the switch element 12 is turned on in one of the memory cells connected to the bit line 44, and the data (“0” or “0” recorded in the magnetoresistive element 11 of the memory cell in the on state is turned on. 1 ") is read out. The resistance value of the magnetoresistive element 11 to be read is represented by R _MTJ .
[0025]
Since the reference cell 50 and the selected magnetoresistive element 11 are inserted in series between the power supply _Vcc and the ground potential, the potential of the input terminal a of the comparator 53 is connected to the power supply voltage _Vcc in series. The value is divided by the connection resistance R _MTJ and resistance R _REF . On the other hand, since the resistance values of the resistors 51 and 52 are equal, the midpoint of the resistors 51 and 52, that is, the potential of the input terminal b of the comparator 53 becomes exactly half the power supply voltage _Vcc , that is, V _cc / 2. Yes.
[0026]
As described above, the resistance value R _REF of the reference cell 50 is an intermediate between the resistance value of the magnetoresistive element 11 when “0” is recorded and the resistance value of the magnetoresistive element 11 when “1” is recorded. Value. Here, it is assumed that the higher one of the two possible resistance values of the magnetoresistive element 11 is assigned to “0” and the lower one is assigned to “1”. If “0” is recorded in the selected magnetoresistive element 11, the resistance value R _MTJ is larger than the resistance value R _REF of the reference cell 50, so the potential of the input terminal a of the comparator 53 is V _cc / Greater than 2. On the other hand, if “1” is recorded in the selected magnetoresistive element 11, the resistance value R _MTJ is smaller than the resistance value R _REF of the reference cell 50, so that the potential of the input terminal a of the comparator 53 is It becomes smaller than V _cc / 2. Since the potential of the other input terminal b of the comparator 53 is fixed at V _cc / 2, if “0” is recorded in the selected magnetoresistive element 11, the input terminal a in the comparator 53 Is higher than the input terminal b, and if “1” is recorded, the input terminal b has a higher potential than the input terminal a. Since the comparator 53 outputs “0” or “1” according to the magnitude relationship between the potentials of the input terminal a and the input terminal b, information recorded in the selected magnetoresistive element 11 is output to the output terminal 54. Will be read.
[0027]
In the above description, among the two resistance values that the magnetoresistive element 11 can take, the higher one is assigned to “0” and the lower one is assigned to “1”. Even when the higher one is assigned to “1” and the lower one is assigned to “0”, the information recorded in the selected magnetoresistive element 11 is read from the output terminal 54 by the same operation as described above. It will be.
[0028]
As will be apparent to those skilled in the art, since the power supply _Vcc and the ground potential are relative, the magnetoresistive element 11 may be connected to the power supply potential instead of the ground potential in the memory cell. Good. In that case, the reference cell 50 is connected to the ground potential instead of the power source.
[0029]
The preferred embodiments of the present invention have been described above. The readout circuit of the present invention is equally applicable to a magnetic memory device using a magnetoresistive element using an in-plane magnetic film as a memory element, and to a magnetic memory device using a magnetoresistive element using a perpendicular magnetic film as a memory element. It can be done.
[0030]
【The invention's effect】
As described above, the present invention detects the voltage determined by the resistance division between the reference cell and the magnetoresistive element, so that a constant current circuit is used and current-voltage conversion is performed on both the reference current side and the cell current side. Compared with the conventional configuration to be performed, the circuit scale can be reduced and the operating voltage can be lowered.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of a read circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a configuration of a memory cell array of an MRAM.
FIG. 3 is a cross-sectional view showing an example of a configuration of a memory cell.
[Explanation of symbols]
11 magnetoresistive elements 12, 15, 16 switch element 13 write circuit 14 power supply circuit 20 read circuit 30 semiconductor substrate 31 element isolation region 32 drain region 33 source region 34 gate insulating film 35, WL1 to WL3 word lines 36 to 38, 43, 45 Interlayer insulating film 39, 41 Plug 40 Ground line 42, WWL1 to WWL3 Write line 44, BL1 to BL3 Bit line 50 Reference cell 51, 52 Resistor 53 Comparator 54 Output terminal a, b Input terminal

Claims (8)

A read circuit of a magnetic memory device for reading information recorded in a memory cell having a magnetoresistive element,
A reference cell connected in series to the magnetoresistive element;
A comparator for comparing a potential at a connection point between the magnetoresistive element and the reference cell with a reference potential;
I have a,
The read circuit of a magnetic memory device, wherein the reference cell has a resistance value intermediate between two resistance values that the magnetoresistive element can take . The reference potential is half the potential between the power supply potential and the ground potential;
The read circuit of the magnetic memory device according to claim 1, wherein the reference cell and the magnetoresistive element are provided in series between the power supply potential and the ground potential. 3. The read circuit of the magnetic memory device according to claim 2 , wherein the reference potential is determined by two resistors inserted in series between the power supply potential and the ground potential and having the same resistance value. The comparator has a first input terminal to which the reference potential is input and a potential at a connection point between the magnetoresistive element and the reference cell as a second potential. And a comparator that outputs any one of logic levels corresponding to “0” and “1” according to a magnitude relationship between the reference potential and the second potential. The readout circuit of the magnetic memory device according to any one of claims 1 to 3 The magnetic memory device includes a bit line and a plurality of memory cells.
For each memory cell, the magnetoresistive element and a switch element for selecting the memory cell are provided in series so that one end is connected to the bit line and the other end is grounded or connected to a power source. ,
The reference cell is connected in series with the magnetoresistive element by connecting to said bit line, the read circuit of the magnetic memory device according to any one of claims 1 to 4. The magnetoresistive element has a non-magnetic layer sandwiched between two ferromagnetic layers, records binary information according to the direction of magnetization in the ferromagnetic layer, and responds to the recorded information. in which electrical resistance varies Te, the read circuit of the magnetic memory device according to any one of claims 1 to 5. The read circuit of the magnetic memory device according to claim 6 , wherein the nonmagnetic layer is a tunnel insulating film. The read circuit of the magnetic memory device according to claim 6 or 7 each ferromagnetic layer is a perpendicular magnetization film.

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