JP2003123464A - Magnetic memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an overshoot occurring to a current flowing through write lines and bit lines at the time of writing data. SOLUTION: At the time of writing data, in the case of consecutively switching switch elements connected with write lines WWL1-WWL3, and in the case of consecutively switching the switch elements connected with bit lines BL1-BL3, each switch element is made to overlap for a period before and after it is switched ON. Further, any of the switch elements connected with write lines WWL1-WWL3 or the switch element connected with a dummy wiring WWL0 is made to be always turned on, and/or any of the switch elements connected with the bit lines BL1-BL3 or the switch element connected with a dummy wiring BL0 is made to be always turned on, and in the period before and after switching any switch element, each switch element is made to overlap for the period before and after the switch is switched ON.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile magnetic memory device, and more particularly to a magnetic memory device having a memory cell using a magnetoresistive element.

[0002]

2. Description of the Related Art In a magnetic material such as a ferromagnetic material, a magnetoresistive effect is known in which the electric resistance changes depending on the direction of magnetization and the presence or absence of magnetization. Resistance ratio (MR ratio; Magneto-Resistance)
Ratio). Giant Magneto-Resistance (GMR) materials and Colossal Magneto-Resista (CMR) materials are used as materials having a large magnetic resistance ratio.
nce) materials, which are generally metals, alloys, complex oxides, and the like. For example, Fe, Ni, Co, Gd,
Tb and these alloys, La _X Sr _1-X MnO ₉ , La _X
There are materials such as complex oxides such as Ca _1-X MnO ₉ . In general, a ferromagnetic substance has a characteristic that the magnetization generated in the ferromagnetic substance by an externally applied magnetic field remains even after the external magnetic field is removed (this is called remanent magnetization).

Therefore, if a ferromagnetic material is used as the magnetoresistive material and the residual magnetization of the ferromagnetic material is utilized, a non-volatile memory for storing information by selecting an electric resistance value depending on the magnetization direction and the presence / absence of magnetization is constructed. can do. Such a nonvolatile memory is a magnetic memory (MRAM: Magnetic Random Access Memory).
is called.

Most of the MRAMs that have been developed in recent years store information by the residual magnetization of a ferromagnetic material of a giant magnetoresistive material, and can detect a change in electric resistance value caused by a difference in magnetization direction. Therefore, a method of reading the stored information is adopted. Further, by changing the magnetization direction of the ferromagnetic memory cell by a magnetic field induced by applying a current to the write wiring, it is possible to write information in the memory cell and rewrite the information.

As a memory cell of an MRAM, a tunnel magnetoresistive element (TMR; Tunnel Magneto-) having a structure in which a tunnel insulating film (an electric insulating film having a thickness such that a tunnel current flows) is sandwiched between two ferromagnetic layers. Resistance, or MTJ (Magnetic Tunnel Junction), has a high rate of change in magnetoresistance (MR ratio), and is expected as a device that is most practical. As such a memory cell, one having a structure in which a tunnel insulating film is sandwiched between two in-plane magnetized films has been conventionally studied. However, in the case of a memory cell using an in-plane magnetized film, the MR ratio is reduced and the required write current is increased with the miniaturization of the memory cell, and the operating point (hysteresis indicating the magnetic characteristics of the memory cell is It is known that there are issues that need to be solved, such as movement of loops). On the other hand, in Japanese Unexamined Patent Application Publication No. 11-213650, 2
A structure has been proposed in which a non-magnetic layer that is a tunnel insulating film is sandwiched between a plurality of perpendicularly magnetized films. By using the perpendicular magnetization film, even if the memory cell is miniaturized, a decrease in MR ratio and an increase in write current can be suppressed, and a shift in a hysteresis loop can also be suppressed. You can get cells.

FIG. 9 is a circuit diagram showing an example of the configuration of the memory cell array of the MRAM.

One memory cell includes a magnetoresistive element (memory element) 11 represented as a variable resistance, and a transistor 12 having one end connected to the magnetoresistive element 11. The transistor 12 is typically a MOS (Metal-Ox).
ide-Semiconductor) field effect transistor, the other end is grounded. A plurality of such memory cells are two-dimensionally arranged in a matrix to form a memory cell array. Here, when the arrangement in the horizontal direction in the drawing is called a row and the arrangement in the vertical direction is called a column, the illustrated area shows a region of 3 rows × 3 columns in the memory cell array. Bit lines BL1 to BL3 extending in the row direction are provided for each row, and word lines WL1 to WL3 extending in the column direction are provided for each column. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line of the corresponding row, and the gate of the transistor 12 is connected to the word line of the corresponding column.

The broken lines shown in the figure indicate write lines WWL1 to WW for writing data to each memory cell.
L3, and the write line is provided for each column. T1 to T4 are transistors as switching elements,
A write circuit 13 is connected to the write lines WWL1 to WWL3 for each column. Write lines WWL1 to WWL
3 is folded back at the other end of the column and connected to the power supply circuit 14 via the transistors T1 and T4 or T2 and T3 that form the writing circuit 13. A writing current flows counterclockwise in the drawing when the transistors T1 and T4 are turned on, and a writing current flows clockwise in the drawing when the transistors T2 and T3 are turned on. Therefore, the write circuit 13 allows the current from the power supply circuit 14 to flow bidirectionally as a write current to the write line.

FIG. 10 is a sectional view showing an example of the structure of a memory cell. In the figure, two memory cells arranged in the column direction are shown.

An element isolation region 31 is formed on a semiconductor substrate 30, and a drain region 3 of the transistor 12 is formed.
2 and the source region 33 are provided, and in a region sandwiched between the drain region 32 and the source region 33, a word line 35 (word lines WL1 to WL3 in FIG. 9) which also serves as a gate electrode of the transistor 12 is provided via a gate insulating film 34.
Corresponding to) is formed. In the illustrated example, the two transistors 12 also serve as the source region 33, and the interlayer insulating films 36, 37 and 38 are provided in this order so as to cover such a transistor 12. The interlayer insulating film 38 is formed particularly thin. The source region 33 is connected to the ground line 40 formed on the interlayer insulating film 36 via the plug 39, and the drain region 32.
Is connected to the lower surface of the magnetoresistive element 11 formed on the interlayer insulating film 38 via the plug 41. In the illustrated example, the magnetoresistive element 11 is disclosed in JP-A-11-213650.
As described in Japanese Unexamined Patent Publication (Kokai), a tunnel insulating film which is a non-magnetic layer is sandwiched between two layers of perpendicularly magnetized films. A write line 42 (corresponding to the write lines WWL1 to WWL3 in FIG. 9) is formed below the interlayer insulating film 38 so as to be engraved in the interlayer insulating film 37. An interlayer insulating film 43 is formed so as to fill the region between the adjacent magnetoresistive elements 11, and the upper surface of the magnetoresistive element 11 is formed on the interlayer insulating film 43 and extends in the left-right direction in the drawing (see FIG. Bit lines BL1 to B in 9
It corresponds to L3). Further, the interlayer insulating film 43
An interlayer insulating film 45 that also serves as a protective film is formed so as to cover the bit line 44 and the bit line 44.

Writing of data to a memory cell in the memory cell array shown in FIG. 9 is performed by a write magnetic field by a write current flowing through a write line and an assist flowing through a bit line in a memory cell (selected memory cell) to be written with data. Data is written only in the selected memory cell by the sum magnetic field of the current and the assist magnetic field. For example, an assist current is passed through the bit line of the row to which the memory cell belongs to generate an assist magnetic field horizontal to the film surface of the magnetoresistive element, and then the write value ("Low (0)" or " H
write (1) ″) is passed to generate a write magnetic field perpendicular to the film surface of the magnetoresistive element, and the sum magnetic field of the write magnetic field and the assist magnetic field causes
Data is written only in the selected memory cell. The assist magnetic field is a magnetic field that acts to reduce the magnitude of the write magnetic field necessary for reversing the magnetization direction of the ferromagnetic layer, and the write magnetic field is the magnetic field that determines the magnetization direction of the ferromagnetic layer. As a method for writing to a memory cell, writing may be achieved by generating a write magnetic field after generating an assist magnetic field, or writing may be performed by first generating a write magnetic field and then generating an assist magnetic field. You may achieve it.

Further, in order to pass an assist current to the bit line of the selected row, the power supply circuit 1 is provided at one end of each bit line.
4 is provided with a transistor 15 as a switch element for connecting the bit line to the bit line 4, and the other end is provided with a transistor 16 as a switch element for grounding the bit line at the other end. Transistors 15 and 16
Are typically constituted by MOS field effect transistors.

In such a memory cell array, the read circuit 20 is provided at one end of each of the bit lines BL1 to BL3.
Is provided. The read circuit 20 uses the word line WL
The data written in the memory cell of the column selected by 1 to WL3 is read out. Specifically, all the transistors 15 and 16 are turned off, and the transistor 1 of a specific column is set by the word line.
2 is turned on, the resistance value of the magnetoresistive element 11 of the target memory cell is read from the read circuit 20 side, and whether "0" or "1" is recorded is determined based on the result. In this case, instead of measuring the absolute value of the resistance value of the magnetoresistive element 11, for example, a reference cell is provided in the read circuit 20, and the reference cell and the resistance of the magnetoresistive element 11 are compared to determine “0”. It is determined whether it is "" or "1". In the reference cell, a resistance value that is intermediate between the resistance value when the recorded value is “0” and the resistance value when the recorded value is “1” in the magnetoresistive element 11 is set. Then, a predetermined current is passed through both the reference cell and the magnetoresistive element 11, the voltage generated at both ends of the reference cell and the magnetoresistive element 11 at that time is detected, and the voltages of both are compared to obtain the reference cell. It is determined whether the resistance value of 1 is larger or the resistance value of the magnetoresistive element 11 is larger, and the data recorded in the magnetoresistive element 11 is determined.

[0014]

However, in the above-described conventional memory cell array, when all the switch elements connecting the write line and the bit line to the power supply circuit 14 are off, the destination of the current flow from the power supply circuit 14 is large. Is eliminated, the current is charged into the parasitic capacitance C10. In addition, the elements constituting the parasitic capacitance C10 referred to in this specification include the output capacitance of the power supply circuit to which the write line is connected, the wiring capacitance of the write line and the bit line, the parasitic capacitance of the switch element, and the like. What is the parasitic capacitance of the switch element?
If the switch element is, for example, a MOS transistor, it corresponds to the diffusion capacitance and the overlap capacitance with the gate terminal.

As a result, when a pulse current having an amplitude I as shown in FIG. 11 is applied to the write line and the bit line during data writing, the energy (charge) charged in the parasitic capacitance C10 at that moment is instantly discharged. Therefore, an overshoot occurs in the pulse current waveform immediately after that, which causes malfunctions and writing failures.

SUMMARY OF THE INVENTION An object of the present invention is to provide a magnetic memory device capable of suppressing an overshoot generated in a current flowing through a write line and a bit line when writing data.

[0017]

To achieve the above object, a magnetic memory device of the present invention comprises a magnetoresistive element,
A plurality of memory cells arranged in a matrix, a plurality of write lines connected to the memory cells, a plurality of bit lines arranged to intersect the plurality of write lines and connected to the memory cells, A first switch element group for supplying a current to the plurality of write lines, and a second switch group group for supplying a current to the plurality of bit lines. At the time of data writing, the first and second switch elements to which the corresponding write line and bit line are connected are turned on to cause a current to flow through the write line and the bit line, and the magnetic fields respectively induced by the current are generated. In the magnetic memory device applied to the magnetoresistive element, the first switch connected to the plurality of write lines is used when sequentially writing data to the plurality of magnetoresistive elements. In the case of sequentially switching the H element or the second switch element connected to the plurality of bit lines, the period before and after the switching in which the first or second switch element is turned on is overlapped. To do.

According to this structure, when data is sequentially written to the plurality of magnetoresistive elements, all of the first or second switch elements that supply a current to the write line or the bit line are turned off, and the parasitic capacitance is charged. Since charging is avoided, a current whose overshoot is suppressed can be passed through the write line or the bit line.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following description,
Although the ferromagnetic layer of the magnetoresistive element will be described as a vertically magnetized film, the present invention is not limited to this, and is applicable even if the ferromagnetic layer of the magnetoresistive element is a horizontally magnetized film. is there.

(First Embodiment) FIG. 1 is a diagram showing a configuration of a magnetic memory device according to an embodiment of the present invention. The magnetic memory device shown in FIG. 1 has the same basic configuration as that of the magnetic memory device of FIG. 9, and schematically shows a portion related to data writing.

In FIG. 1, M11 to M33 are magnetoresistive elements provided in each memory cell, 141 is a constant current source for write current, 142 is a constant current source for assist current, and C20 and C30 are parasitic capacitances ( (Parasitic capacitance due to the same factor as the parasitic capacitance C10 shown in FIG. 9), T1
T4 is a transistor as a switching element, and 13 is a first writing circuit having transistors T1 to T4.
Switch elements, φWWL11 to φWWWL32 are the first
The write lines WWL1 to WWL3 are controlled by controlling the respective transistors T1 to T4 in the group of switch elements 13 of
Switch element for supplying write current to φBL
1 to φBL3 are switch elements as second switch elements for supplying an assist current to the bit lines BL1 to BL3, and in the present embodiment, they are n-type MOS transistors. In this embodiment, the constant current source 141
And 142 are configured in the same power circuit 14,
Two or more power supply circuits may be provided, and the constant current sources 141 and 142 may be provided in different power supply circuits. The transistors T1, T2, T3, and T4 of this embodiment are n-type M
Although it is composed of an OS transistor, the transistor of the present invention is not limited to this, and for example, a transistor (T
1, T3) may be a p-type MOS transistor, and the transistors (T2, T4) may be an n-type MOS transistor. In that case, in FIG.
The φWWL11 for controlling T2 and T2 may not be an inverter circuit, but may have a circuit configuration in which the same input signal is input to both switches. Further, the transistors T1 to T4 and the switch element φBL1 are not limited to the transistors and may be switches having an ON / OFF switching function.

In the magnetic memory device of this embodiment, the transistor T1 is turned on and the transistor T2 is turned off by applying a high pulse to the switch element φWWL11. In addition, switch element φWWL12 is Low
Is applied to turn off the transistor T3, turn on the transistor T4, and the write line WWL.
A write current flows counterclockwise in FIG. Conversely, a low pulse is applied to the switch element φWWL11,
When a high pulse is applied to the switch element φWWL12, the transistors T2 and T3 are turned on and the transistors T1 and T4 are turned off. Therefore, the write line WWL
1, a write current flows clockwise in the drawing.

When the switch element φBL1 is turned on by a high pulse, an assist current flows in the bit line BL1 to the left in the drawing.

For example, at the time of writing data to the magnetoresistive element M11, while the switch element φBL1 is turned on and the assist current is flowing to the bit line BL1, the write current flows to the write line WWL1 in the direction corresponding to the write value. . Further, in the present specification, the operation in which the write current is made to flow bidirectionally is set as one set, but only the write current having the polarity corresponding to the write value (“0” or “1”) may be made to flow only in one direction.

The operation of writing data in the magnetic memory device shown in FIG. 1 will be described below with reference to the time chart of FIG. In the following, the magnetoresistive element M1
Write "High (1)" data to 1 and then
Description will be made assuming that the data of "Low (0)" is written in the magnetoresistive element M22. Note that FIG. 2 shows an operation example in which a write magnetic field is first generated and then an assist magnetic field is generated at the time of data writing to achieve writing.

First, since data is written in the magnetoresistive element M11, the switch elements φWWL11, φWWL12
By the above-mentioned operation, the write current is bidirectionally switched to the write line WWL1. Here, since the data of "High (1)" is written in the magnetoresistive element M11,
While the write current flows in the write line WWL1 clockwise in the drawing by the switch elements φWWL11 and the switch φWWL12, the switch element φBL1 is turned on and an assist current is passed to the bit line BL1 to generate a magnetic resistance by the magnetic field generated by each current. Write to element M11. Then, the operation of writing data in the magnetoresistive element M12 is started. Since the write current is always switched bidirectionally, the assist current is supplied while the write current having the polarity corresponding to the write value (“High (1)” or “Low (0)”) is flowing. Here, since the data of "Low (0)" is written in the magnetoresistive element M12,
A low pulse to the switch element φWWL22 causes φWW
While the write current is flowing counterclockwise in the write line WWL2 by applying a High pulse to L21, the switch element φBL1 is turned on to flow an assist current.

However, in the above-mentioned conventional operation, when the switching elements of the plurality of write lines are continuously switched at time t2, the power supply circuit 14 and the write line WWL are used.
Since there is a time in which all the switch elements connecting 1 to WWL3 are in the off state, the parasitic capacitance C20 illustrated in FIG. 1 is charged at that time, and due to the charge, FIG. As shown, an overshoot occurs in the waveform of the write current.

Therefore, in the present embodiment, in the magnetic memory device shown in FIG. 1, when the switch elements of the plurality of write lines are continuously switched to continuously write data to the plurality of magnetoresistive elements, the switch elements are switched. The power supply circuit 14 and the write lines WWL1 to WW are overlapped by overlapping the periods before and after the switching to turn on each.
It is supposed that all of the switch elements connecting L3 are turned off to prevent the parasitic capacitance C20 from being charged. As a result, the overshoot of the write current, which is a cause of malfunction or write failure at the time of writing, is suppressed.

Specifically, at the time of continuous switching from the switch element φWWL12 to the switch element φWWL21, the timing of applying a high pulse to the switch element φWWL12 is shifted after t2 to switch the switch element φWWL12.
By shifting the timing of applying the High pulse to WL21 before time t2, the periods before and after the switching in which the respective switch elements are turned on are overlapped.

As described above, when the switching elements of the plurality of write lines are continuously switched, the switching elements φWWL11 to φWWL3 are overlapped by overlapping the periods before and after the switching in which the switching elements are turned on.
Since all of 2 are turned off to prevent the parasitic capacitance C20 from being charged with electric charge, the overshoot generated in the write current at the time of writing can be suppressed as shown in FIG.

In the example shown in FIG. 2, the overlap period is provided by shifting both the periods in which the switch elements before and after switching the plurality of write lines are turned on, but only one of them is shifted. An overlap period may be provided. Further, in the present specification, the current flowing clockwise with respect to the write line is “High (1)”.
However, it is appropriately determined and is not limited to the configuration of the present specification. For example, the configuration may be such that "Low (0)" is written when a current flows clockwise in the drawing.

(Second Embodiment) In the above-described first embodiment, the operation at the time of data writing is such that when the first switch elements of a plurality of write lines are sequentially switched, the first switch elements are switched before and after the switching. The operation in which the write magnetic field is first generated and then the assist magnetic field is generated, including the operation for overlapping the period before and after the switching in which the switch element is turned on, has been described. In the present embodiment, the time chart of FIG. As shown in, when the second switch elements of a plurality of bit lines are sequentially switched, including the operation of overlapping the period before and after the switching in which the respective second switch elements are turned on before and after the switching, the assist magnetic field is generated. The operation when the write magnetic field is generated after the operation is performed will be described. According to the conventional operation, when the switching elements of the bit line are continuously switched at time t1, all the switching elements φBL1 to φBL3 for connecting the power supply circuit 14 and the bit line in FIG. Since the parasitic capacitance C30 shown in the drawing is charged with electric charges, the electric charges shown in FIG.
As shown in, overshoot occurs in the waveform of the assist current.

Therefore, in the present embodiment, when the switching elements of a plurality of bit lines are continuously switched in the magnetic memory device shown in FIG. 1, the switching elements are turned on and the periods before and after the switching are overlapped. This prevents all the switch elements φBL1 to φBL3 that connect the power supply circuit 14 and the bit line from being turned off to prevent the parasitic capacitance C30 from being charged. As a result, the overshoot of the assist current, which is a cause of malfunction or writing failure during writing, is suppressed.

Specifically, when switching from the switch element φBL1 to the switch element φBL2, the switch element φ
The timing to turn off BL1 is shifted after time t1,
The timing for turning on the switch element φBL2 is time t
By shifting the switch elements by 1 before, the periods before and after the switching in which the respective switch elements are turned on are overlapped. Note that FIG. 3 shows an operation example in the case of sequentially writing data of “High” and “Low” to the magnetoresistive elements M11 and M22, respectively.

As described above, when the switching elements of the bit line are continuously switched, by overlapping the periods before and after the switching in which the switching elements are turned on, all the switching elements φBL1 to φBL3 are turned off and parasitic. Since the capacitor C30 is prevented from being charged with electric charges, the overshoot generated in the assist current at the time of writing can be suppressed as shown in FIG.

In the example shown in FIG. 3, the overlap period is provided by shifting both the periods in which the switching elements before and after switching are turned on, but by shifting only one of them. May be.

(Third Embodiment) FIG. 4 is a diagram showing the configuration of a magnetic memory device according to another embodiment of the present invention.

The magnetic memory device shown in FIG. 4 is different from the magnetic memory device shown in FIG. 1 in that the first dummy wiring connected to the constant current source 141 via the switch element φWWL0 as the third switch element. Dummy wiring WWL0 as
And a switch element φBL0 as a fourth switch element
The configuration is the same except for the point that a dummy wiring BL0 as a second dummy wiring connected to the constant current source 142 via is provided. The dummy wiring WWL0 and the dummy wiring BL0 are the dummy wiring WWL0 and the dummy wiring BL in an area other than the area where the memory cells are arranged.
The magnetoresistive element is arranged in a region that is not affected by the current flowing through 0. The dummy wire WWL0 is turned on when a high pulse is applied to the switch element φWWL0 (n-type MOS transistor), and a current flows in one direction downward in the figure.

In the above-described first and second embodiments, all the switch elements that connect the power supply circuit 14 and the write line are turned off when the switch elements of the plurality of write lines are continuously switched. However, in reality, all switch elements that connect the power supply circuit 14 and the write line are in the OFF state while the data write operation is not performed, and during that period, a plurality of write lines are connected. It is much longer than when switching the switching elements continuously. Therefore, in order to further suppress the overshoot, not only is it possible to prevent the parasitic capacitance from being charged with electric charges when the switching elements of the plurality of write lines are continuously switched, but also during the data write operation is not performed. Also, it is desirable that the parasitic capacitance is not charged.

Therefore, in this embodiment, as shown in the time chart of FIG. 5, the write line and the power supply circuit 14 are connected.
When all the switch elements (transistors T1 and T3 in this embodiment) that connect to and are turned off, the switch φWWL0 connected to the dummy wiring WWL0 is turned on to discharge and sweep out the electric charge of the parasitic capacitance C20. It is intended to prevent the parasitic capacitance C20 from being charged. Further, when all the switch elements φBL1 to φBL3 connecting the bit line and the power supply circuit 14 are turned off, the switch element φBL0 connected to the dummy wiring BL0 is turned on to discharge and sweep out the electric charge of the parasitic capacitance C30. The charging of the parasitic capacitance C30 is avoided. In addition, FIG.
As in the case of FIG. 2, the data write operation includes the continuous switching operation of the switch elements of the write line, and the operation of generating the write magnetic field first and then the assist magnetic field is performed. , M22, the operation example in the case of sequentially writing the data of "High" and "Low", respectively.

More specifically, regarding the operation of avoiding the charging of the parasitic capacitance C20 with electric charges, when all the switch elements connecting the write line and the power supply circuit 14 are all in the off state, the dummy wiring WWL0 is The connected switch φWWL0 is turned on. However, in this state, when the switch element φWWL0 is continuously switched to the switch element φWWL11 at time t0, and at time t8.
Switch element φWWL22 to switch element φWWL0
When switching continuously to the
There is a time when all of the φWWL 32 are turned off.

Therefore, when the switch element φWWL0 is continuously switched to the switch element φWWL11, the switch element φWWL0 is turned off at time t.
By shifting after 0, the timing of turning on the switch element φWWL11 is shifted before time t1, thereby overlapping the periods before and after the switching in which the respective switch elements are turned on. Similarly, the switch element φWWL2
Even during continuous switching from 2 to the switch element φWWL0, the periods before and after the switch in which each switch element is turned on are overlapped. The operation of providing the overlap period during continuous switching of the switch elements φWWL11 to φWWL22 is the same as in FIG.

As a result, when the data writing is started from the period in which the data writing is not performed, not all the switch elements connecting the power supply circuit 14 and the write line are turned off, so that the parasitic capacitance C20 is charged. Since this is avoided, the overshoot that occurs in the write current at the time of writing can be suppressed as shown in FIG.

In the embodiment of FIG. 5, the switch φWWL0 is turned on so that the parasitic capacitance C20 is not charged with electric charges during the period in which data is not written, and the current always flows to the ground. It is also possible to suppress the overshoot by turning off φWWL0 and turning it on with the overlap period provided immediately before to discharge the charge stored in the parasitic capacitance C20. As a result, lower power consumption can be realized as compared with the case where a current is constantly supplied to the ground.

On the other hand, regarding the operation of avoiding the charging of the parasitic capacitance C30, when the switch elements connecting the bit line and the power supply circuit 14 are all in the off state, the switch φBL0 connected to the dummy wiring BL0 is turned on. It is turned on. However, in this state, when the switch element φBL0 is continuously switched to the switch element φBL1 at time t2, when the switch element φBL1 is continuously switched to the switch element φBL0 at time t3, the switch element φBL0 is switched to the switch element φBL2 at time t5. There is a time in which all of the switch elements φBL0 to φBL3 are turned off when continuously switching and when switching the switch element φBL2 to the switch element φBL0 at time t6.

Therefore, when the switching element φBL0 is continuously switched to the switching element φBL1, the timing for turning off the switching element φBL0 is shifted after time t2, and the timing for turning on the switching element φBL1 is shifted before time t2. , And the period before and after the switching in which each of the switch elements is turned on is overlapped. Similarly, when the switch element φBL1 is continuously switched to the switch element φBL0, the switch element φB
Even during continuous switching from L0 to the switching element φBL2 and during continuous switching from the switching element φBL2 to the switching element φBL0, the periods before and after the switching in which the switching elements are turned on are overlapped.

As a result, the switch elements φBL0 to φB
One of L3 is always on, and the parasitic capacitance C30
Since the electric charge is prevented from being charged, the overshoot generated in the assist current at the time of writing can be suppressed as shown in FIG.

In the example shown in FIG. 5, both the periods in which the switching elements before and after the switching are turned on are shifted to provide the overlap period, but only one of them is shifted to provide the overlap period. Is also good.

Although the parasitic capacitances of both the write line and the bit line are prevented from being charged with electric charges, the parasitic capacitances of either the write line or the bit line are prevented from being charged with electric charges. It may be configured to.

Further, the embodiment shown in FIG. 6 will be described. 6 is different from the other embodiments in that when the current is switched bidirectionally in the same write line, for example, at time t1, the switch element φWWL0 of the first dummy wiring has an overlap period before and after time t1. The point is that it is provided and turned on. Furthermore, time t7
The same is true for.

As a result, when a bidirectional current is passed through the same write line, it is possible to prevent all the switch elements that connect the power supply circuit 14 and the write line, which were present at the moment of switching the current, from turning off. The overshoot generated in the write current at the time of writing can be suppressed as shown in FIG. Although not shown, the switching elements φWWL11 and φW are used at the time of switching the current.
When the overlap period is provided in WL12, the transistors T1 and T3 are both turned on and have the same potential, so that no current flows through the write line and the parasitic capacitance C2.
It is conceivable that the electric charge is charged to 0, but even in that case, by switching the switch element φWWL0 of the first dummy wiring before and after the switching as in the embodiment of FIG. By supplying, it is possible to avoid charging the parasitic capacitance C20 with electric charges.

In the above operation, instead of the dummy wiring WWL0 through which the current flows only in one direction as shown in FIG. 4, the dummy wiring WWL which can be switched in both directions to allow the current to flow therethrough.
It can also be performed by the magnetic memory device shown in FIG. The dummy wiring WWL0 in FIG. 7 is connected to the power supply circuit 14 through the write circuit 13 similar to the other write lines, and when a high pulse is applied to the switch element φWWL01 and a low pulse is applied to the switch element φWWL02, the transistor T1, T4 is turned on, a low pulse is applied to the switch element φWWL01, and the switch element φWW
By applying a high pulse to L02, the transistors T2 and T3 are turned on, and the electric charge stored in the parasitic capacitance C20 can be discharged.

When the above operation is performed in the magnetic memory device shown in FIG. 7, when all the switch elements connecting the power supply circuit 14 and the write line are in the off state, either of the switch elements φWWL01 or φWWL02 is Hi.
It is only necessary to apply a gh pulse to turn it on, and to overlap the periods before and after switching in which the respective switch elements are turned on, and the other operations are similar to the above.

Further, in the magnetic memory device shown in FIG. 7, the basic operation is the same as that described above when the operation including the continuous switching operation of the switch elements of the bit lines is performed as shown in FIG. Is. That is, when all the switch elements connecting the power supply circuit 14 and the write line are in the off state, a high pulse is applied to the switch element φWWL0 connected to the dummy wiring WWL0 to turn it on,
When all the switch elements that connect the power supply circuit 14 and the bit line are in the off state, a high pulse is applied to the switch element φBL0 connected to the dummy wiring BL0 to turn it on, and each switch element is turned on. It suffices to make the periods of overlap overlap, and the operation of providing the overlap period at the time of continuous switching of the switch elements φBL1 to φBL3 is similar to that of FIG.

In the configuration described above, the number of write lines is 1.
One constant current source is connected via each switch element, and the current is bidirectionally supplied to the write line by each switch. However, as shown in FIG. A configuration may be used in which a current is passed through. Figure 8
Shows a configuration in which four constant current sources 151 to 154 cause a current to flow bidirectionally in each of the write lines WWL1 to WWL3. When a current flows in the write lines WWL1 to WWL3 counterclockwise in the drawing, a constant current is applied. When the currents are made to flow by the sources 151 and 154 and the write lines WWL1 to WWL3 are made to flow clockwise in the drawing, the currents are made to flow by the constant current sources 152 and 153. The constant current sources 151 and 152 and the constant current sources 153 and 154 may be provided in the same power supply circuit, or two or more power supply circuits may be provided and may be provided in different power supply circuits. .

Further, although the configuration described above is a configuration in which a folding current is passed through each write line bidirectionally, the present invention is also applied to a configuration in which a current is passed through each write line only in one direction. It is possible.

[0057]

As described above, according to the present invention, when data is written to the magnetoresistive element, the switch elements connected to a plurality of write lines are continuously switched, or the switch elements connected to a plurality of bit lines are switched. When switching the elements continuously, by overlapping the period before and after the switching in which each of the switching elements is turned on, the switching element of the plurality of write lines and / or the plurality of bit lines can be connected to the power supply circuit when continuously switching. Write line and /
Alternatively, since it is avoided that all the switching elements that connect the power supply circuit and the bit line are turned off and the parasitic capacitance is charged with electric charge, a current whose overshoot is suppressed is supplied to the write line and the bit line. There is an effect that can be.

Further, any one of the switch element for connecting the plurality of write lines and the power supply circuit or the switch element for connecting the first dummy wiring and the power supply circuit is always turned on and / or a plurality of switch elements. It is assumed that any one of the switch elements for connecting the bit line and the power supply circuit or the switch element for connecting the second dummy wiring and the power supply circuit is always turned on, and the switch element before and after the switching of the switch elements. By overlapping the periods before and after the switching, in which each switch is turned on, the switching element for connecting the power supply circuit and the write line and / or the power supply circuit and the bit line is connected during the period other than the continuous switching of the switching device. Since all of them are turned off to avoid charging the parasitic capacitance, There is an effect that it is possible to flow a current overshoot is suppressed to the bit line.

Further, also in the configuration in which the current is switched to flow bidirectionally in the same write line, by providing the overlap period of the present invention and turning on the switch element of the first dummy wiring, the destination of the current flow. By supplying the charge, it is possible to prevent the parasitic capacitance from being charged with electric charge, so that there is an effect that a current whose overshoot is suppressed can flow in the write line.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a magnetic memory device according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining one operation example at the time of writing in the magnetic memory device shown in FIG.

FIG. 3 is a time chart for explaining another operation example at the time of writing in the magnetic memory device shown in FIG.

FIG. 4 is a diagram showing a configuration of a magnetic memory device according to another embodiment of the present invention.

FIG. 5 is a time chart for explaining one operation example at the time of writing in the magnetic memory device shown in FIG.

6 is a time chart for explaining another operation example at the time of writing in the magnetic memory device shown in FIG.

FIG. 7 is a diagram showing a configuration of a magnetic memory device according to still another embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a magnetic memory device according to still another embodiment of the present invention.

FIG. 9 is a circuit diagram showing an example of a configuration of a memory cell array of MRAM.

FIG. 10 is a cross-sectional view showing an example of the configuration of a memory cell.

FIG. 11 is a diagram showing an example of a pulse current waveform at the time of writing in the conventional magnetic memory device.

FIG. 12 is a diagram showing an example of a pulse current waveform at the time of writing in the magnetic memory device of the present invention.

[Explanation of symbols]

M11 to M33 magnetoresistive elements 141, 142, 151 to 154 constant current sources WWL1 to WWL3 write lines BL1 to BL3 bit lines φWWL11 to φWWWL32 switch elements φBL1 to φBL3 switch elements T1 to T4 transistors C20 and C30 parasitic capacitance WWL0 dummy wiring φWWL0, φWWL01, φWWWL02 Switch element BL0 Dummy wiring φBL0 switch element

Claims (12)

[Claims] 1. A plurality of memory cells provided with a magnetoresistive element and arranged in a matrix, a plurality of write lines connected to the memory cells, and a plurality of write lines arranged to intersect the plurality of write lines. A plurality of bit lines connected to the memory cells; a group of first switch elements for supplying a current to the plurality of write lines; and a second switch for supplying a current to the plurality of bit lines. And writing the data to the magnetoresistive element, turning on the first and second switch elements to which the corresponding write line and bit line are connected, respectively, and turning on the write line and the bit line. In a magnetic memory device that applies a magnetic field respectively induced by the current to the magnetoresistive element, when writing data sequentially to the plurality of magnetoresistive elements,
The first switch element connected to the plurality of write lines or the second switch element connected to the plurality of bit lines
2. When the switching elements are sequentially switched, the magnetic memory device is characterized in that the periods before and after the switching in which the first or second switching elements are turned on are overlapped. 2. When writing the data to the plurality of magnetoresistive elements, when sequentially switching the second switch elements connected to the plurality of bit lines, the second switch elements are turned on before and after the switching. 2. The magnetic memory device according to claim 1, wherein the periods are overlapped. 3. The magnetic memory device according to claim 1, wherein the plurality of write lines and the plurality of bit lines are connected to a constant current source. 4. A third switch element connected to a power supply circuit for supplying a current to the write line via the first switch element, and a first dummy wiring connected to the third switch element. And sequentially switching between the first switch element connected to the write line and the third switch element connected to the first dummy wiring, each of the first and third switch elements 4. The magnetic memory device according to claim 1, wherein the periods before and after the switching to turn on are overlapped. 5. The first switch element or the third switch element.
5. The magnetic memory device according to claim 4, wherein at least one of the switching elements of 1. is always turned on. 6. A fourth switch element connected to a power supply circuit for supplying a current to the bit line via the second switch element, and a second dummy wiring connected to the fourth switch element. And sequentially switching between the second switch element connected to the bit line and the third switch element connected to the second dummy wiring, each of the second and third switch elements 6. The magnetic memory device according to claim 1, wherein the periods before and after the switching to turn on are overlapped. 7. The second switch element or the fourth switch element.
7. The magnetic memory device according to claim 6, wherein at least one of the switch elements of 1. is always turned on. 8. When the first switch element is bidirectionally switched in the write line to flow a current, the period before and after the switching of the first switch element and the first dummy wiring are connected. 7. The magnetic memory device according to claim 4, wherein a period in which the switch element of 3 is turned on is overlapped. 9. The magnetic memory device according to claim 6, wherein the power supply circuits that supply current to the write line and the bit line are the same power supply circuit. 10. The write line is configured by connecting one ends of wirings arranged so as to sandwich the element row of the magnetoresistive element to each other, and the write line is connected to a plurality of constant current sources. 10. The magnetic memory device according to claim 1, wherein a current flows bidirectionally through the write line by the constant current source. 11. The write line is configured by connecting one ends of wirings arranged so as to sandwich the element row of the magnetoresistive element to each other, and connecting the write line to one constant current source, 10. The line is provided with a plurality of switch elements, and by switching the plurality of switch elements, a current flows in the write line bidirectionally. The magnetic memory device according to 1. 12. When writing data to the magnetoresistive element, a plurality of the first first lines connected to a corresponding write line.
Of the second switch connected to the corresponding bit line while the current is flowing in the write line in the direction corresponding to the write value by sequentially switching the switch elements of 12. The magnetic memory device according to claim 11, wherein an element is switched to flow a current through the bit line.