JP2003132670A - Magnetic memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress overshoot caused in a current flowing write-in lines and bit lines at write-in of data. SOLUTION: Switch elements ϕ 100 are provided at preceding stages of write-in lines WWL1-WWL3, and each write-in line WWL1-WWL3 is connected to a power source circuit 14 through the switch elements ϕ 100. In the same way, switch elements ϕ 200 are provided at preceding stages of bit lines BL1-BL3, and each write-in line BL1-BL3 is connected to a power source circuit 14 through the switch elements ϕ 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile magnetic memory device, and more particularly to a magnetic memory device having a memory cell using a magnetoresistive element.

[0002]

2. Description of the Related Art In a magnetic material such as a ferromagnetic material, a magnetoresistive effect is known in which the electric resistance changes depending on the direction of magnetization and the presence or absence of magnetization. Resistance ratio (MR ratio; Magneto-Resistance)
Ratio). Giant Magneto-Resistance (GMR) materials and Colossal Magneto-Resista (CMR) materials are used as materials having a large magnetic resistance ratio.
nce) materials, which are generally metals, alloys, complex oxides, and the like. For example, Fe, Ni, Co, Gd,
Tb and these alloys, La _X Sr _1-X MnO ₉ , La _X
There are materials such as complex oxides such as Ca _1-X MnO ₉ . In general, a ferromagnetic substance has a characteristic that the magnetization generated in the ferromagnetic substance by an externally applied magnetic field remains even after the external magnetic field is removed (this is called remanent magnetization).

Therefore, if a ferromagnetic material is used as the magnetoresistive material and the residual magnetization of the ferromagnetic material is utilized, a non-volatile memory for storing information by selecting an electric resistance value depending on the magnetization direction and the presence / absence of magnetization is constructed. can do. Such a nonvolatile memory is a magnetic memory (MRAM: Magnetic Random Access Memory).
It is called.

Most of the MRAMs that have been developed in recent years store information by the residual magnetization of a ferromagnetic material of a giant magnetoresistive material, and can detect a change in electric resistance value caused by a difference in magnetization direction. Therefore, a method of reading the stored information is adopted. Further, by changing the magnetization direction of the ferromagnetic memory cell by a magnetic field induced by applying a current to the write wiring, it is possible to write information in the memory cell and rewrite the information.

As a memory cell of an MRAM, a tunnel magnetoresistive element (TMR; Tunnel Magneto-) having a structure in which a tunnel insulating film (an electric insulating film having a thickness such that a tunnel current flows) is sandwiched between two ferromagnetic layers. Resistance, or MTJ (Magnetic Tunnel Junction), has a high rate of change in magnetoresistance (MR ratio), and is expected as a device that is most practical. As such a memory cell, one having a structure in which a tunnel insulating film is sandwiched between two in-plane magnetized films has been conventionally studied. However, in the case of a memory cell using an in-plane magnetized film, the MR ratio is reduced and the required write current is increased with the miniaturization of the memory cell, and the operating point (hysteresis indicating the magnetic characteristics of the memory cell is It is known that there are issues that need to be solved, such as movement of loops). On the other hand, in Japanese Unexamined Patent Application Publication No. 11-213650, 2
A structure has been proposed in which a non-magnetic layer that is a tunnel insulating film is sandwiched between a plurality of perpendicularly magnetized films. By using the perpendicular magnetization film, even if the memory cell is miniaturized, a decrease in MR ratio and an increase in write current can be suppressed, and a shift in a hysteresis loop can also be suppressed. You can get cells.

FIG. 6 is a circuit diagram showing an example of the configuration of the memory cell array of the MRAM.

One memory cell includes a magnetoresistive element (memory element) 11 represented as a variable resistance, and a transistor 12 having one end connected to the magnetoresistive element 11. The transistor 12 is typically a MOS (Metal-Ox).
ide-Semiconductor) field effect transistor, the other end is grounded. A plurality of such memory cells are two-dimensionally arranged in a matrix to form a memory cell array. Here, when the arrangement in the horizontal direction in the drawing is called a row and the arrangement in the vertical direction is called a column, the illustrated area shows a region of 3 rows × 3 columns in the memory cell array. Bit lines BL1 to BL3 extending in the row direction are provided for each row, and word lines WL1 to WL3 extending in the column direction are provided for each column. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line of the corresponding row, and the gate of the transistor 12 is connected to the word line of the corresponding column.

The broken lines shown in the figure indicate write lines WWL1 to WW for writing data to each memory cell.
L3, and the write line is provided for each column. T1 to T4 are transistors as switching elements,
A write circuit 13 is a first switch element that supplies a current to the write lines WWL1 to WWL3 for each column. The write lines WWL1 to WWL3 are folded back at the other end of the column to form transistors W1 to WWL3 that form the write circuit 13.
4 or T2, T3 and is connected to the power supply circuit 14. When the transistors T1 and T4 are turned on, the write current flows counterclockwise in the figure, and the transistor T1
When 2 and T3 are turned on, the write current flows clockwise in the drawing. Therefore, the switch element of the write circuit 13 allows a current from the power supply circuit 14 to flow bidirectionally as a write current to the write line.

FIG. 7 is a sectional view showing an example of the structure of a memory cell. In the figure, two memory cells arranged in the column direction are shown.

An element isolation region 31 is formed on a semiconductor substrate 30, and a drain region 3 of the transistor 12 is formed.
2 and the source region 33 are provided, and in a region sandwiched between the drain region 32 and the source region 33, the word line 35 (the word lines WL1 to WL3 in FIG. 6) also serving as the gate electrode of the transistor 12 is provided via the gate insulating film 34.
Corresponding to) is formed. In the illustrated example, the two transistors 12 also serve as the source region 33, and the interlayer insulating films 36, 37 and 38 are provided in this order so as to cover such a transistor 12. The interlayer insulating film 38 is formed particularly thin. The source region 33 is connected to the ground line 40 formed on the interlayer insulating film 36 via the plug 39, and the drain region 32.
Is connected to the lower surface of the magnetoresistive element 11 formed on the interlayer insulating film 38 via the plug 41. In the illustrated example, the magnetoresistive element 11 is disclosed in JP-A-11-213650.
As described in Japanese Unexamined Patent Publication (Kokai), a tunnel insulating film which is a non-magnetic layer is sandwiched between two layers of perpendicularly magnetized films. A write line 42 (corresponding to the write lines WWL1 to WWL3 in FIG. 6) is formed below the interlayer insulating film 38 so as to be engraved in the interlayer insulating film 37. An interlayer insulating film 43 is formed so as to fill the region between the adjacent magnetoresistive elements 11, and the upper surface of the magnetoresistive element 11 is formed on the interlayer insulating film 43 and extends in the left-right direction in the drawing (see FIG. Bit lines BL1 to B in 6
It corresponds to L3). Further, the interlayer insulating film 43
An interlayer insulating film 45 that also serves as a protective film is formed so as to cover the bit line 44 and the bit line 44.

Writing of data to a memory cell in the memory cell array shown in FIG. 6 is performed by a write magnetic field due to a write current flowing through a write line and an assist flowing through a bit line in a memory cell (selected memory cell) to which data is to be written. Data is written only in the selected memory cell by the sum magnetic field of the current and the assist magnetic field. For example, an assist current is passed through the bit line of the row to which the memory cell belongs to generate an assist magnetic field horizontal to the film surface of the magnetoresistive element, and then the write value ("Low (0)" or " H
write (1) ″) is passed to generate a write magnetic field perpendicular to the film surface of the magnetoresistive element, and the sum magnetic field of the write magnetic field and the assist magnetic field causes
Data is written only in the selected memory cell. The assist magnetic field is a magnetic field that acts to reduce the magnitude of the write magnetic field necessary for reversing the magnetization direction of the ferromagnetic layer, and the write magnetic field is the magnetic field that determines the magnetization direction of the ferromagnetic layer. As a method for writing to a memory cell, writing may be achieved by generating a write magnetic field after generating an assist magnetic field, or writing may be performed by first generating a write magnetic field and then generating an assist magnetic field. You may achieve it.

Further, in order to pass an assist current to the bit line of the selected row, the power supply circuit 1 is provided at one end of each bit line.
4 is provided with a transistor 15 as a switch element for connecting the bit line to the bit line 4, and the other end is provided with a transistor 16 as a switch element for grounding the bit line at the other end. Transistors 15 and 16
Are typically constituted by MOS field effect transistors.

In such a memory cell array, the read circuit 20 is provided at one end of each of the bit lines BL1 to BL3.
Is provided. The read circuit 20 uses the word line WL
The data written in the memory cell of the column selected by 1 to WL3 is read out. Specifically, all the transistors 15 and 16 are turned off, and the transistor 1 of a specific column is set by the word line.
2 is turned on, the resistance value of the magnetoresistive element 11 of the target memory cell is read from the read circuit 20 side, and whether "0" or "1" is recorded is determined based on the result. In this case, instead of measuring the absolute value of the resistance value of the magnetoresistive element 11, for example, a reference cell is provided in the read circuit 20, and the reference cell and the resistance of the magnetoresistive element 11 are compared to determine “0”. It is determined whether it is "" or "1". In the reference cell, a resistance value that is intermediate between the resistance value when the recorded value is “0” and the resistance value when the recorded value is “1” in the magnetoresistive element 11 is set. Then, a predetermined current is passed through both the reference cell and the magnetoresistive element 11, the voltage generated at both ends of the reference cell and the magnetoresistive element 11 at that time is detected, and the voltages of both are compared to obtain the reference cell. It is determined whether the resistance value of 1 is larger or the resistance value of the magnetoresistive element 11 is larger, and the data recorded in the magnetoresistive element 11 is determined.

FIG. 8 is a diagram for explaining in detail the structure of a portion related to data writing in the memory cell array of the MRAM.

In FIG. 8, M11 to M33 are magnetoresistive elements provided in each memory cell, 141 is a constant current source for write current, 142 is a constant current source for assist current, and φWWL11 to φWWWL32 are switches T1 to T1. T
4 is a switch element for supplying a write current to the write lines WWL1 to WWL3, and φBL1 to φBL3 are switch elements for supplying an assist current to the bit lines BL1 to BL3, and are composed of n-type MOS transistors here. is doing. In addition, two or more power supply circuits 14 are provided,
The constant current sources 141 and 142 may be provided in different power supply circuits. Here, the transistors T1 and T
Although 2, T3 and T4 are composed of n-type MOS transistors, for example, the transistors (T1, T3) are p-type M transistors.
OS transistors, which are transistors (T2, T
4) may be an n-type MOS transistor. In that case, in FIG. 8, φWWL11 for controlling the transistors T1 and T2 may not be an inverter circuit, but may have a circuit configuration in which the same input signal is input to both switches.

In the memory cell array shown in FIG. 8, when a high pulse is applied to the switch element φWWL11, the transistor T1 is turned on and the transistor T2 is turned on.
Turns off. Further, the switching element φWWL12 is Lo
By applying the pulse of w, the transistor T3 is turned off, the transistor T4 is turned on, and the write line WW
A write current flows through L1 counterclockwise in the drawing. vice versa,
When a low pulse is applied to the switch element φWWL11 and a high pulse is applied to the switch element φWWL12, the transistors T2 and T3 are turned on and the transistors T1 and T4 are turned off. Therefore, the write line W
A write current flows through WL1 clockwise in the drawing.

When the switch element φBL1 is turned on by a high pulse, an assist current flows in the bit line BL1 to the left in the drawing.

For example, at the time of writing data to the magnetoresistive element M11, while the switch element φBL1 is turned on and the assist current is flowing to the bit line BL1, the write current flows to the write line WWL1 in the direction corresponding to the write value. . Further, at the time of data writing, the operation of passing the write current in the write line bidirectionally may be performed as one set, and only the write current of the polarity corresponding to the write value (“0” or “1”) is passed in only one direction. May be.

[0019]

However, in the above-mentioned conventional memory cell array, all the switch elements for connecting the write line and the power supply circuit 14 are in the off state,
Alternatively, when all the switch elements that connect the bit line and the power supply circuit 14 are off, the current from the power supply circuit 14 does not flow to the parasitic capacitance C1.
It is charged to 0 or C20. The elements constituting the parasitic capacitances C10 and C20 referred to in this specification include the output capacitance of the power supply circuit to which the write line and the bit line are connected, the wiring capacitance of the write line and the bit line, and the parasitic of the switch element. Capacity etc.

As a result, when a pulse current having an amplitude I as shown in FIG. 9 is passed through the write line and the bit line at the time of writing data, the energy (charge) charged in the parasitic capacitances C10 and C20 is instantly generated at that moment. Since it is discharged, an overshoot occurs in the pulse current waveform immediately after that, which causes malfunctions and writing failures.

Here, the parasitic capacitance of the switch element means, for example, if the switch element is a MOS transistor, the overlap capacitance between S (source) and G (gate) and the diffusion capacitance of S as shown in FIG. Corresponds to. In the memory cell array of the MRAM, data cannot be written unless a write current and an assist current above a predetermined threshold value are supplied. Therefore, it is necessary to remarkably increase the current driving capability of the switch element as compared with a DRAM using a normal capacitor cell. Therefore, the parasitic capacitance of the switch element becomes larger than the above-mentioned wiring capacitance and the like.

For example, in FIG. 8, the transistor T
Assuming that T1 and T3 are in the off state (cutoff state), S-
The overlap capacitance between G and the diffusion capacitance of S are parasitic capacitance components of the transistors T1 and T3 viewed from the power supply circuit 14. Since these capacitance components are connected in parallel to the power supply circuit 14 by the number of write lines, the parasitic capacitance of the switch element becomes more dominant among the elements constituting the parasitic capacitance C10.

Therefore, an object of the present invention is to provide a magnetic memory device capable of suppressing an overshoot generated in a current flowing through a write line and a bit line at the time of writing data by reducing the parasitic capacitance of the entire switch element. To do.

[0024]

To achieve the above object, a magnetic memory device of the present invention comprises a magnetoresistive element,
A plurality of memory cells arranged in a matrix, a current source for supplying a current, a plurality of wirings for applying a magnetic field to the memory cells, and a switch element for supplying a current from the current source for each of the plurality of wirings And a magnetic memory device having a switch element for disconnecting the current source from the plurality of switch elements.

According to this structure, even if all the switch elements provided for supplying the current to the plurality of wirings and the switch element for disconnecting the plurality of switch elements are turned off, the current flows through the plurality of switch elements. Does not flow into
As a result, electric charges are charged only in the parasitic capacitance of the switch element for disconnection. As a result, the parasitic capacitance on the wiring side as viewed from the current source is greatly reduced by the amount of the plurality of switch elements, so that a current with overshoot suppressed can flow through the write line during data writing.

Further, the magnetic memory device of the present invention comprises a plurality of memory cells which are provided with a magnetoresistive element and are arranged in a matrix, a plurality of write lines for applying a magnetic field to the memory cells, and a plurality of the write operations. A first switch element provided for each line for supplying a current to a corresponding write line; a plurality of bit lines arranged to intersect the plurality of write lines and connected to the memory cells; In a magnetic memory device having a second switch element provided for each of a plurality of bit lines and supplying a current to a corresponding bit line, one for disconnecting a power supply circuit from a plurality of the first switch elements It is characterized by having the above-mentioned third switch element and / or having a fourth switch element for separating the power supply circuit from the plurality of second switch elements.

According to this structure, even if all of the first switch element and the third switch element that supply current to the plurality of write lines are turned off, the current does not flow into the first switch element and the third switch element does not flow into the third switch element. The electric charge will be charged only to the parasitic capacitance of the switching element. As a result, the parasitic capacitance of the switch element on the write line side as seen from the power supply circuit is greatly reduced, so that a current whose overshoot is suppressed can flow through the write line during data writing. The same can be said for the bit line, and since the parasitic capacitance of the switch element on the bit line side as seen from the power supply circuit is greatly reduced, a current with overshoot suppressed can flow through the bit line during data writing.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a portion related to data writing of a magnetic memory device according to an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted.

Referring to FIG. 1, in the magnetic memory device of the present embodiment, a write circuit 13 as a plurality of switch elements for supplying a current to the write lines WWL1 to WWL3 or a first switch element for each column, each write. Transistors T1 to T4 as a plurality of fifth switch elements that form the circuit 13, switch elements φ100 as a switch element for disconnecting the plurality of first switch elements and the power supply circuit 14 or as a third switch element The write lines WWL1 to WWL3 are arranged from the transistors T1 to T4 in each write circuit 13 to the switch element φ1.
00 to the constant current source 141 in the power supply circuit 14. Also, as a switch element for supplying a current to the bit lines BL1 to BL3, or as a second switch element, a switch element φBL1 to φBL3, a switch element for disconnecting the plurality of switch elements φBL1 to BL3 from the power supply circuit 14, or The switch element φ200 as the switch element of No. 4 is arranged, and the bit lines BL1 to BL3
Are connected to the constant current source 142 in the power supply circuit 14 from the switch elements φBL1 to φBL3 via the switch element φ200.

Although FIG. 1 shows only a region of 3 rows × 3 columns in the memory cell array of the magnetic memory device, the overall configuration is as shown in FIG. 2, for example. However, the magnetic memory device of the present embodiment is not necessarily limited to the configuration shown in FIG. 2, and regarding the switch elements φ100-1 to φ100-N, two or more switch elements φ100-1 to φ100-N are provided. Each write line is connected to a write line, and each write line is a switching element φ100-1
It is sufficient if the configuration is such that it is connected to the power supply circuit 14 via any one of ˜φ100-N. Also, switch element φ
For 200-1 to φ200-M, the switching element φ
200-1 to φ200-M are connected to two or more bit lines, and each bit line has switching elements φ200-1 to φ20.
Any configuration may be used as long as it is connected to the power supply circuit 14 via any of 0-M.

Switch element φ10 in the present embodiment
0 and φ200 are composed of n-type MOS transistors having an S-G overlap capacitance and an S diffusion capacitance as shown in FIG. However, the switch elements φ100 and φ200 of the present invention are not limited to this, and may be p-type MOS transistors.

For example, when all the switch elements (switch element φ100 and transistors T1 and T3 in each write circuit 13 in FIG. 1) connecting the write lines WWL1 to WWL3 and the power supply circuit 14 are turned off, the power supply circuit 14 is turned off. The current from is charged into the parasitic capacitance (the above-mentioned overlap capacitance and diffusion capacitance) of the switch element φ100. However, since the switch element φ100 is turned off, no current flows through the transistors T1 and T3, and the transistors T1 and T3 are not charged. Therefore, the parasitic capacitance of the switch element on the write line side as viewed from the power supply circuit 14 is only the parasitic capacitance of the switch element φ100.

On the other hand, in the conventional magnetic memory device shown in FIG. 8, switch elements for connecting the write lines WWL1 to WWL3 and the power supply circuit 14 (transistors T1 and T3 in each write circuit 13 in FIG. 8). When all are turned off, the current from the power supply circuit 14 is charged in the parasitic capacitance of the transistors T1 and T3. Therefore, the parasitic capacitance of the switch element on the write line side as viewed from the power supply circuit 14 becomes a combined capacitance of the parasitic capacitances of the transistors T1 and T3 connected in parallel to the power supply circuit 14 by the number of write lines.

As a result, in this embodiment, the parasitic capacitance C
Since the parasitic capacitance of the switch element, which is dominant in 10 in FIG. 10, is greatly reduced as compared with the conventional example, the overshoot occurring in the write current at the time of writing data can be suppressed as shown in FIG.

Similarly, since the parasitic capacitance of the switch element on the bit line side is greatly reduced as compared with the conventional example, the overshoot generated in the assist current at the time of writing to each magnetoresistive element is shown in FIG. Can be suppressed.

Regarding the operation at the time of writing data in the magnetic memory device shown in FIG. 1, the switch element φ1 is provided at the same time as or before and after the write current is applied to the write line.
A high pulse is applied to 00 to turn it on, and a high pulse is applied to the switching element φ200 to turn it on at the same time as or before and after the assist current is passed to the bit line. Therefore, the description thereof will be omitted.

In this embodiment, the switch elements φ100 and φ200 are provided as the collective switches in the preceding stages of the write line and the bit line, respectively, to suppress the overshoot of both the write current and the assist current. However, the present invention is not limited to this, and by providing the collective switch only in the preceding stage of either the write line or the bit line, suppression of overshoot of only one of the write current and the assist current is suppressed. It may be configured to achieve.

Further, in the present embodiment, the current is bidirectionally passed through each write line by one constant current source, but the present invention is not limited to this, and a plurality of current lines are provided as shown in FIG. It can also be applied to a configuration in which a constant current source causes a current to flow bidirectionally in each write line. FIG. 4 shows four constant current sources 1.
51 to 154, a configuration is shown in which a current flows bidirectionally through the write lines WWL1 to WWL3.
When a current flows in the counterclockwise direction shown in WL1 to WWL3, the constant current sources 151 and 154 are selected to supply the current, and when a current flows in the clockwise direction shown in each write line WWL1 to WWL3, the constant current source 152 , 153 is selected to pass a current. The constant current sources 151 and 152 and the constant current source 15
3, 154 may be provided in the same power supply circuit,
Further, two or more power supply circuits may be provided and may be provided in different power supply circuits.

Further, in the present embodiment, the current is passed in both directions to each write line, but the present invention is not limited to this, and as shown in FIG. 5, each write line is only in one direction. It is also applicable to a configuration in which an electric current is passed.

[0041]

As described above, according to the present invention, it is necessary to separate the power supply circuit from the two or more first switching elements.
It has three or more third switch elements, and a current is supplied to the write line via the first switch element and the third switch element. Thereby, the first switch element and the third switch element that supply current to the plurality of write lines are provided.
Even if all the switch elements are turned off, charges are charged only in the parasitic capacitance of the third switch element, and the parasitic capacitance on the write line side as seen from the power supply circuit is greatly reduced by the amount of the first switch element. There is an effect that a current whose overshoot is suppressed can be passed through the write line at the time of writing data.

Further, there is provided one or more fourth switch elements for separating the power supply circuit from the two or more second switch elements, and the bit line has the second switch element and the fourth switch element. For the same reason as described above, the parasitic capacitance on the bit line side seen from the power supply circuit is greatly reduced by the amount of the second switch element. This has the effect of allowing a current whose overshoot is suppressed to flow.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a magnetic memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the overall configuration of the magnetic memory device shown in FIG.

FIG. 3 is a diagram showing switching elements φ100 and φ200 shown in FIG.
It is a figure which shows one structural example.

FIG. 4 is a diagram showing a configuration of a magnetic memory device according to another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a magnetic memory device according to still another embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a configuration of a memory cell array of MRAM.

FIG. 7 is a cross-sectional view showing an example of the configuration of a memory cell.

FIG. 8 is a diagram illustrating in detail a configuration of a portion related to data writing of the memory cell array illustrated in FIG.

FIG. 9 is a diagram showing an example of a pulse current waveform at the time of writing in the conventional magnetic memory device.

FIG. 10 is a diagram showing an example of a pulse current waveform at the time of writing in the magnetic memory device of the present invention.

[Explanation of symbols]

M11-M33 Magnetoresistive element 141, 142, 151-154 constant current source φ100, φ200 switch element WWL1 to WWL3 write lines BL1 to BL3 bit lines φWWL11 to φWWWL32 switch element φBL1 to φBL3 switch elements T1 to T4 transistors C10, C20 parasitic capacitance

Claims (8)

[Claims] 1. A plurality of memory cells provided with a magnetoresistive element and arranged in a matrix, a current source for supplying a current, a plurality of wirings for applying a magnetic field to the memory cells, and a plurality of wirings for each of the plurality of wirings. A magnetic memory device comprising: a switch element that supplies a current from the current source; and a switch element that separates the current source from the plurality of switch elements. 2. A plurality of memory cells provided with a magnetoresistive element and arranged in a matrix, a plurality of write lines for applying a magnetic field to the memory cells, and provided for each of the plurality of write lines. A first switch element for supplying a current to a write line, a plurality of bit lines arranged to intersect the plurality of write lines and connected to the memory cells, and provided for each of the plurality of bit lines. A second switching element for supplying a current to a corresponding bit line, and a magnetic memory device having one or more third switching elements for disconnecting the power supply circuit from the plurality of first switching elements. And / or a fourth switch element for disconnecting the power supply circuit from the plurality of second switch elements. 3. The power supply circuit, wherein the write line is connected to the first switch element through the third switch element, and the bit line is the second switch element and the fourth switch element. 3. The magnetic memory device according to claim 2, wherein the power supply circuit connected to the power supply circuit is the same power supply circuit. 4. The magnetic memory device according to claim 2, wherein in the power supply circuit, the write line and the bit line are connected to a constant current source. 5. The magnetic memory device according to claim 2, wherein the third switch element and the fourth switch element are MOS field effect transistors. 6. When writing data to the magnetoresistive element, a current is applied to the corresponding write line and bit line,
The magnetic memory device according to claim 2, wherein the magnetic fields respectively induced by the currents are applied to the magnetoresistive element. 7. The write line is configured by connecting one ends of wirings arranged so as to sandwich the element row of the magnetoresistive element to each other, and connecting the write line to one constant current source, A plurality of fifth switch elements are provided in the first switch element connected to the line, and by switching the plurality of fifth switch elements, a current flows in the write line bidirectionally. The magnetic memory device according to claim 2. 8. The write line is configured by connecting one ends of wirings arranged so as to sandwich the element row of the magnetoresistive element to each other, and connecting the write line to a plurality of constant current sources. 7. The magnetic memory device according to claim 2, wherein a current flows bidirectionally in the write line by the constant current source.