JP2007102904A - Magnetic random access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic random access memory capable of generating a suitable amount of boost current corresponding to temperature characteristics of a magnetoresistive element. <P>SOLUTION: This magnetic random access memory is provided with: a memory array (2) in which memory cells for storing data by a direction of magnetization and write-in wiring are arranged; constant current sources (7, 7A, 7B) for allowing constant currents to flow through the write-in wiring in order to write the data to selected memory selected from among the memory cells; and boost current sources (8. 8A-8D, 9, 9A-9C) for supplying boost currents to charge parasitic capacitance of the paths through which the constant current flows just after starting the write-in operation. The amounts of the constant currents and boost currents are controlled according to operation temperature. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a magnetic random access memory, and more particularly to a technique for generating a write current in a magnetic random access memory.

  In recent years, with the rapid spread of portable devices such as mobile phones, there is an increasing demand for memories that realize nonvolatile data storage, high-speed access to data, large storage capacity, and low voltage operation. One of the promising memories that satisfy such requirements is a magnetic random access memory.

  A memory cell of a magnetic random access memory (MRAM) is generally composed of a magnetoresistive element such as an MTJ (magnetic tunnel junction) element. FIG. 1 is an example of the most typical structure of an MRAM memory cell composed of MTJ elements; the MRAM memory cell shown in FIG. 1 will be described as a conventional memory cell. Referring to FIG. 1, a conventional memory cell 100 is configured by a stacked body in which a pinned magnetic layer (pinned layer) 101, a tunnel insulating layer 102, and a free magnetic layer (free layer) 103 are stacked. The direction of magnetization of the pinned magnetic layer 101 is fixed during manufacturing. On the other hand, the free magnetic layer 103 is formed so that its magnetization direction can be reversed by a magnetic field generated by the wiring current. In a typical magnetic random access memory, the magnetization direction of the free magnetic layer 103 is inverted by a magnetic field generated by currents flowing through bit lines and word lines arranged above and below the MTJ element. One of the magnetization directions of the free magnetic layer 103 is assigned to data “1”, and the other is assigned to data “0”. The data stored in the MTJ element is read out using the change in electrical resistance of the MTJ element depending on the magnetization direction of the free magnetic layer 103; the relative directions of magnetization of the fixed magnetic layer 101 and the free magnetic layer 103 are parallel. In some cases (corresponding to data “0” in FIG. 1), the electrical resistance of the MTJ element is small, and when it is antiparallel (corresponding to data “1” in FIG. 1), the electrical resistance is large.

  One problem with magnetic random access memories that use conventional memory cells is poor memory cell selectivity. A technique for solving this problem is a toggle writing system disclosed in US Pat. No. 6,545,906. FIG. 2 is a schematic diagram of the structure of the MRAM memory cell 100A corresponding to the toggle writing method; hereinafter, the MRAM memory cell shown in FIG. 2 will be described as a toggle type memory cell. In the toggle memory cell 100A, the free magnetic layer is formed of a stacked body including a plurality of ferromagnetic layers separated by a nonmagnetic layer. In the MRAM memory cell 100A of FIG. 2, the free magnetic layer is composed of a first free magnetic layer 103A and a second free magnetic layer 103B separated by a nonmagnetic layer 104. The first free magnetic layer 103A and the second free magnetic layer 103B are configured such that their magnetization directions can be reversed by a magnetic field generated by the wiring current. One of the magnetization directions of the first free magnetic layer 103A is assigned to data “1”, and the other is assigned to data “0”. When the relative magnetization directions of the pinned magnetic layer 101 and the first free magnetic layer 103A are parallel (corresponding to data “0” in FIG. 2), the electrical resistance of the MTJ element is small and antiparallel (FIG. 1). Then, data “1”) has a large electric resistance. The magnetizations of the first and second free magnetic layers 103A and 103B are antiferromagnetically coupled by exchange interaction via the nonmagnetic layer 104; that is, the magnetizations of the first and second free magnetic layers 103A and 103B. Are facing in opposite directions. This plays an important role in toggle writing as described below.

  FIG. 3 is a plan view showing an example of the configuration of the memory array of the magnetic random access memory, and FIG. 4 is a cross-sectional view. In the memory array, memory cells 100 (or 100A) are arranged in a matrix. Above each memory cell 100, bit lines 106 (BL) extending in parallel to each other in the vertical direction are provided, and below (writing) word lines 105 (extending in parallel to each other in the horizontal direction). WL).

  As shown in FIG. 4, one end of the memory cell 100 (100A) is connected to the bit line 106 via a contact 117, and the other end is connected to the antiferromagnetic layer 116. When a read operation is performed, the read current is read through the bit line 106, the memory cell 100 (100A), the antiferromagnetic layer 116, the base electrode 115, the contact 114, and the access transistor 112 formed on the substrate 110. It flows to the termination electrode 111. On / off of the access transistor 112 is controlled by the level of the read word line 112. On the other hand, when a write operation is performed, a write current is passed through the write word line 105 and the bit line 106, and the free magnetic layer 103 (or the first free magnetic layer 103A and the second free magnetic layer 103A) is generated by the magnetic field generated by the write current. The magnetization of the layer 103B) is reversed.

FIG. 5A is a timing chart showing a write operation to the conventional memory cell 100, and FIG. 5B is a conceptual diagram showing the magnetization direction of the free magnetic layer 103. When the conventional memory cell 100 is rewritten from data “0” to data “1”, _first , the write word line current I _WL is raised at time t ₁ . Then, it begins to conduct write bit line current _{I BL} at time _{t 2.} When the combined magnetic field of the magnetic fields H _X and H _Y generated by the word line current I _WL and the bit line current I _BL at this time satisfies the predetermined condition shown in FIG. 7A, the magnetization of the free magnetic layer 103 is Invert. Subsequently lowered the write word line current I _WL at time t _3, then at time t ₄ by turning off the write bit line current I _BL, the write operation is completed. When the conventional memory cell 100 is rewritten from data “1” to data “0”, only the direction of the bit line current _IBL is inverted while the direction of the word line current _IWL is left as it is.

On the other hand, FIG. 6A is a timing chart showing the write operation of the toggle write method when the toggle memory cell 100A is rewritten from data “0” to data “1”, and FIG. 6B shows the first free magnetic layer 103A, the first It is a conceptual diagram which shows the direction of magnetization of 2 free magnetic layer 103B. In the toggle writing method, the magnetization of the first and second free magnetic layers 103A and 103B is reversed by rotating the direction of the applied magnetic field. Specifically, first, at time t ₁ , the write word line current I _WL is raised and a magnetic field H _{X is applied} to the first free magnetic layer 103A and the second free magnetic layer 103B. Then, launch the write bit line current _{I BL} at time _{t 2.} When the combined magnetic fields of the magnetic fields H _X and H _Y generated by the word line current I _WL and the bit line current I _BL at this time satisfy the predetermined condition shown in FIG. 7B, the first free magnetic layer 103A and The combined magnetization of the second free magnetic layer 103B is directed in the direction of the combined magnetic field H _X + H _Y. Subsequently, by at time _{t 3} lowers the write word line current _{I WL,} the MRAM memory cells 100, only the magnetic field _{H Y} is applied, the synthetic magnetization oriented in the direction of the magnetic field _{H Y.} Finally, by lowers the write bit line current I _BL at time t _4, the write operation is completed. In this state, it should be noted that the orientations of the first and second free magnetic layers 103A and 103B are opposite to the original directions. By the same procedure, the toggle memory cell 100A can be rewritten from data “1” to data “0”.

In a magnetic random access memory employing the conventional memory cell 100, it is necessary to apply a magnetic field of an appropriate magnitude in order to selectively write data to a desired memory cell. FIG. 7A shows a magnetic field region in the conventional memory cell 100 in which magnetization reversal is possible. If a magnetic field corresponding to a region outside the magnetization reversal curve (that is, the “inversion” region and the “multiple selection” region) is applied, writing can be performed on the selected cell. For example, when a magnetic field H _DX in the X direction and a magnetic field H _{DY in the} Y direction having a magnitude as shown in FIG. 7A are applied to the selected memory cell, the resultant magnetic field vector (H _DX , H _DY ) is “inverted”. Since it is in the region, the magnetization of the free magnetic layer 103 of the selected memory cell is reversed. At this time, in half-selected memory cells (that is, memory cells connected to only one of the selected bit line and the selected word line), magnetic fields H _DX and H _DY corresponding to the inner region of the magnetization reversal curve are applied. Therefore, magnetization reversal does not occur. That is, selective writing is possible. However, in order to enable selective writing, it is necessary to appropriately control the word line current I _WL and the bit line current I _BL . When an excessively large word line current I _WL and bit line current I _BL that generate magnetic fields H _X and H _Y corresponding to the “multiple selection” region of FIG. 7A are flowed, the word line current I _WL and the bit line current I A magnetic field H _X0 corresponding to a region outside the magnetization reversal curve is generated in only one of the _BLs , and writing is also performed to the half-selected memory cell; that is, writing occurs. In order to perform selective writing, it is necessary to pass a word line current I _WL and a bit line current I _BL having a magnitude corresponding to the “inverted” region in FIG. 7A. In other words, the word line current I _WL and the bit line It is necessary to appropriately control the current _IBL .

On the other hand, the magnetic random access memory using the toggle type memory cell 100A can avoid the problem of selectivity. FIG. 7B shows a magnetic field region in which the magnetization reversal of the toggle memory cell 100A is possible. When a magnetic field H _DX in the X direction and a magnetic field H _{DY in the} Y direction having the magnitudes shown in FIG. 7B are applied to the selected memory cell, the resultant magnetic field vector (H _DX , H _DY ) is in the “inversion” region. Therefore, the magnetizations of the first and second free magnetic layers 103A and 103B of the toggle memory cell 100A are reversed, and data is written to the toggle memory cell 100A. Since the distance between the magnetization reversal curve and the X-axis and Y-axis is largely separated, magnetization reversal hardly occurs in the half-selected memory cell. This means that toggle writing has excellent memory cell selectivity.

However, even with toggle writing, it is still important to appropriately control the magnitudes of the word line current I _WL and the bit line current I _BL . If the word line current I _WL and the bit line current I _BL are excessively large, the combined magnetic fields (H _DX , H _DY ) generated by them become excessively large, and the toggle memory cell 100A has a “magnetization saturation” region. A corresponding magnetic field is applied. When an excessively large magnetic field is applied, the magnetizations of the first and second free magnetic layers 103A and 103B are directed in the same direction, and the first and second free magnetic layers 103A and 103B after the magnetic field is removed. The direction of magnetization of becomes indefinite. This means that erroneous writing occurs stochastically. Therefore, an excessively large word line current I _WL and bit line current I _BL are not allowed to flow through the word line 105 and the bit line 106. In order to prevent erroneous writing, it is necessary to flow a word line current I _WL and a bit line current I _BL having appropriate magnitudes.

One advantage of magnetic random access memory is said to be high speed writing. Actually, since the magnetization reversal time of the magnetic material is 1 nsec or less, high speed writing of the magnetic random access memory is possible in principle. is there. However, one problem is that the high speed of writing is impaired due to the parasitic capacitance existing in the wiring and selector through which the write current flows, and the power consumption at the time of writing increases. If an attempt is made to generate a write current for reversing the magnetization with only a constant current source, a charge is accumulated in the parasitic capacitance of the wiring and the selector, so that a considerable delay time (until the write current of a desired magnitude actually flows) Typically 10 nm). This problem becomes more prominent as the memory capacity increases. For example, as shown in FIG. 8, the large-capacity array is often composed of M × N small arrays. In this case, the parasitic resistance and the parasitic capacitance are the memory sizes L _X , L _It increases as _Y increases.

FIG. 9 illustrates a small array located in the first row of the small arrays illustrated in FIG. N small arrays are arranged in one row. A write current is supplied to the memory cells located in these small arrays by the X-side constant current source circuit 201. Notably, for example, the current path 202 ₁ for supplying to the memory cell write current of the small array (1,1), a current path for the memory cell a write current of a small array (1, N) in a 202 _N, it is that the length is different. The change in the length of the current path causes a change in the wiring potential in addition to the change in the wiring resistance and parasitic capacitance, so the change in the length of the current path is the charge required to charge the parasitic capacitance in the current path. Bring about a change in quantity. This means that the delay time of the current path is different.

  However, in the architecture of a conventional magnetic random access memory that uses a constant current source to generate a write current, it is difficult to flow the write current in a short time by minimizing the influence of the parasitic capacitance depending on the location of the selected array. is there. In addition, since the amount of charge accumulated in the parasitic capacitance varies depending on the magnitude of the write current, the rise time of the write current differs depending on the magnitude of the write current. This makes it difficult to realize high-speed writing independent of the magnitude of the write current. In addition, an increase in the rise time of the write current undesirably increases the power consumption, but it is difficult to avoid this problem in the conventional magnetic random access memory architecture.

  Japanese Patent Laid-Open No. 2004-234816 discloses a magnetic random access including a current boost circuit that generates an instantaneous current using a capacitor in addition to a constant current source that generates a write current in order to overcome such difficulties. A memory is disclosed. As shown in FIG. 10, the known magnetic random access memory includes an X-side current boost circuit 301, a Y-side boost circuit 302, an X-side write constant current source circuit 303, and a Y-side write constant current source. Circuit 304.

  The X-side current boost circuit 301 is a circuit that generates a boost current IBX for charging a parasitic capacitance. The X-side current boost circuit 301 includes a capacitor CBX, PMOS transistors MSX and MBX, a power supply terminal 305, and an inverter 306. One end of the capacitor CBX is grounded, and the other end is connected to the node VBX. The node VBX is connected to the power supply terminal 305 to which the power supply voltage Vbst is supplied via the PMOS transistor MBX. The node VBX is further connected to the node NLX via the PMOS transistor MSX. The node NLX is a node connected to the output of the X side write constant current source circuit 303. The X-side boost signal VBSTX is input to the gate of the PMOS transistor MBX, and the X-side boost signal VBSTX is input to the gate of the PMOS transistor MSX via the inverter 306. The X-side boost signal VBSTX is a signal that allows or prohibits the X-side current boost circuit 301 to generate the boost current IBX. The PMOS transistors MBX and MSX are exclusively turned on in response to the X-side boost signal VBSTX.

  The Y-side current boost circuit 302 is a circuit that generates a boost current IBY. The Y-side boost circuit 302 has the same configuration and function as the X-side current boost circuit 301, and includes a capacitor CBY, PMOS transistors MSY and MBY, a power supply terminal 307 to which a power supply voltage Vbst is supplied, and an inverter. 308.

  Each of the X-side write constant current source circuit 303 and the Y-side write constant current source circuit 304 is a constant current source having a large output impedance, and is configured to allow a constant current to flow without being affected by the load. Has been. The magnitudes of the currents generated by the X-side write constant current source circuit 303 and the Y-side write constant current source circuit 304 coincide with the magnitude of the write current that is finally passed through the cell array. The X-side write constant current source circuit 303 starts generating the constant current ICX in response to the activation of the X-side write enable signal WENX. Similarly, the Y-side write constant current source circuit 304 starts generating the write current ICY in response to the activation of the X-side write enable signal WENY.

  FIG. 11 is a timing chart showing the operations of the X-side current boost circuit 301 and the X-side write constant current source circuit 303; the Y-side boost circuit 302 and the Y-side write constant current source circuit 304 perform the same operation.

  In the initial state, both the X-side write enable signal WENX and the X-side boost signal VBSTX are at the low level (Gnd). In this state, the PMOS transistor MBX is turned on and the PMOS transistor MSX is turned off. Therefore, the capacitor CBX is charged by the power supply voltage Vbst.

  When the X-side write enable signal WENX and the X-side boost signal VBSTX are activated (that is, when the Low level is switched to the High level (Vdd)), the PMOS transistor MBX is turned off and the PMOS transistor MSX is turned on. Since the potential of the node VBX is approximately Vbst and the wiring potential is a lower potential, for example, Gnd, the electric charge accumulated in the capacitor CBX rapidly flows to the wiring selected by the X selector; Boost current IBX that rises sharply from side current boost circuit 301 flows into node NLX. This boost current IBX flows for several nsec while charging the parasitic capacitances CLX, CX1,..., CXm. Eventually, when the potential of the node VBX becomes equal to the potential of the node NLX, the boost current IBX stops. While the X-side boost signal VBSTX is activated, the potential of the node VBX decreases by ΔVBX. Conversely, the potential of the node NLX (that is, the potential of the wiring selected by the X selector) is changed from the ground potential to Vbst−. It rises to ΔVBX.

  When the write current is generated by the X-side write constant current source circuit 303 alone, the write current is used for charging the parasitic capacitance, so that the rise of the current that actually flows through the wiring becomes dull. However, if the X-side current boost circuit 301 is used, the parasitic capacitance can be rapidly charged by the boost current IBX, so that current waveform dullness is reduced. If the capacitance of the capacitor CBX is appropriately designed, the write current ICX + IBX that actually flows through the cell array can be raised in a short time (typically about 2 nsec) as shown in the lowermost stage of FIG. . Therefore, writing is completed at a high speed and an increase in power consumption is prevented.

  Another problem of the magnetic random access memory is that the MTJ element has a temperature dependency. For example, as shown in FIG. 12A, in the conventional memory cell 100, the higher the temperature, the smaller the reversal magnetic field (coercive magnetic field). Therefore, the current necessary for reversing the magnetization (magnetization reversal current) also increases. Get smaller. Typically, when the temperature is increased by 100 ° C., the magnitude of the magnetization reversal current is reduced by 20%. On the other hand, at a low temperature, the magnitude of the magnetization reversal current increases. Therefore, in order to prevent erroneous writing to the half-selected memory cell, it is necessary to appropriately control the magnitude of the write current according to the temperature.

  Similarly, as shown in FIG. 12B, in the toggle memory cell 100A, the higher the temperature, the smaller the reversal magnetic field and the smaller the magnetization reversal current. Typically, when the temperature is increased by 100 ° C., the magnitude of the magnetization reversal current is reduced by 20%. In addition, the magnetic field that saturates the magnetization of the free magnetic layer (that is, the magnitude of the write current (magnetization saturation current) that saturates the magnetization) also decreases as the temperature increases. On the other hand, at a low temperature, the magnitude of the magnetization reversal current increases. Therefore, in order to prevent erroneous writing, it is necessary to appropriately control the magnitude of the writing current according to the temperature.

  However, the magnetic random access memory including the current boost circuit of FIG. 10 cannot generate an appropriate boost current corresponding to the temperature dependence of the magnetization reversal current. The amount of charge stored in the capacitor CBX is determined only by the power supply voltage Vbst and the capacitance C of the capacitor CBX, and generally has no temperature dependence. This means that the boost current is constant regardless of temperature. In the current boost circuit of FIG. 10, the boost current cannot be appropriately controlled according to the temperature. This is not preferable in order to appropriately control the magnitude of the write current finally passed through the memory array in accordance with the temperature.

  In relation to the present invention, Japanese Patent Application Laid-Open No. 2003-257175, Japanese Patent Application Laid-Open No. 2004-095157, and Japanese Patent Application Laid-Open No. 2004-234816 disclose writing generated by a constant current source according to the temperature dependence of the MTJ element A technique for controlling the magnitude of current is disclosed. However, the techniques disclosed therein do not mention anything about the control of the boost current generated by the current boost circuit.

Accordingly, it is desired to provide a magnetic random access memory capable of generating a boost current having an appropriate magnitude corresponding to the temperature characteristics of the magnetoresistive element.
US Pat. No. 6,545,906 JP 2004-234816 A JP 2003-257175 A JP 2004-095157 A

  An object of the present invention is to provide a magnetic random access memory capable of generating a boost current having an appropriate magnitude corresponding to the temperature characteristics of a magnetoresistive element.

  In order to achieve the above object, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Best Mode for Carrying Out the Invention] Number / symbol used in the best mode for doing this is added. However, the added number / symbol should not be used to limit the technical scope of the invention described in [Claims].

  The magnetic random access memory according to the present invention includes a memory array (2) in which a memory cell for storing data according to the direction of magnetization, a write wiring, and a selected memory cell selected from the memory cells. A constant current source (7, 7A, 7B) for supplying a constant current for writing to the write wiring and a boost current for charging a parasitic capacitance of a path through which the constant current flows immediately after the write operation is started Boost current sources (8, 8A-8D, 9, 9A-9C). The magnitudes of the constant current and the boost current are controlled according to the operating temperature. More specifically, the magnitudes of the constant current and the boost current are decreased as the operating temperature is increased. In such a magnetic random access memory, the magnitude of the boost current is controlled according to the operating temperature in addition to the constant current generated by the constant current source (7, 7A, 7B). In addition to raising the current, it is possible to generate a write current having temperature dependence that more appropriately corresponds to the temperature characteristics of the memory cell.

  In one embodiment, the boost current source (8, 8A-8D, 9, 9A-9C) is a current boost circuit (8) that outputs the boost current by discharging a charge charged in a capacitive element (CBX). , 8A-8C) and control means (9, 9A-9C) for controlling the magnitude of the boost current output from the current boost circuit (8, 8A-8C) according to the operating temperature. Yes.

  In a preferred embodiment, the control means (9A-9C) includes a first node (NLX) to which an output of the current boost circuit (8, 8A-8D) is connected for a predetermined time after the write operation is started. , VCX), or a current clamper circuit (9A-9C) for flowing a subtraction current from the first node (VCX) to the ground terminal (29). The magnitudes of the addition current and the subtraction current are controlled according to the operating temperature. Such a configuration is suitable for reducing the number of switch elements existing on the path through which the boost current flows from the capacitor element (CBX), and for quickly raising the write current.

  In order to reduce the number of switch elements of the write circuit, the magnetic random access memory includes a second node (NLX) electrically connected to the write wiring of the memory array (2) and the first node ( VCX) and a switch element (MP8) connected between the second node (NLX) and an output of the constant current source is connected to the first node (VCX). Is preferred.

  The current clamper circuit (9C) is preferably configured to control the subtraction current according to the position of the selected memory cell. In this case, it is preferable that the subtraction current is reduced as the position of the selected memory cell is farther from the constant current source.

  In another embodiment, one terminal of the capacitive element (CBX) of the current boost circuit (8C) is connected to the first node (VCX), and the other terminal pulls the potential in response to the start of the write operation. It is preferable to be connected to the third node (VBX) that is up. Such a configuration is suitable for reducing the capacitance value of the capacitor (CBX).

  In this case, in one embodiment, the third node (VBX) is connected to the power supply terminal (23) via the first switch element (MP1), and is connected to the ground terminal via the second switch element (MN3). Connected to (22). When the write operation is started, the first switch element (MP1) is turned on, the second switch element (MN3) is turned off, and when the write operation is finished, the first switch element (MP1) is turned off. Then, the second switch element (MN3) is turned on.

  In another embodiment, the magnetic random access memory according to the present invention further comprises a temperature compensation voltage generation circuit (13) for generating a control voltage (VP) depending on the operating temperature. The boost current source (8D) functions as a capacitive element for generating the boost current, and has a PMOS transistor (MP9) supplied with a predetermined first power supply voltage to the drain, immediately before the write operation is started. The control voltage (VP) is supplied to the gate of the PMOS transistor (MP9) until a predetermined second power supply voltage higher than the control voltage is applied to the gate of the PMOS transistor (MP9) when the write operation is started. Switch circuits (MP1, MC1) for supplying to

  According to the present invention, a magnetic random access memory capable of generating a boost current having an appropriate magnitude corresponding to the temperature characteristics of the magnetoresistive element is provided.

  Hereinafter, embodiments of a magnetic random access memory according to the present invention will be described with reference to the accompanying drawings. It should be noted that in the accompanying drawings, the same, corresponding or similar elements are referred to by the same or corresponding reference numerals.

First embodiment:
FIG. 13 is a block diagram showing a configuration of the magnetic random access memory 1 according to the first embodiment of the present invention. The magnetic random access memory 1 includes a memory array 2, an X-side selector 3, and a Y-side selector 4. The memory array 2 has the configuration shown in FIG. That is, the memory array 2 includes a plurality of write word lines extending in parallel with the X-axis direction and bit lines extending in parallel with the Y-axis direction. MTJ elements used as memory cells are arranged in a matrix at the intersecting positions. The X-side selector 3 is used for selecting a write word line, and the Y-side selector 4 is used for selecting a bit line.

  An X-side constant current source circuit 7 and a Y-side constant current source circuit 10 are provided to supply write currents IWX and IWY to the write word line and the bit line, respectively. Each of the X-side constant current source circuit 7 and the Y-side constant current source circuit 10 is a constant current source having a large output impedance so that a constant current can be generated without being affected by the load. It is configured. The magnitude of the constant current generated by the X-side constant current source circuit 7 and the Y-side constant current source circuit 10 is the magnitude of the write current that is finally passed through the memory array 2 (that is, at the final stage of the write operation). Match.

  In addition, the magnetic random access memory 1 includes an X-side current boost circuit 8, an X-side current temperature compensation circuit 9, a Y-side current boost circuit 11, a Y-side current temperature compensation circuit 12, and a temperature compensation voltage generation circuit 13. Yes. The X-side current boost circuit 8 is a circuit used to generate a boost current that charges a load capacitance existing in a path through which the write current generated by the X-side constant current source circuit 7 flows. Similarly, the Y-side current boost circuit 11 is a circuit used to generate a boost current that charges a load capacitance existing in a path through which the write current generated by the Y-side constant current source circuit 10 flows. The X-side current temperature compensation circuit 9 and the Y-side current temperature compensation circuit 12 are circuits for controlling the boost current generated by the X-side current boost circuit 8 and the Y-side current boost circuit 11 in response to the temperature, respectively. is there. The temperature compensation voltage generation circuit 13 is a circuit that generates a control voltage VP in response to temperature. As shown in FIG. 18A, the control voltage VP increases as the operating temperature of the magnetic random access memory 1 increases. The X-side current boost circuit 8 and the Y-side current boost circuit 11 control the boost current in response to the control voltage VP. One feature of the magnetic random access memory of this embodiment is that the magnitude of the boost current is controlled in response to the control voltage VP, that is, in response to the operating temperature of the magnetic random access memory 1.

  FIG. 14 is a block diagram showing the configuration of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current temperature compensation circuit 9 in this embodiment; the Y-side constant current source circuit 10 and the Y-side current The configurations of the boost circuit 11 and the Y-side current temperature compensation circuit 12 are the same as those of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current temperature compensation circuit 9, respectively.

  The X-side constant current source circuit 7 is a constant current source that generates a constant current ICX, and includes PMOS transistors MP4 and MP5, and a power supply terminal 25 to which a power supply voltage Vdd is supplied. The PMOS transistors MP4 and MP5 are connected in series between the node NLX connected to the input of the X-side selector 3 and the power supply terminal 25. The control voltage VP generated by the temperature compensation voltage generation circuit 13 is supplied to the gate of the PMOS transistor MP4, and the write enable signal WENX is supplied to the gate of the PMOS transistor MP5 via the inverter 24. The X-side constant current source circuit 7 configured as described above generates a constant current ICX having a magnitude corresponding to the control voltage VP when the write enable signal WENX is pulled up to a high level.

  The X-side current boost circuit 8 is a circuit that generates a boost current IBX, and includes a PMOS transistor MP1, a capacitor CBX, a ground terminal 22, and a power supply terminal 23 to which a boost power supply voltage Vbst is supplied. The capacitor CBX is connected between the node VBX and the ground terminal 22, and the PMOS transistor MP1 is connected between the node VBX and the power supply terminal 23. The boost signal VBSTX is supplied to the gate of the PMOS transistor MP1. The PMOS transistor MP1 electrically connects or disconnects the capacitor CBX from the power supply terminal 23 according to the boost signal VBSTX. When the capacitor CBX is connected to the power supply terminal 23, the capacitor CBX is charged with the power supply voltage Vbst. That is, the power supply voltage Vbst is a power supply voltage used for charging the capacitor CBX. The charge stored in the capacitor CBX is used to generate the boost current IBX.

  Boost power supply voltage Vbst is preferably generated independently of other power supply voltages Vdd. Such a configuration is suitable in order to suppress the influence of fluctuations in the power supply voltage Vdd that can occur particularly during writing on the amount of charge accumulated in the capacitor CBX.

  PMOS transistors MP2 and MP3 are connected in series between the node VBX of the X-side current boost circuit 8 and the node NLX. The control voltage VP is supplied from the temperature compensation voltage generation circuit 13 to the gate of the PMOS transistor MP2, and the PMOS transistor MP2 functions as an X-side current temperature compensation circuit 9 that controls the boost current IBX according to the temperature. The boost signal VBSTX is supplied to the PMOS transistor MP3 via the inverter 21. The PMOS transistor MP3 outputs the boost current IBX in response to the boost signal VBSTX or cuts it off.

  During boost standby (ie, when the boost signal VBSTX is at a low level), the PMOS transistor MP1 is turned on and the PMOS transistor MP3 is turned off, so that the charge QBX (= C · Vbst) is accumulated in the capacitor CBX: C is the capacitance of the capacitor CBX. When the current boost is permitted (that is, when the boost signal VBSTX is pulled up to a high level), the PMOS transistor MP1 is turned off and the PMOS transistor MP3 is turned on, so that the charge accumulated in the capacitor CBX is applied to the node NLX. Is released, thereby generating a boost current IBX instantaneously. The magnitude of the boost current IBX is controlled according to the control voltage VP by the X-side current temperature compensation circuit 9 (that is, by the PMOS transistor MP2).

  It should be noted that the constant current ICX generated by the X-side constant current source circuit 7 and the boost current IBX generated by the X-side current boost circuit 8 are both controlled according to the control voltage VP. As described above, the control voltage VP is a voltage generated according to the operating temperature of the magnetic random access memory 1, and therefore the constant current ICX and the boost current IBX have the same temperature dependency; The constant current ICX and the boost current IBX both decrease with increasing temperature and increase with decreasing temperature, as shown in FIG. 18B.

FIG. 15 shows an example of the configuration of the capacitor CBX. In one embodiment, the capacitor CBX is configured with a gate capacitance of a MOS transistor. Specifically, P-well 52 is formed on the substrate 51, ^{N +} drain region 53 is formed on the P-well 52. Above the P well 52, a gate electrode 54 insulated from the P well 52 by a gate oxide film 55 is formed. Gate electrode 54 is connected to node VBX, and N ⁺ drain region 53 is connected to ground terminal 22. The capacitance of the capacitor CBX formed in this way is determined by the area of the gate electrode 54.

FIG. 16A shows an example of the configuration of the temperature compensation voltage generation circuit 13. In one embodiment, the temperature compensation voltage generation circuit 13 includes a reference voltage generation circuit 41 and a voltage conversion circuit 42. The reference voltage generation circuit 41 is a circuit that generates a reference voltage V _ref in response to an operating temperature. Typically, a band gap reference circuit is used as the reference voltage generation circuit 41. In one embodiment, the reference voltage generation circuit 41 includes diodes D _{0 to} D ₂ , resistors R ₁ and R ₂ , NMOS transistors 43 and 44, and PMOS transistors 45 to 47. The voltage conversion circuit 42 is a circuit that converts the reference voltage V _ref to a control voltage VP, and includes resistors R ₃ and R ₄ and an operational amplifier 48. According to the configuration of the temperature compensation voltage generation circuit 13 as described above, the control voltage VP represented by the following formula (1) is generated:
VP = (1 + R ₄ / R ₃ ) V <sub>0
- (R 4 / R 3)</sub> {V F + (k B T / q) · (R 2 / R 1) ln (N)}. ... (1)
Here, _{V F} is the junction potential of the diode _{D 2,} N is the area ratio of the PN junction of the diode _D 0, _{D 1, k B} is the Boltzmann constant, q is the elementary charge. The temperature dependence of the control voltage VP can be controlled by the resistances R _{1 to} R ₄ , N and the value of the voltage V ₀ supplied to the normal input of the operational amplifier 48.

The temperature compensation voltage generation circuit 13 can adopt other configurations. For example, as shown in FIG. 16B, it is also possible to use a reference voltage generating circuit 41A of the PNP bipolar transistor _Q 0 to Q ₂ which is diode-connected in place of the diode _D 0 to D ₂ is incorporated . FIG. 17A shows a typical structure of the diodes D _{0 to} D ₂ , and FIG. 17B shows a typical structure of the PNP bipolar transistors Q _{0 to} Q ₂ . As shown in FIG. 17A, the diodes D _{0 to} D ₂ typically include an N well 61 formed in the substrate 51, a P ⁺ diffusion region 62 formed in the N well 61, and an N ⁺ diffusion. The area 63 is configured. On the other hand, as shown in FIG. 17B, the PNP bipolar transistors Q _{0 to} Q ₂ include an N well 64 formed in the substrate 51, a P ⁺ diffusion region 65 and an N ⁺ diffusion region formed in the N well 64. 66. As understood from FIGS. 17A and 17B, the diodes D _{0 to} D ₂ and the PNP bipolar transistors Q _{0 to} Q ₂ have substantially the same structure, and it is technical to distinguish them. Note that there is no meaning.

  In addition, as shown in FIG. 16C, an amplifier-type reference voltage generation circuit 41B can be used. In both configurations of FIG. 16B and FIG. 16C, the control voltage VP is expressed by Expression (1).

Further, as shown in FIG. 16D, a voltage conversion circuit 42A having another configuration may be used. In the temperature compensation voltage generation circuit 13 shown in FIG. 16D, a control voltage VP represented by the following equation (2) is generated:
VP = 1 / [(1 + R ₄ / R ₃ ) {V _F + (k _B T / q) · (R ₂ / R ₁ ) ln (N)}].
... (2)

  Next, the write operation of the magnetic random access memory 1 of this embodiment will be described. In the following, the operations of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current temperature compensation circuit 9 will be described. The Y-side constant current source circuit 10, the Y-side current boost circuit 11, and the Y-side The current temperature compensation circuit 12 performs the same operation.

  As shown in FIG. 19, in the initial state, the write enable signal WENX and the boost signal VBSTX are set to the low level. In this state, the PMOS transistor MP1 is turned on and the PMOS transistor MP3 is turned off. Therefore, the potential of the node VBX is approximately equal to Vbst. The capacitor CBX is charged with the power supply voltage Vbst.

Write enable signal WENX and the boost signal VBSTX is pulled up from the Low level to the High level at time _{t 1,} PMOS transistor MP1 is turned off, PMOS transistor MP3 is turned on. At the moment of pull-up of the write enable signal WENX and the boost signal VBSTX, the potential of the node VBX is approximately equal to Vbst, and the potential of the node NLX is lower than that, for example, the ground potential Gnd, so that the capacitor CBX The charge QBX stored in the current flows into the node NLX and a boost current IBX is generated. This boost current IBX continues to flow for several nsec, and charges the parasitic capacitance CLX of the node NLX and the parasitic capacitance of the selected write word line. When the potential of the node VBX becomes equal to the potential of the node NLX and the selected write word line, the flow of the boost current IBX stops. While the boost signal VBSTX is on, the potential of the node VBX decreases by ΔVBST from the original potential Vbst, and conversely, the potential of the node NLX and the selected write word line increases from the ground potential to Vbst−ΔVBST.

When the boost signal VBSTX is pulled down from the high level to the low level at time t ₁ ′, the PMOS transistor MP3 is turned off and the boost current IBX does not flow. On the other hand, since the PMOS transistor MP1 is turned on, charging of the capacitor CBX starts. The potential of the node VBX also rises due to the charging of the capacitor CBX. Since the PMOS transistor MP1 functions as a switch, the time required for charging is 1 ns or less.

When the write enable signal WENX is pulled down to a low level at time t ₁ ″, the X-side constant current source circuit 7 stops generating the constant current ICX, thereby completing the write operation.

  In the magnetic random access memory 1 of the present embodiment, the parasitic capacitance can be rapidly charged by the boost current IBX, so that the dullness of the current waveform is reduced. If the write current is generated by the X-side constant current source circuit 7 alone, the constant current ICX generated by the X-side constant current source circuit 7 is used for charging the parasitic capacitance. I'm going to lose However, the magnetic random access memory 1 of the present embodiment using the X-side current boost circuit 8 can avoid such a problem. If the capacitance of the capacitor CBX is appropriately designed, the current IWX (= ICX + IBX) that actually flows through the cell array is raised in a short time (typically about 2 nsec) as shown in the lowermost stage of FIG. be able to. Therefore, writing is completed at a high speed and an increase in power consumption is prevented.

  In addition, in the magnetic random access memory of the present embodiment, the boost current IBX is controlled depending on the operating temperature in addition to the constant current ICX, so the temperature characteristics of the write current IWX that is actually passed through the memory array 2 are It can be made closer to the ideal temperature dependence. If the boost current IBX is constant without depending on the temperature, the ratio of the boost current IBX to the write current IWX that is actually passed through the memory array 2 changes according to the temperature change. This inhibits the write current IWX from giving an ideal temperature dependency. In the magnetic random access memory according to the present embodiment, for example, the boost current IBX is reduced in accordance with the reduction of the constant current ICX, whereby the write current IWX actually passed through the memory array 2 is reversed with the magnetization of the memory cell. It is possible to follow the temperature change of the current (magnetization reversal current) required for.

  For example, as shown in FIG. 20A, when a conventional memory cell is used, the magnetization reversal current (a) of the half-selected memory cell and the magnetization reversal current (b) of the selected memory cell are both It decreases with increasing operating temperature. However, in the magnetic random access memory according to the present embodiment, which can control the boost current IBX in addition to the constant current ICX depending on the operating temperature, the write current IWX that actually flows through the memory array 2 is set regardless of the operating temperature. The magnetization reversal current (a) of the half-selected memory cell and the magnetization reversal current (b) of the selected memory cell can be set to an appropriate current value. This increases the write current margin and reduces the probability of erroneous writing.

  On the other hand, when a toggle memory cell is used, as shown in FIG. 20B, the magnetization saturation current (a) and the magnetization reversal current (b) of the selected cell both increase the operating temperature. Decreases with. However, in the magnetic random access memory according to the present embodiment, which can control the boost current IBX in addition to the constant current ICX depending on the operating temperature, the write current IWX that actually flows through the memory array 2 is set regardless of the operating temperature. The current value between the magnetization saturation current (a) and the magnetization reversal current (b) of the selected cell can be set. This increases the write current margin and reduces the probability of erroneous writing.

  FIG. 21 is a graph showing the results of measuring the temperature dependence of the write current of the magnetic random access memory of this embodiment. As the temperature rises, the magnetization reversal current of the memory cell decreases. However, as the magnetization reversal current of the memory cell decreases, the write current also decreases accordingly. As a result, the write current is maintained at a substantially intermediate current value that is larger than the magnetization reversal current of the selected memory cell and smaller than the magnetization reversal current of the half-selected memory cell. Therefore, the magnetic random access memory according to the present embodiment can provide a large write current margin even if the operating temperature changes, and can reduce the probability of erroneous writing. An appropriate value for the write current is 1.0 to 2.0 times the current at which the magnetization of the selected cell is reversed. The temperature dependence of the magnetization reversal current of the memory cell is typically in the range of -0.01% to -0.5% / ° C, although it depends on the characteristics of the magnetic material constituting the memory cell. Therefore, the write current is preferably generated so as to have a temperature dependency of −0.01% to −0.5% / ° C.

As shown in FIG. 19, the recharge (boost precharge) after the capacitor CBX is discharged is performed during the write operation. This is suitable for performing the write operation continuously. FIG. 22 is a timing chart showing the operation of the magnetic random access memory according to the present embodiment when continuous writing (burst write) is performed. At time _{t 1} 1 th write operation is started, the boost signal VBXTX write enable signal WENX is pulled up to the High level. When the boost signal VBXTX is pulled down to a low level at time t1 ′, the boost current IBX is cut off and recharging of the capacitor CBX is started. When the write enable signal WENX is pulled down to the low level at time t1 ″, the write current is cut off and the first write operation ends. At time t2, the second write starts, but at time t _2. Since the capacitor CBX has already been charged, the X-side current boost circuit 8 can immediately pass the boost current IBX in the same manner as the third and fourth times started at times t3, t4, and t5. Also in the fifth and fifth write operations, the charging of the capacitor CBX is completed before the write operation, and the boost current IBX can flow immediately.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to depend on the temperature. In this case, the boost power supply voltage Vbst decreases as the temperature increases. For example, the boost power supply voltage Vbst can be generated so as to depend on the temperature by a temperature compensation voltage generation circuit that generates a voltage depending on the temperature as illustrated in FIGS. 16A to 16D.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to coincide with the power supply voltage Vdd. This is suitable for simplifying the circuit configuration and layout configuration and reducing the circuit area and the number of pins.

Second embodiment:
FIG. 23 is a block diagram showing a configuration of a magnetic random access memory 1A according to the second embodiment of the present invention. The magnetic random access memory according to the second embodiment has a configuration similar to that shown in FIG. 13, but instead of the X-side current temperature compensation circuit 9 and the Y-side current temperature compensation circuit 12. The difference is that an X-side current clamper circuit 9A and a Y-side current clamper circuit 12A are provided. The X-side current clamper circuit 9A is for removing excess from the boost current output from the X-side current boost circuit 8 according to the operating temperature of the magnetic random access memory 1A, or adding the shortage to the boost current. It is. Similarly, the Y-side current clamper circuit 12A is for removing excess from the boost current output from the Y-side current boost circuit 11 in accordance with the operating temperature, or adding the shortage to the boost current. The removal of the excess and the addition of the deficiency are performed in response to the operating temperature of the magnetic random access memory 1A. In this embodiment, the temperature compensation voltage generation circuit 13A is configured to generate the three control voltages VP0, VP1, and VP2 in order to remove excess and respond to the operating temperature. . The X-side constant current source circuit 7 and the Y-side constant current source circuit 10 generate a constant current in response to the control voltage VP0. On the other hand, the X-side current clamper circuit 9A and the Y-side current clamper circuit 12A perform removal of excess boost current and addition of shortage in response to the control voltages VP1 and VP2.

  FIG. 24 is a block diagram showing the configuration of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current clamper circuit 9A in the present embodiment; the Y-side constant current source circuit 10 and the Y-side current boost. The configurations of the circuit 11 and the Y-side current clamper circuit 12A are the same as those of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current clamper circuit 9A, respectively.

  The configurations of the X-side constant current source circuit 7 and the X-side current boost circuit 8 are substantially as described in the first embodiment. The X-side constant current source circuit 7 includes a power supply terminal 25 to which a power supply voltage Vdd is supplied, and PMOS transistors MP4 and MP5. The control voltage VP0 is input from the temperature compensation voltage generation circuit 13A to the gate of the PMOS transistor MP4. The control voltage VP0 is generated so as to increase as the operating temperature increases. As shown in FIG. 25B, the constant current ICX generated by the X-side constant current source circuit 7 decreases as the control voltage VP0 increases, that is, as the operating temperature increases.

  Referring back to FIG. 24, the X-side current boost circuit 8 includes PMOS transistors MP1 and MP2, a capacitor CBX, and a power supply terminal 23 to which a boost power supply voltage Vbst is supplied. During boost standby (that is, when the boost signal VBSTX is at a low level), the capacitor CBX is charged with the boost power supply voltage Vbst and charges QBX (= CBX · Vbst) are accumulated. When boosting is permitted (that is, when boost signal VBSTX is pulled up to High level), charge QBX stored in capacitor CBX flows into node NLX and boost current IBX is generated. In this embodiment, unlike the first embodiment, the PMOS transistor MP3 is directly connected to the node VBX. However, it is obvious to those skilled in the art that this does not cause an essential difference in operation. .

  The X-side current clamper circuit 9A includes a current addition circuit 26 and a current subtraction circuit 27. The current subtracting circuit 27 has a function of flowing the excess amount of the boost current IBX, that is, the subtracted current IRX to the ground terminal 29 without flowing to the node NLX. Specifically, the current subtraction circuit 27 includes NMOS transistors MN1 and MN2, an AND element MAN, and a delay element 31. The NMOS transistors MN1 and MN2 are connected in series between the node NLX and the ground terminal 29. The gate of the NMOS transistor MN1 is connected to the output of the AND element MAN. A write enable signal WENX is input to the normal input of the AND element MAN, and a write enable signal WENX is input to the inverted input via the delay element 31. The control voltage VP1 is supplied from the temperature compensation voltage generation circuit 13A to the gate of the NMOS transistor MN2.

  Similarly, the current addition circuit 26 has a function of additionally supplying the shortage of the boost current IBX, that is, the addition current IAX to the node NLX. PMOS transistors MP6 and MP7, a power supply terminal 28 to which a power supply voltage Vdd is supplied, a NAND element MAP, and a delay element 30 are provided. The PMOS transistors MP6 and MP7 are connected in series between the power supply terminal 28 and the node NLX. The gate of the PMOS transistor MP7 is connected to the output of the NAND element MAP. A write enable signal WENX is input to the normal input of the NAND element MAP, and a write enable signal WENX is input to the inverted input via the delay element 30. A control voltage VP2 is supplied from the temperature compensation voltage generation circuit 13A to the gate of the PMOS transistor MP6.

  As shown in FIG. 25A, the control voltage VP1 supplied to the current subtracting circuit 27 increases as the operating temperature increases, like the control voltage VP0 supplied to the X-side constant current source circuit 7. Is generated. The magnitude of the subtraction current IRX flowing from the node NLX to the ground terminal 29 is determined by the size of the NMOS transistor MN2 and the control voltage VP1 supplied to the gate thereof. The subtraction current IRX increases as the control voltage VP1 increases in a range where the control voltage VP1 exceeds the threshold voltage VTN of the NMOS transistor MN2. In other words, the subtraction current IRX increases as the operating temperature increases.

  On the other hand, unlike the control voltages VP0 and VP1, the control voltage VP2 supplied to the current adding circuit 26 is generated so as to decrease as the operating temperature increases. The magnitude of the addition current IAX flowing from the power supply terminal 28 to the node NLX is determined by the size of the PMOS transistor MP6 and the control voltage VP2 supplied to the gate thereof. The addition current IRX increases as the control voltage VP2 decreases in a range where the control voltage VP2 is lower than Vdd−VTP; where Vdd is the power supply voltage applied to the power supply terminal 28, and VTP is the PMOS transistor MP6. Threshold voltage (absolute value thereof). In other words, the addition current IAX decreases as the operating temperature increases.

The boost current IBX ′ that finally flows into the node NLX is obtained by subtracting the subtraction current IRX from the boost current IBX output by the X-side current boost circuit 8 and adding the addition current IBX; that is, IBX ′ = IBX− IRX + IAX. ... (3)
This boost current IBX ′ decreases as the operating temperature increases, as shown in FIG. 25B. As a result, the magnetic random access memory 1A of the present embodiment can bring the temperature characteristics of the write current IWX actually flowing through the memory array 2 closer to ideal temperature dependence.

  In order to reduce the power consumption of the X-side current clamper circuit 9A at room temperature, as shown in FIG. 25A, the control voltage VP1 at room temperature is set to a value close to the threshold voltage VTN of the NMOS transistor MN2. Is effective. As a result, the subtraction current IRX when the operating temperature is not more than room temperature can be made zero, leading to power saving. Similarly, it is effective to set the control voltage VP2 at room temperature to a value close to Vdd-VTP. Thereby, the addition current IRX when the operating temperature is room temperature or higher can be made zero.

  The X-side current clamper circuit 9A is configured to selectively operate only in the initial stage of the write operation in which the X-side current boost circuit 8 outputs the boost current IBX. The continuous operation of the X-side current clamper circuit 9A from the beginning to the end of the write operation means that the addition current IAX or the subtraction current IRX flows even after the boost current IBX stops, and is supplied to the memory array 2. From the viewpoint of controlling the boost current IBX ′, it is not preferable. Specifically, the operation time of the X-side current clamper circuit 9A is determined by the time during which the NMOS transistor MN1 or the PMOS transistor MP7 is on, that is, the delay time Δt of the delay elements 30 and 31. The X-side current clamper circuit 9A allows the addition current IAX or the subtraction current IRX to flow for the delay time T after the write enable signal WENX is activated.

  26A and 26B are timing charts showing the operation of the magnetic random access memory 1A of the present embodiment when the operating temperature is high and low, respectively. 26A and 26B show only the operations of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current clamper circuit 9A, but the Y-side constant current source circuit 10 and the Y-side current are shown. The operations of the boost circuit 11 and the Y-side current clamper circuit 12A are the same as those of the X-side constant current source circuit 7, the X-side current boost circuit 8, and the X-side current clamper circuit 9A, respectively.

  Referring to FIG. 26A, when write enable signal WENX and boost signal BSTX are pulled up to High level at time t1, PMOS transistor MP1 is turned off and PMOS transistor MP3 is turned on in X-side current boost circuit 8. The potential of the node VBX immediately before time t1 is approximately Vbst, and the potential of the node NLX and the selective write word line is a potential lower than this, for example, the ground potential, so that the charge accumulated in the capacitor CBX flows into the node NLX. The boost current IBX is generated.

  On the other hand, when the write enable signal WENX is pulled up, the X-side current clamper circuit 9A is also activated and starts its operation. The operation time is determined by the delay time Δt of the delay elements 30 and 31. After the write enable signal WENX is pulled up, the NMOS transistor MN1 is activated only for the time Δt, whereby the subtraction current IRX flows. The magnitude of the subtraction current IRX is determined according to the control voltage VP1 supplied to the gate of the NMOS transistor MN2. Since the control voltage VP1 increases as the operating temperature increases, the subtraction current IRX also increases as the operating temperature increases. On the other hand, when the operating temperature is high, a sufficiently high control voltage VP2 is supplied to the gate of the PMOS transistor MP6, so that the addition current IAX is almost zero. In other words, the current adding circuit 26 does not operate. Therefore, the boost current IBX ′ that is finally generated decreases as the operating temperature increases. Note that when the operating temperature is high, the boost current IBX ′ that is finally generated is the boost current IBX that is generated by the X-side current boost circuit 8 minus the subtraction current IRX.

  When the boost signal VBSTX is pulled down to a low level at time t1 ', the PMOS transistor MP3 of the X-side current boost circuit 8 is turned off and the boost current IBX does not flow. On the other hand, since the PMOS transistor MP1 is turned on, charging of the capacitor CBX is started. By charging the capacitor CBX, the potential of the node VBX rises. Since the PMOS transistor MP1 functions as a switch, the time required for charging is 1 ns or less.

  According to such an operation, both the constant current ICX and the boost current IBX ′ can be reduced as the operating temperature increases. Therefore, in the present embodiment, the write current IWX (= ICX + IBX ′) that is actually passed through the memory array 2 can be generated so as to have an ideal temperature dependence adapted to the temperature characteristics of the memory cell.

  On the other hand, the same applies when the operating temperature is low. Referring to FIG. 26B, when write enable signal WENX and boost signal BSTX are pulled up to High level at time t1, PMOS transistor MP1 is turned off and PMOS transistor MP3 is turned on in X-side current boost circuit 8. The potential of the node VBX immediately before time t1 is approximately Vbst, and the potential of the node NLX and the selective write word line is a potential lower than this, for example, the ground potential, so that the charge accumulated in the capacitor CBX flows into the node NLX. The boost current IBX is generated.

  On the other hand, when the write enable signal WENX is pulled up, the X-side current clamper circuit 9A is also activated and starts its operation. The operation time is determined by the delay time Δt of the delay elements 30 and 31. After the write enable signal WENX is pulled up, the PMOS transistor MP7 is activated only during the time Δt, whereby the addition current IAX flows. The magnitude of the addition current IAX is determined according to the control voltage VP2 supplied to the gate of the PMOS transistor MP6. Since the control voltage VP2 increases as the operating temperature decreases, the added current IAX also increases as the operating temperature decreases. On the other hand, when the operating temperature is low, a sufficiently low control voltage VP1 is supplied to the gate of the NMOS transistor MN2, so that the subtraction current IRX is almost zero. In other words, the current subtraction circuit 27 does not operate. Therefore, the boost current IBX ′ that is finally generated increases as the operating temperature decreases. It should be noted that when the operating temperature is low, the boost current IBX 'that is finally generated is the sum of the boost current IBX generated by the X-side current boost circuit 8 and the addition current IAX.

  When the boost signal VBSTX is pulled down to a low level at time t1 ', the PMOS transistor MP3 of the X-side current boost circuit 8 is turned off and the boost current IBX does not flow. On the other hand, since the PMOS transistor MP1 is turned on, charging of the capacitor CBX is started. By charging the capacitor CBX, the potential of the node VBX rises. Since the PMOS transistor MP1 functions as a switch, the time required for charging is 1 ns or less.

  According to such an operation, both the constant current ICX and the boost current IBX ′ can be increased as the operating temperature decreases. Therefore, in the present embodiment, the write current IWX (= ICX + IBX ′) that is actually passed through the memory array 2 can be generated so as to have an ideal temperature dependence adapted to the temperature characteristics of the memory cell.

Another advantage of the magnetic random access memory 1A of this embodiment is that the rise time of the write current (that is, the word line current and the bit line current) can be shortened. Shortening the rise time of the word line current and bit line current is important for shortening the write cycle time. FIG. 27 shows the distribution of operation time in one write cycle. In the magnetic random access memory, it is necessary to sequentially flow the word line current IWX and the bit line current IBX while the write enable signal WE is activated. For example, in order to satisfy the specification that the write operation is performed at 100 MHz, the write cycle (that is, the time during which the write enable signal WE is activated) needs to be 10 ns or less. One write cycle consists of word line current standby time T ₁ , word line current rise time T ₂ , word line current stabilization time T ₃ , bit line current rise time T ₄ , word line current / bit line current sustain time T _5. , And a bit line current maintaining time T ₆ and a bit line current falling time T ₇ . About ₁ ns is sufficient for the times T ₁ , T ₃ , T ₆ , and T ₇ , and about 2 ns is required for the time T ₅ . Therefore, in order to suppress the sum of the times T _{1 to} T ₇ to 10 ns or less, it is necessary to suppress the rise time of the word line current and the bit line current to 2 ns or less.

In the magnetic random access memory 1 of the first embodiment, two PMOS transistors are connected in series between the capacitor CBX and the node NLX, whereas in the magnetic random access memory 1A of the second embodiment, the capacitor Only one PMOS transistor is connected between CBX and node NLX. This effectively shortens the rise times T ₂ and T ₄ of the write current.

  FIG. 28 is a graph showing the simulation result of the rise time of the write current in the magnetic random access memory 1A of the present embodiment. The simulation is performed under the condition that the memory array 2 is a large-scale array having a parasitic resistance of 100Ω and a parasitic capacitance of 10 pF. The write current value is selected from 2.5 mA, 5.0 mA, and 10 mA. As the small array to be written, the one closest to the constant current source used for writing and the one far from the constant current source are selected. In any case, the rise time of the write current is 2 ns or less, and when the write current is 2.5 mA or 5.0 mA, the rise time of 1 ns or less can be achieved. This means that high-speed writing of 100 MHz or more can be realized.

  Further, as in the first embodiment, since the capacitor CBX is recharged during the write operation, it will be understood by those skilled in the art that continuous writing can be easily achieved in this embodiment.

  Also in the present embodiment, the boost power supply voltage Vbst is preferably generated independently of the other power supply voltage Vdd. Such a configuration is suitable in order to suppress the influence of fluctuations in the power supply voltage Vdd that can occur particularly during writing on the amount of charge accumulated in the capacitor CBX. In this case, the boost power supply voltage Vbst can be generated depending on the temperature. In this case, the boost power supply voltage Vbst decreases as the temperature increases. For example, the boost power supply voltage Vbst can be generated so as to depend on the temperature by a temperature compensation voltage generation circuit that generates a voltage depending on the temperature as illustrated in FIGS. 16A to 16D.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to coincide with the power supply voltage Vdd. This is suitable for simplifying the circuit configuration and layout configuration and reducing the circuit area and the number of pins.

Third embodiment:
In the magnetic random access memory 1A of the second embodiment shown in FIG. 24, when the write enable signal WENX and the boost signal VBSTX are pulled up at the same timing at the start of the write operation, the X-side current boost The functions of the PMOS transistor MP3 of the circuit 8 and the PMOS transistor MP5 of the X-side constant current source circuit 7 can be realized by one PMOS transistor.

  More specifically, in the magnetic random access memory 1B of the third embodiment, as shown in FIG. 29, the functions of the PMOS transistors MP3 and MP5 in FIG. 24 are realized by the PMOS transistor MP8. Accordingly, the PMOS transistors MP3 and MP5 are removed from the X-side constant current source circuit 7A and the X-side current boost circuit 8A, respectively. The outputs of the X-side constant current source circuit 7A and the X-side current boost circuit 8A are connected to the node VCX. In other words, the capacitor CBX and the PMOS transistor MP4 are directly connected to the node VCX. In addition, the current addition circuit 26 and the current subtraction circuit 27 of the X-side current clamper circuit 9A are also connected to the node VCX. The node VCX is connected to the node NLX via the PMOS transistor MP8. Note that the node NLX is a node connected to the write word line via the X-side selector 3. The Y-side constant current source circuit that supplies the write current IWY to the bit line and the Y-side current boost circuit are similarly configured.

  FIG. 30 is a timing chart showing the operation of the magnetic random access memory 1B of the present embodiment. The timing chart of FIG. 30 shows the operation of the magnetic random access memory 1B when the operating temperature is high (that is, when only the current subtracting circuit 27 operates). It is the same except that only the circuit 26 operates. It should be noted that the Y-side constant current source circuit and the Y-side current boost circuit operate similarly.

  Referring to FIG. 30, when write enable signal WENX and boost signal BSTX are pulled up to high level at time t1, PMOS transistor MP1 is turned off and PMOS transistor MP8 is turned on in X-side current boost circuit 8. The potential of the node VBX immediately before time t1 is approximately Vbst, and the potential of the node NLX and the selective write word line is a potential lower than this, for example, the ground potential, so that the charge accumulated in the capacitor CBX flows into the node NLX. The boost current IBX is generated.

  On the other hand, when the write enable signal WENX is pulled up, the X-side current clamper circuit 9A is also activated and starts its operation. The operation time is determined by the delay time Δt of the delay elements 30 and 31. After the write enable signal WENX is pulled up, the NMOS transistor MN1 is activated only for the time Δt, whereby the subtraction current IRX flows. The magnitude of the subtraction current IRX is determined according to the control voltage VP1 supplied to the gate of the NMOS transistor MN2. Since the control voltage VP1 increases as the operating temperature increases, the subtraction current IRX also increases as the operating temperature increases. Therefore, the boost current IBX ′ that is finally generated decreases as the operating temperature increases.

  When the write enable signal WENX is pulled down to a low level at time t1 ', the PMOS transistor MP8 is turned off and the write current IWX does not flow. On the other hand, since the PMOS transistor MP1 is turned on, charging of the capacitor CBX is started. By charging the capacitor CBX, the potential of the node VBX rises. Since the PMOS transistor MP1 functions as a switch, the time required for charging is 1 ns or less. In FIG. 30, the time at which charging is completed is indicated by the symbol “t1” ”. FIG. 30 shows an operation in the case where the write enable signal WENX and the boost signal BSTX are simultaneously pulled down to the low level, but the boost signal BSTX is pulled down before the write enable signal WENX in time. Note that it is also possible.

  According to such an operation, both the constant current ICX and the boost current IBX ′ can be reduced as the operating temperature increases. Therefore, in the present embodiment, the write current IWX (= ICX + IBX ′) that is actually passed through the memory array 2 can be generated so as to have an ideal temperature dependence adapted to the temperature characteristics of the memory cell.

FIG. 31 is a timing chart showing the operation of the magnetic random access memory according to the present embodiment when continuous writing (burst write) is performed. It should be noted that the recharge (boost precharge) of the capacitor CBX is performed after the write operation. At time _{t 1} 1 th write operation is started, the boost signal VBXTX write enable signal WENX is pulled up to the High level. When the boost signal VBXTX and the write enable signal WENX are pulled down to a low level at time t1 ′, the write current IWX is cut off and recharging of the capacitor CBX is started. At time t2 after time t1 ′, the second writing is started. It should be noted that the time t2 of the _second writing must be after the charging of the capacitor CBX is completed. This means that a certain waiting time needs to be prepared after the write operation is completed. This is not suitable for performing continuous writing in a short time.

  In order to eliminate the waiting time after the write operation is completed, it is preferable to prepare two write systems having the same configuration for each of the word lines and the bit lines as shown in FIG. . Specifically, the magnetic random access memory 1B of FIG. 32 includes X-side constant current source circuits 7A and 7B, X-side current boost circuits 8A and 8B, X-side current clamper circuits 9A and 9B, and a Y-side constant current source. Circuits 10A and 10B, Y-side current boost circuits 11A and 11B, and Y-side current clamper circuits 12A and 12B are provided. The X-side constant current source circuit 7A, the X-side current boost circuit 8A, and the X-side current clamper circuit 9A constitute a first word line write system, and the X-side constant current source circuit 7B, the X-side current boost circuit 8B, The X-side current clamper circuit 9B constitutes a second write system. Similarly, the Y-side constant current source circuit 10A, the Y-side current boost circuit 11A, and the Y-side current clamper circuit 12A constitute a first write system, and the Y-side constant current source circuit 10B and the Y-side current boost circuit 11B. , And the Y-side current clamper circuit 12B constitute a second write system.

  A control signal is also prepared for each of the first writing system and the second writing system. A write enable signal WENX1 and a boost signal VBSTX1 are supplied to the X-side constant current source circuit 7A, the X-side current boost circuit 8A, and the X-side current clamper circuit 9A, and the X-side constant current source circuit 7B and the X-side current boost circuit are supplied. The write enable signal WENX2 and the boost signal VBSTX2 are supplied to the 8B and X side current clamper circuit 9B. Similarly, a write enable signal WENY1 and a boost signal VBSTY1 are supplied to the Y side constant current source circuit 10A, the Y side current boost circuit 11A, and the Y side current clamper circuit 12A, and the Y side constant current source circuit 10B, Y side A write enable signal WENY2 and a boost signal VBSTY2 are supplied to the current boost circuit 11B and the Y-side current clamper circuit 12B.

  FIG. 33 is a timing chart showing the operation of the magnetic random access memory 1B shown in FIG. FIG. 33 illustrates the operations of the X-side constant current source circuits 7A and 7B, the X-side current boost circuits 8A and 8B, and the X-side current clamper circuits 9A and 9B. The operations of the Y-side current boost circuits 11A and 11B and the Y-side current clamper circuits 12A and 12B are the same.

  At time t1 when the first write operation is started, the boost signal VBSTX1 and the write enable signal WENX1 are pulled up to a high level, and the boost signal VBSTX2 and the write enable signal WENX2 are pulled down to a low level. As a result, the constant current ICX1 and the boost current IBX1 are generated by the X-side constant current source circuit 7A and the X-side current boost circuit 8A, respectively, and the write current IWX1 that flows to the memory array 2 is generated from these currents. Since the X-side current clamper circuit 9A adds the addition current IAX to the boost current IBX1 or removes the subtraction current IRX from the boost current IBX1, the write current IWX1 has an ideal temperature dependency that matches the temperature characteristics of the memory cell. Generated to have.

  At time t1 'when the second write operation is started, the boost signal VBSTX2 and the write enable signal WENX2 are pulled up to a high level, and the boost signal VBSTX1 and the write enable signal WENX1 are pulled down to a low level. As a result, the constant current ICX2 and the boost current IBX2 are generated by the X side constant current source circuit 7B and the X side current boost circuit 8B, respectively, and the write current IWX2 that flows to the memory array 2 is generated from these currents. Since the X-side current clamper circuit 9B adds the addition current IAX to the boost current IBX2 or removes the subtraction current IRX from the boost current IBX2, the write current IWX2 has an ideal temperature dependence that matches the temperature characteristics of the memory cell. Generated to have. At time t1 ′, the capacitor CBX of the X-side current boost circuit 8A is not fully charged, but the capacitor CBX of the X-side current boost circuit 8B is used to generate the boost current IBX2, so the write current IWX2 is shortened. There is no problem in starting up in time.

  Subsequently, at time t2 when the third write operation is started, the boost signal VBSTX1 and the write enable signal WENX1 are pulled up to a high level, and the boost signal VBSTX2 and the write enable signal WENX2 are pulled down to a low level. At time t2, the X-side current boost circuit 8A is used to generate a boost current. At this time, charging of the capacitor CBX of the X-side current boost circuit 8A is completed, so that the boost current is generated immediately. Can do.

  Similarly, at times t3, t3 ', t4, t4', t5, and t5 ', it is possible to generate a write current having an ideal temperature dependency suitable for the temperature characteristics of the memory cell with a short rise time.

  Also in the present embodiment, the boost power supply voltage Vbst is preferably generated independently of the other power supply voltage Vdd. Such a configuration is suitable in order to suppress the influence of fluctuations in the power supply voltage Vdd that can occur particularly during writing on the amount of charge accumulated in the capacitor CBX. In this case, the boost power supply voltage Vbst can be generated depending on the temperature. In this case, the boost power supply voltage Vbst decreases as the temperature increases. For example, the boost power supply voltage Vbst can be generated so as to depend on the temperature by a temperature compensation voltage generation circuit that generates a voltage depending on the temperature as illustrated in FIGS. 16A to 16D.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to coincide with the power supply voltage Vdd. This is suitable for simplifying the circuit configuration and layout configuration and reducing the circuit area and the number of pins.

Fourth embodiment:
FIG. 34 is a circuit diagram showing a configuration of the magnetic random access memory 1C of the fourth embodiment. The configuration of the magnetic random access memory 1C of the fourth embodiment is substantially the same as the configuration of the magnetic random access memory 1B of FIG. 29, but in this embodiment, the X-side current clamper circuit 9C is selected as a write target. The subtracting current IRX is controlled according to the position of the memory cell. This is intended to keep the write current that actually flows at the position of the selected memory cell constant by adjusting the boost current. When supplying a write current from a write current source to a nearby memory cell, the X-side current clamper circuit 9C increases the subtraction current IRX and relatively decreases the boost current. Conversely, when supplying a write current to a memory cell far from the write current source, the subtraction current IRX is decreased and the boost current is relatively increased.

  Specifically, the X-side current clamper circuit 9C includes a current addition circuit 26 that generates an addition current IAX and a current subtraction circuit 27A that generates a subtraction current IRX. The current addition circuit 26 receives the control voltage VP2 from the temperature compensation voltage generation circuit 13A, and generates an addition current IAX in response to the control voltage VP2. The configuration and operation of the current adding circuit 26 are as described above, and details thereof will not be described.

  The current subtracting circuit 27A includes NMOS transistors MNR11 to MNR1n, MNR21 to MNR2n, NAND gates MA11 to MA1n, and delay elements 31-1 to 31-n. Between the node VCX and the ground terminal 29, a MOS transistor group composed of two NMOS transistors, each connected in series, is connected in parallel. More specifically, the NMOS transistor MNR1k and the NMOS transistor MNR2k are connected in series between the node VCX and the ground terminal 29, where k is an arbitrary natural number equal to or less than n.

  The NMOS transistors MNR21 to MNR2n are used to generate a current corresponding to the operating temperature. The control voltage VP1 is supplied from the temperature compensation voltage generation circuit 13A to the gates of the NMOS transistors MNR21 to MNR2n, and the current flowing through the NMOS transistors MNR21 to MNR2n is controlled according to the control voltage VP1.

  On the other hand, the NMOS transistors MNR11 to MNR1n have a role of controlling the number of transistors actually contributing to the generation of the subtraction current IRX among the NMOS transistors MNR21 to MNR2n according to the position of the selected memory cell. Specifically, the gates of the NMOS transistors MNR11 to MNR1n are connected to the outputs of the AND elements MA11 to MA1n, respectively. Each of the AND elements MA11 to MA1n includes two normal inputs and one inverting input. The write enable signal WENX is input to the first normal rotation inputs of the AND elements MA11 to MA1n, and the write enable signal WENX is input to the inverting inputs via the delay elements 31-1 to 31-n. Further, selection signals SEL1 to SELn are input to the second normal rotation inputs of the AND elements MA11 to MA1n, respectively. The selection signals SEL1 to SELn are a set of signals indicating the position of the selected memory cell. In one embodiment, as the selection signals SEL1 to SELn, inverted signals of the address signals X1 to Xn can be used, respectively. In this case, as the selected memory cell is farther from the write current source, more selection signals among the selection signals SEL1 to SELn are set to the high level. Thereby, as the selected memory cell is farther from the write current source, more of the NMOS transistors MNR21 to MNR2n actually contribute to the generation of the subtraction current IRX.

  The Y-side constant current source circuit that supplies the write current IWY to the bit line and the Y-side current boost circuit are similarly configured.

  According to such a configuration, the subtraction current IRX, that is, the boost current is controlled according to the position of the selected memory cell, and the write current that actually flows at the position of the selected memory cell can be kept constant.

  Also in the present embodiment, the boost power supply voltage Vbst is preferably generated independently of the other power supply voltage Vdd. Such a configuration is suitable in order to suppress the influence of fluctuations in the power supply voltage Vdd that can occur particularly during writing on the amount of charge accumulated in the capacitor CBX. In this case, the boost power supply voltage Vbst can be generated depending on the temperature. In this case, the boost power supply voltage Vbst decreases as the temperature increases. For example, the boost power supply voltage Vbst can be generated so as to depend on the temperature by a temperature compensation voltage generation circuit that generates a voltage depending on the temperature as illustrated in FIGS. 16A to 16D.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to coincide with the power supply voltage Vdd. This is suitable for simplifying the circuit configuration and layout configuration and reducing the circuit area and the number of pins.

Fifth embodiment:
FIG. 35 is a circuit diagram showing a configuration of a magnetic random access memory 1D according to the fifth embodiment of the present invention. The magnetic random access memory 1D according to the present embodiment is substantially the same as the configuration of the magnetic random access memory 1B of FIG. 29, but in this embodiment, the configuration of the X-side current boost circuit 8C is changed.

  More specifically, in the present embodiment, the X-side current boost circuit 8C has a PMOS transistor MP1, an NMOS transistor MN3, a capacitor CBX, an inverter 21, a ground terminal 22, and a power supply terminal 23 to which a boost power supply voltage Vbst is supplied. It is configured with. The PMOS transistor MP1 is connected between the power supply terminal 23 and the node VBX, and the NMOS transistor MN3 is connected between the node VBX and the ground terminal 22. The boost signal VBSTX is commonly supplied to the gates of the PMOS transistor MP1 and the NMOS transistor MN3 via the inverter 21. Capacitor CBX is connected between node VBX and node VCX. The node VCX is a node to which the output of the X-side current boost circuit 8C is connected, and is connected to the node NLX through the PMOS transistor MP8.

  FIG. 36 is a timing chart showing the operation of the magnetic random access memory 1D of this embodiment, particularly the operation of the X-side current boost circuit 8C. During boost standby (ie, when the boost signal VBSTX is at a low level), both the PMOS transistor MP1 of the X-side current boost circuit 8C and the PMOS transistor MP8 that controls on / off of the write current IWX are turned off, and the NMOS transistor MN1 is turned on. Turned on. As a result, the potential of the node VCX becomes Vdd, and the potential of the node VBX becomes the ground potential. Therefore, the charge QBX (= CBX · Vdd) is accumulated in the capacitor CBX.

  When a write operation is started at time t1 and the write enable signal WENX and the boost signal VBSTX are pulled up to a high level, the PMOS transistor MP1 is turned on and the NMOS transistor MN3 is turned off. As a result, the potential of the node VBX suddenly rises to Vbst. As a result, the charge QBX accumulated in the capacitor CBX by coupling flows into the node VCX via the node VCX and the PMOS transistor MP8, and the boost current IBX is generated. Further, the addition current IAX flows into the node VCX or the subtraction current IRX flows out of the node VCX, so that the boost current IBX is adjusted according to the temperature, thereby generating the boost current IBX '. With this boost current IBX ', the parasitic capacitance CLX of the node NLX and the parasitic capacitance of the memory array 2 are charged. This charging is typically completed in a time of 1 nsec or less. The potential of the node VCX rises rapidly when the potential of the node VBX suddenly rises to Vbst, and then settles to the potential Vbst−ΔVBSTX. On the other hand, when the boost current IBX ′ flows, the potential of the node VLX also gradually approaches Vbst−ΔVBSTX.

  When the boost signal VBSTX is pulled down to a low level at time t1 ', the PMOS transistor MP1 of the X-side current boost circuit 8C is turned off and the NMOS transistor MN3 is turned on. As a result, the potential of the node VBX returns to the ground potential, and therefore the flow of the boost current IBX stops. Thereafter, only the constant current ICX flows as the write current IWL. As described above, the constant current ICX is a current having temperature dependence corresponding to the temperature characteristic of the memory cell.

  A feature of the magnetic random access memory according to the present embodiment is that the capacitance of the capacitor CBX can be reduced. In the current boost circuits of the first to fourth embodiments, the potential of one end of the capacitor CBX is fixed to the ground potential, and only a part of the charge stored in the capacitor CBX is used for generating the boost current IBX. . On the other hand, in the X-side current boost circuit 8C of the present embodiment, the potential at one end of the capacitor CBX can be raised, so that much of the charge accumulated in the capacitor CBX can be released to the node VCX. Therefore, the capacity required for the capacitor CBX is small.

  FIG. 37 is a graph showing the results of a simulation performed to confirm this effect. In the magnetic random access memory assumed to have a certain parasitic capacitance, when the current boost circuit of FIG. 10 is used, the capacitance of the capacitor CBX needs to be 30 pF or more. On the other hand, FIG. 37 is a graph showing the waveform of the write current when the X-side current boost circuit 8C according to the present embodiment is used in the same magnetic random access memory. When the X-side current boost circuit 8C according to the present embodiment is used, the capacitance of the capacitor CBX is 8 pF or more. In other words, in this embodiment, the occupied area of the capacitor CBX used for current boost can be reduced to about 25%. This makes it possible to realize a magnetic random access memory with a high memory cell occupation rate.

  Also in the present embodiment, the boost power supply voltage Vbst is preferably generated independently of the other power supply voltage Vdd. Such a configuration is suitable in order to suppress the influence of fluctuations in the power supply voltage Vdd that can occur particularly during writing on the amount of charge accumulated in the capacitor CBX. In this case, the boost power supply voltage Vbst can be generated depending on the temperature. In this case, the boost power supply voltage Vbst decreases as the temperature increases. For example, the boost power supply voltage Vbst can be generated so as to depend on the temperature by a temperature compensation voltage generation circuit that generates a voltage depending on the temperature as illustrated in FIGS. 16A to 16D.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to coincide with the power supply voltage Vdd. This is suitable for simplifying the circuit configuration and layout configuration and reducing the circuit area and the number of pins.

Sixth embodiment:
FIG. 38 is a circuit diagram showing a configuration of a write circuit of the magnetic random access memory 1E of the sixth embodiment. In this embodiment, the X-side current boost circuit is configured to have a function of controlling the amount of charge accumulated in the capacitive element depending on the operating temperature.

  More specifically, the magnetic random access memory 1E of this embodiment includes an X-side constant current source circuit 7A, an X-side current boost circuit 8D, and a PMOS transistor MP8. The X-side constant current source circuit 7A includes a PMOS transistor MP4 connected between the node VCX and the power supply terminal 25 to which the power supply voltage Vdd is supplied. A control voltage VP is supplied from the temperature compensation voltage generation circuit 13 to the gate of the PMOS transistor MP4. The control voltage VP is generated so as to increase as the operating temperature increases. As a result, the constant current ICX generated by the X-side constant current source circuit 7A decreases as the operating temperature increases.

  The X-side current boost circuit 8D is configured to output a boost current IBX to the node VCX in response to activation of the boost signal VBSTX. Specifically, the X-side current boost circuit 8D is supplied with PMOS transistors MP1 and MP9, a transmission gate MC1, an inverter 21, a power supply terminal 23A to which a power supply voltage Vdd is supplied, and a boost power supply voltage Vbst. Power supply terminal 23B. The PMOS transistor MP1 is connected between the node VBX and the power supply terminal 23A, and a boost signal VBSTX is supplied to its gate via the inverter 21. The node VBX is connected to the temperature compensation voltage generation circuit 13 through the transmission gate MC1. The transmission gate MC1 is controlled according to the boost signal VBSTX, and the control voltage VP is supplied to the node VBX from the temperature compensation voltage generation circuit 13 when the boost signal VBSTX is at the low level. When the boost signal VBSTX is at a high level, the node VBX is connected to the power supply terminal 23A, and the power supply voltage Vdd is supplied to the node VBX. The power supply voltage Vdd is higher than the control voltage VP. The PMOS transistor MP9 has a source connected to the power supply terminal 23B and a drain connected to the node VCX. The gate of the PMOS transistor MP9 is connected to the node VBX. The boost current IBX is output from the source of the PMOS transistor MP9 to the node VCX.

In the present embodiment, the charge for causing the boost current IBX to flow is accumulated in the parasitic capacitance CBX between the gate and the drain of the PMOS transistor MP9. It should be noted that the amount of charge accumulated in the parasitic capacitance CBX has a temperature dependency, which gives the boost current IBX a temperature dependency. When the boost signal VBSTX is at the low level, the potential of the gate of the PMOS transistor MP9 is VP. Therefore, a charge proportional to Vbst−VP is accumulated between the gate and the drain of the PMOS transistor MP9. That is, the charge amount QBX accumulated in the parasitic capacitance CBX between the gate and drain of the PMOS transistor MP9 is
QBX = CBX · (Vbst−VP),
It is represented by Since the control voltage VP increases as the operating temperature increases, the charge amount QBX decreases as the operating temperature increases. Since the boost current IBX increases as the charge amount QBX increases, as a result, the boost current IBX also decreases as the operating temperature increases.

  The PMOS transistor MP8 has a function of permitting or prohibiting the output of the write current IWX that is actually supplied to the memory array 2. A write enable signal WENX is supplied to the gate of the PMOS transistor MP8 via the inverter 24. When the write enable signal WENX is activated, output of the write current IWX to the memory array 2 is started.

  The Y-side constant current source circuit that supplies the write current IWY to the bit line and the Y-side current boost circuit are similarly configured.

  FIG. 39 is a timing chart showing the operation of the magnetic random access memory 1E of this embodiment. FIG. 39 illustrates only the operations of the X-side constant current source circuit 7A and the X-side current boost circuit 8D, but the operations of the Y-side constant current source circuit and the Y-side current boost circuit are the same.

  In boost standby, the boost signal VBSTX is set to a low level, and the charge QBX (= CBX · (Vbst−VP)) is accumulated in the parasitic capacitance CBX of the PMOS transistor MP9.

  When the write operation is started at time t1, when the write enable signal WENX and the boost signal VBSTX are pulled up to a high level, the PMOS transistor MP1 is turned on and the transmission gate MC1 is turned off. As a result, the potential of the node VBX rises rapidly to Vdd. As a result, the charge QBX accumulated in the parasitic capacitance CBX of the PMOS transistor MP9 flows out to the node VCX by coupling, and a boost current IBX is generated. With this boost current, the parasitic capacitance CLX of the node NLX and the parasitic capacitance of the memory array 2 are charged. When the potential of the node VCX and the potential of the node NLX become equal, the flow of the boost current IBX stops. In the second graph from the bottom in FIG. 39, the waveform of the boost current IBX is illustrated. While the boost signal VBSTX is maintained at the high level, the potential of the node VCX decreases from ΔVbst by ΔVBST. On the other hand, the potential of the node NLX rises from the ground potential to Vbst−ΔVBST.

  If the size of the PMOS transistor MP9 of the X-side current boost circuit 8D is appropriately designed, the size of the parasitic capacitance CBX becomes an appropriate value, and the write current IWX (= ICB + IBX) actually flowing through the memory array 2 is reduced for a short time. Can be launched. This makes it possible to reduce the current pulse width of the write current IWX and reduce the power consumption.

  In addition, since the boost current IBX has temperature dependence, the write current IWX can be generated so as to have ideal temperature dependence adapted to the temperature characteristics of the memory cell.

  Also in the present embodiment, the boost power supply voltage Vbst can be generated so as to depend on the temperature. In this case, the boost power supply voltage Vbst decreases as the temperature increases. For example, the boost power supply voltage Vbst can be generated so as to depend on the temperature by a temperature compensation voltage generation circuit that generates a voltage depending on the temperature as illustrated in FIGS. 16A to 16D.

  In the present embodiment, the boost power supply voltage Vbst can be generated so as to coincide with the power supply voltage Vdd. This is suitable for simplifying the circuit configuration and layout configuration and reducing the circuit area and the number of pins.

  It is obvious that the present invention is not limited to the above-described embodiments, and can be appropriately changed within the scope of the technical idea of the present invention. For example, the current boost circuit is preferably arranged in the vicinity of the constant current source in terms of layout, but may be arranged in the vicinity of the memory array and in the memory array. It is clear that the arrangement of each circuit block differs from the attached drawings without affecting the essence of the present invention.

FIG. 1 is a cross-sectional view showing a configuration of a conventional memory cell. FIG. 2 is a cross-sectional view showing a configuration of a toggle type memory cell. FIG. 3 is a plan view showing an example of the configuration of a conventional magnetic random access memory. FIG. 4 is a cross-sectional view showing an example of the configuration of a conventional magnetic random access memory. FIG. 5A is a timing chart showing a write operation to a conventional memory cell. FIG. 5B is a conceptual diagram illustrating a write operation to a conventional memory cell. FIG. 6A is a timing chart showing a write operation to a toggle memory cell. FIG. 6B is a timing chart showing a write operation to the toggle type memory cell. FIG. 7A is a graph showing an operation region of a conventional memory cell. FIG. 7B is a graph showing an operation region of the toggle memory cell. FIG. 8 is a block diagram illustrating an example of the configuration of a large-scale memory array. FIG. 9 is a block diagram showing an example of a configuration of a portion corresponding to one row of small arrays in the large-scale memory array. FIG. 10 is a block diagram showing a configuration of a write circuit of a conventional magnetic random access memory. FIG. 11 is a timing chart showing the operation of a conventional magnetic random access memory. FIG. 12A is a graph showing temperature characteristics of a conventional memory cell. FIG. 12B is a graph showing temperature characteristics of the toggle memory cell. FIG. 13 is a block diagram showing the configuration of the magnetic random access memory according to the first embodiment of the present invention. FIG. 14 is a circuit diagram showing a configuration of a write circuit of the magnetic random access memory according to the first embodiment. FIG. 15 is a cross-sectional view illustrating an example of the configuration of the capacitor CBX. FIG. 16A is a circuit diagram illustrating an example of a configuration of a temperature compensation voltage generation circuit. FIG. 16B is a circuit diagram illustrating another example of the configuration of the temperature compensation voltage generation circuit. FIG. 16C is a circuit diagram illustrating still another example of the configuration of the temperature compensation voltage generation circuit. FIG. 16D is a circuit diagram illustrating still another example of the configuration of the temperature compensation voltage generation circuit. FIG. 17A is a cross-sectional view illustrating an example of the structure of a diode. FIG. 17B is a cross-sectional view showing an example of the structure of the PNP transistor. FIG. 18A is a graph showing the temperature characteristics of the control voltage in the first embodiment. FIG. 18B is a graph showing temperature characteristics of the constant current ICX and the boost current IBX in the first embodiment. FIG. 19 is a timing chart showing the operation of the magnetic random access memory according to the first embodiment. FIG. 20A is a graph showing temperature characteristics of the magnetic random access memory according to the first embodiment when a conventional memory cell is used. FIG. 20B is a graph showing temperature characteristics of the magnetic random access memory according to the first embodiment when the toggle memory cell is used. FIG. 21 is a graph showing the results of measuring the temperature dependence of the write current of the magnetic random access memory according to the first embodiment. FIG. 22 is a timing chart showing the operation of the magnetic random access memory according to the first embodiment when the continuous write operation is performed. FIG. 23 is a block diagram showing the configuration of the magnetic random access memory according to the second embodiment. FIG. 24 is a circuit diagram showing a configuration of a write circuit of the magnetic random access memory according to the second embodiment. FIG. 25A is a graph showing temperature characteristics of the control voltages VP1 and VP2. FIG. 25B is a graph showing temperature characteristics of the addition current IAX, the subtraction current IRX, the boost current IBX, and the constant current ICX. FIG. 26A is a timing chart showing the operation of the magnetic random access memory according to the second embodiment when the operation temperature is high. FIG. 26B is a timing chart showing the operation of the magnetic random access memory according to the second embodiment when the operation temperature is low. FIG. 27 is a graph showing operation time distribution in the write cycle. FIG. 28 is a graph showing the simulation result of the rise time of the write current in the magnetic random access memory of the second embodiment. FIG. 29 is a circuit diagram showing a configuration of a write circuit of the magnetic random access memory according to the third embodiment. FIG. 30 is a timing chart showing the operation of the magnetic random access memory according to the third embodiment. FIG. 31 is a timing chart showing the operation of the magnetic random access memory according to the third embodiment when the continuous write operation is performed. FIG. 32 is a block diagram showing a configuration of a magnetic random access memory suitable for the continuous write operation. FIG. 33 is a timing chart showing the operation of the magnetic random access memory of FIG. FIG. 34 is a circuit diagram showing a configuration of a write circuit of the magnetic random access memory according to the fourth embodiment. FIG. 35 is a circuit diagram showing a configuration of a write circuit of the magnetic random access memory according to the fifth embodiment. FIG. 36 is a timing chart showing the operation of the magnetic random access memory according to the fifth embodiment. FIG. 37 is a graph showing the waveform of the write current when the X-side current boost circuit according to the fifth embodiment is used. FIG. 38 is a circuit diagram showing a configuration of the magnetic random access memory according to the sixth embodiment. FIG. 39 is a timing chart showing the operation of the magnetic random access memory according to the sixth embodiment.

Explanation of symbols

1, 1A, 1B, 1C, 1D, 1E: Magnetic random access memory 2: Memory array 3: X side selector 4: Y side selector 5: X side current termination circuit 6: Y side current termination circuit 7, 7A, 7B: X side constant current source circuit 8, 8A, 8B, 8C, 8D: X side current boost circuit 9: X side current temperature compensation circuit 9A, 9B, 9C: X side current clamper circuit 10, 10A, 10B: Y side constant current Source circuit 11, 11A, 11B: Y-side current boost circuit 12: Y-side current temperature compensation circuit 12A, 12B: Y-side current clamper circuit 13, 13A: Temperature compensation voltage generation circuit 14: Sense amplifier 21, 24: Inverter 22: Ground terminal 23, 23A, 23B: Power supply terminal 25: Power supply terminal 26: Current addition circuit 27, 27A: Current subtraction circuit 28: Power supply terminal 29: Ground terminal 30, 31: Slow Element 41, 41A, 41B: Reference voltage generation circuit 42, 42A: Voltage conversion circuit 43, 44: NMOS transistor 45, 46, 47: PMOS transistor 48: Operational amplifier 51: Substrate 52: P well 53: Drain region 54: Gate electrode 55: Gate oxide film 61: N well 62: P ⁺ diffusion region 63: N ⁺ diffusion region 64: N well 65: P ⁺ diffusion region 66: N ⁺ diffusion region MP1, MP2, MP3, MP4, MP5, MP6, MP7 , MP8, MP9: PMOS transistors MN1, MN2, MN3, MNR11, MNR1n, MNR21, MNR2n: NMOS transistors MC1: Transmission gate

Claims (10)

A memory array including a memory cell including a magnetoresistive element that stores data according to the direction of magnetization, and a write wiring;
A constant current source for causing a constant current for writing data to a selected memory cell selected from among the memory cells to flow through the write wiring;
A boost current source for supplying a boost current for charging a parasitic capacitance of a path through which the constant current flows immediately after a write operation is started;
A magnetic random access memory in which the magnitudes of the constant current and the boost current are controlled according to an operating temperature. The magnetic random access memory according to claim 1,
The magnitude of the constant current and the boost current is reduced as the operating temperature increases. Magnetic random access memory. The magnetic random access memory according to claim 1,
The boost current source includes a current boost circuit that outputs the boost current by discharging a charge charged in a capacitive element;
A magnetic random access memory comprising: control means for controlling the magnitude of the boost current output from the current boost circuit according to the operating temperature. The magnetic random access memory according to claim 3,
The control means sends an addition current to the first node to which the output of the current boost circuit is connected for a predetermined time after the write operation is started, or sends a subtraction current from the first node to the ground terminal. Including a current clamper circuit
The magnitude of the addition current and the subtraction current is controlled according to the operating temperature. Magnetic random access memory. The magnetic random access memory according to claim 4,
A second node electrically connected to the write wiring of the memory array;
A switching element connected between the first node and the second node;
The output of the constant current source is connected to the first node,
Magnetic random access memory. The magnetic random access memory according to claim 4,
The subtraction current is controlled according to the position of the selected memory cell. Magnetic random access memory. The magnetic random access memory according to claim 6,
The subtraction current is decreased as the position of the selected memory cell is farther from the constant current source. Magnetic random access memory. The magnetic random access memory according to claim 4,
One terminal of the capacitive element of the current boost circuit is connected to the first node, and the other terminal is connected to a third node whose potential is pulled up in response to the start of the write operation. . The magnetic random access memory according to claim 8,
The third node is connected to the power supply terminal via the first switch element, and is connected to the ground terminal via the second switch element,
When the write operation is started, the first switch element is turned on and the second switch element is turned off. When the write operation is finished, the first switch element is turned off and the second switch element is turned on. Magnetic random access memory. The magnetic random access memory according to claim 1,
A temperature compensation voltage generation circuit for generating a control voltage depending on the operating temperature;
The boost current source is:
A PMOS transistor that functions as a capacitive element for generating the boost current and has a drain supplied with a predetermined first power supply voltage;
The control voltage is supplied to the gate of the PMOS transistor until immediately before the write operation is started, and when the write operation is started, a predetermined second power supply voltage higher than the control voltage is applied to the gate of the PMOS transistor. Magnetic random access memory comprising a switch circuit for supplying.

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