JP2006155846A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a read margin by reducing a leak current that changes dependently upon a resistance value of a memory cell read in a semiconductor memory device including a cross-point type memory cell array. <P>SOLUTION: A semiconductor memory device comprises: a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected, and supplies a second voltage which is different from the first voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection lines separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents the displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  In the present invention, a plurality of memory cells are arranged in the row direction and the column direction, each of the memory cells in the same row has one end connected to the same row selection line, and each of the memory cells in the same column has the other end. The present invention relates to a semiconductor memory device having a cross-point type memory cell array in which the sides are connected to the same column selection line.

  In recent years, a memory cell has no selection element other than a memory element, and the memory element directly has a row selection line (hereinafter referred to as “data line”) and a column selection line (hereinafter referred to as “bit line”) in the memory cell. Development of a cross-point type semiconductor memory device (hereinafter, referred to as “cross-point memory” where appropriate) that forms a memory cell array in connection with the memory cell array (see, for example, Patent Document 1 below).

  In the “equal voltage detection method for a resistive cross-point memory cell array” disclosed in Patent Document 1 below, a predetermined voltage is supplied to each of a data line and a bit line, and a memory cell of an MRAM (Magnetic Random Access Memory) is supplied. The resistance state is detected. According to Patent Document 1, when a selected memory cell is read, a first voltage is applied to a selected data line, and a first voltage is applied to a selected and non-selected bit line and a non-selected data line. A second voltage lower than the voltage is applied to detect the resistance state, that is, the storage state of the selected memory cell.

  FIG. 24 shows a circuit configuration of a memory cell array of a conventional cross point memory, a setting level of a supply voltage to a data line and a bit line, and a current path. In the cross-point memory shown in FIG. 24, when the selected memory cell is read, the third voltage V2 is applied to the selected bit line, and the third bit is applied to the selected and non-selected data lines and the non-selected bit lines. A fourth voltage V1 higher than the voltage V2 is applied to detect the resistance state of the selected memory cell.

  FIG. 24 shows a case where the resistance state of a desired memory cell is determined by reading the current of the selected data line D0 when reading the resistance state of the memory cell where the data line D0 and the bit line B0 cross each other. Show.

  FIG. 25 shows voltage settings and current paths for each data line and each bit line when reading the resistance value of the memory cell where the data line D0 and the bit line B0 intersect. In FIG. 25, the voltage setting is the same as the voltage setting in Patent Document 1 described above, and when the selected memory cell is read, the first voltage V1 is applied to the selected data line, and the selected and non-selected bit lines are connected to the non-selected bit line. A second data V2 lower than the first voltage V1 is applied to the selected data line to detect the resistance state of the selected memory cell. In this case, the resistance state of the desired memory cell is determined by reading the current of the bit line B0.

FIG. 26 shows current paths of leakage currents I _leak 0, I _leak 1,..., I _leak k that are generated when the read current Id of the memory cell Md is measured. In the figure, “M” virtually indicates an ammeter that measures the current IM on the selected data line. In the read state shown in FIG. 26, the applied voltage to the bit line and the data line is set to the same setting as that shown in FIG. In this case, the read current Id of the memory cell Md is as shown in the following formula 1. In this specification, the operation symbols Σ _{i = 0 to k} represent an arithmetic sum in the range of i = 0 to k.

(Equation 1)
Id = IM−Σ _{i = 0 to k} I _leak i

FIG. 27 shows a case where the current path and direction of the leakage current Σ _{i = 0 to k} I _leak 1i generated when the read current Id1 of the memory cell Md1 is measured, and the read current Id2 of the memory cell Md2 are measured. The direction of the leakage current Σ _{i = 0 to k} I _leak 2i generated in FIG. In the read state shown in FIG. 27, the voltage applied to the bit line and the data line is set to be the same as that shown in FIG. In this case, if the resistance value of the memory cell Md1 is low in the memory cell connected to the selected bit line, the resistance division ratio between the on-resistance value of the driver that drives the data line and the resistance value of the memory cell Md1 is set. The voltage of the data line D1 is lowered by the corresponding voltage division.

Accordingly, since the voltage at the contact point d1A between the memory cell Md1 and the data line D1 is lower than the other data line voltages, a leakage current flowing from each bit line toward the memory cell Md1 is generated. That is, a leakage current (a _sneak current passing through the non-selected memory cell) Σ _{i = 0 to k} I _leak 1i is generated from each bit line through the data line D1 toward the memory cell Md1. In this case, the relationship between the read current Id1 of the memory cell Md1 and the measurement current IM1 in the data line D1 is as shown in the following formula 2. M1 in FIG. 27 virtually indicates an ammeter that measures the current IM1.

(Equation 2)
IM1 = Id1-Σ _{i = 0 to k} I _leak 1i

  If the resistance value of the memory cell Md2 is high in the memory cell connected to the selected bit line, the resistance division ratio between the on-resistance value of the driver that drives the data line and the resistance value of the memory cell Md2 is determined. Due to the divided voltage, the voltage of the data line D2 becomes high.

Accordingly, since the voltage at the contact point d2A between the memory cell Md2 and the data line D2 is higher than the other data line voltages, the leakage current (the _sneak current through the non-selected memory cells) Σ _{i = 0 to k} I _leak 2i flows from the data line D2 in the direction of each bit line. That is, a leakage current Σ _{i = 0 to k} I _leak 2i is generated from the data line D2 to the memory cell Mdx connected to each data line through each bit line. In this case, the relationship between the read current Id2 of the memory cell Md2 and the measurement current IM2 in the data line D2 is as shown in the following equation (3). M2 in FIG. 27 virtually indicates an ammeter that measures the current IM2.

(Equation 3)
IM2 = Id2 + Σ _{i = 0 to k} I _leak 2i

  In the first place, the reason why the leakage current occurs depending on the resistance value of the selected memory cell to be read is that, as shown in FIG. 28, there are apparent resistance values in the data line and the bit line. Specifically, the apparent resistance value is a resistance value at the time of driving the driver that drives the data line and the driver that drives the bit line.

  Specifically, FIG. 28 shows a case where the same applied voltage as that of the data line and the bit line shown in FIG. 24 is set. First, in order to set the voltage of the data line and the bit line, a driver A is required as shown in FIG. When the driver A is driven, there is an on-resistance (assuming the resistance value is R). When the resistance values of the memory cells on the selected bit line in the memory cell array, for example, R1, R2, R3, and R4 are different, the voltages Vdi (i = 1 to 4) of the data lines 1 to 4 are as follows. It is expressed by Equation 4. However, the drive voltage of each data line is assumed to be V1, and the voltage on the selected bit line is assumed to be V2 '.

(Equation 4)
Vdi = (V1-V2 ′) × Ri / (Ri + R)

  As shown in Equation 4, when Ri is different, the voltage Vdi of each data line is similarly different. Therefore, the voltage of each data line varies depending on the resistance value of the memory cell on the selected bit line, and a leak current is generated.

  Next, a case where the memory cell array is accessed (selected) in units of banks will be described with reference to FIG. FIG. 29 shows a state in which the memory cell array is divided into a plurality of banks. In this case, in addition to the on-resistance of the driver described with reference to FIG. 28, the on-resistance of the bank selection transistor BSi is added. For this reason, the voltage fluctuation of the data line becomes larger than in the case of the single memory cell array configuration shown in FIG. When memory cells in the memory array 10 (bank 1) in FIG. 29 are read, it is necessary to turn on the transistors in the transistor column BS1 (bank selection transistor column) that selects the memory cell array 10 (bank 1). There is. Further, in order to deselect the other memory cell arrays MR0, MR2, MR3 (banks 0, 2, 3), it is necessary to turn off all the transistors in the bank selection transistor columns BS0, BS2, BS3. In this way, by turning on the transistors in the bank selection transistor array BS1, the on-resistances Rbs1, Rbs2,..., Rbsx of the transistors exist on the data line. Therefore, the voltage Vdij of the data line in each bank shown in FIG. Here, i represents the order of the data lines in the same bank, and j represents the order of the banks. Rij indicates the resistance value of the memory cell connected to the selected bit line and the i-th data line in the bank j.

(Equation 5)
Vdij = (V1-V2 ′) × Rij / (Rij + R + Rbsj)

  As shown in Equation 5, the result varies more greatly than the voltage of the data line shown in Equation 4.

  FIG. 30 shows an example of the data line driver / amplifier circuit of FIG. The data line driver / amplifier circuit applies a predetermined voltage (for example, power supply voltage Vcc) to the selected and non-selected data lines. A P-channel MOSFET (hereinafter abbreviated as “PMOS”) P0 in the data line driver / amplifier circuit supplies a drive current Ix for accessing the memory cell from the data line. When the resistance value of the accessed memory cell is large, the current supplied from the PMOS (P0) of the data line drive circuit in FIG. 30 to the memory cell array decreases, so that the gate voltage of the PMOS increases. Further, when the resistance value of the accessed memory cell is small, the current supplied from the PMOS (P0) to the memory cell array increases, so that the gate voltage of the PMOS (P0) decreases. The gate voltage of the PMOS (P0) is amplified by the PMOS (P1) and the load transistor (N-channel MOSFET) in the data line current amplifier circuit in FIG. 30, and the amplified voltage V0 is output.

  FIG. 31 shows an example of the bit line drive circuit of FIG. This bit line drive circuit includes a load circuit P0 formed of PMOS and a column selection circuit formed of two sets of CMOS transfer gates. When the bit line is selected by the decode output of the column address decoder (column decoder), the column selection circuit turns on the right CMOS transfer gate in FIG. 31 and supplies the ground voltage Vss to the bit line. When is not selected, the CMOS transfer gate on the left side in FIG. 31 is turned on to supply a voltage obtained by dropping the threshold voltage of the PMOS (P0) from the power supply voltage Vcc. Note that when the bit line is not selected, the voltage supplied to the bit line is set to the same voltage level as the voltage supplied to the data line.

JP 2002-8369 A

As described above, the measurement current IM1 at the data line D1 in FIG. 27 is as shown in Equation 2, and the measurement current IM2 at the data line D2 in FIG. 27 is as shown in Equation 3. . As shown in Equations (2) and (3), when a predetermined voltage is applied to the data line and the bit line at the time of reading using the conventional data line driver / amplifier circuit and bit line driver, Since the current direction of the leak current changes depending on the resistance value, when the leak current value is large, the memory cell read currents Id1 and Id2 can be calculated from the measured currents IM1 and IM2 measured on the data line. It becomes difficult.

  As described above, FIG. 25 shows the set level of the supply voltage to the data line and the bit line and the current in that case in the “equal voltage detection method for the resistive cross-point memory cell array” disclosed in Patent Document 1. The route was shown. Further, FIG. 32 shows the current direction of the leakage current when the resistance value of the selected memory cell is high when the voltage setting level shown in FIG. 25 is adopted.

In FIG. 32, when the resistance value of the selected memory cell is high, the flow direction of the memory cell current Id1 flowing through the bit line B0 and the leak currents I _leak 0, I _leak 1,..., I _leak k are the same. . As shown in FIG. 27, when the resistance value of the selected memory cell is low, the memory cell current Id2 flowing through the bit line B0 and the leak currents I _leak 00, I _leak 01,..., I _leak 0k The direction of flow is reversed. In this case, since the values of the measurement currents IM1 and IM2 greatly change depending on the leakage current value, the memory cell currents Id1 and Id2 cannot be detected correctly. As shown in FIGS. 32 and 33, the method for setting the supply voltage to the data line and the bit line in FIG. 31 also depends on the resistance value of the selected memory cell, similarly to the leakage current shown in FIGS. This causes a problem that the leakage current flows backward.

  The present invention has been made in view of the above problems, and a first object of the present invention is to reduce the leakage current that changes depending on the resistance value of the memory cell to be read and to improve the read margin. It is a second object of the present invention to improve the read margin by a read circuit that takes into account the influence of a leakage current that varies depending on the resistance value of the memory cell to be read.

  In order to achieve this object, a semiconductor memory device according to the present invention includes a plurality of memory cells made of variable resistance elements that store information according to a change in electrical resistance, each arranged in the row direction and the column direction, and extended in the row direction. A plurality of column selection lines extending in the column direction, and each of the memory cells in the same row has one end of the variable resistance element connected to the same row selection line, and the memory in the same column Each of the cells is a semiconductor memory device having a memory cell array in which the other end side of the variable resistance element is connected to the same column selection line, and each of the column selection lines has a predetermined first time when reading is selected. A column read voltage supply circuit for supplying a voltage and supplying a second voltage different from the first voltage when reading is not selected, and supplying a row read voltage for supplying the second voltage during reading to each of the row selection lines. With circuit A sense circuit for detecting a current flowing through the selected row selection line separately from a current flowing through the non-selected row selection line and detecting an electrical resistance state of the selected memory cell at the time of reading; A column voltage displacement suppression circuit for individually suppressing the displacement of the supplied voltage level for each of the unselected column selection lines at the time of reading, and at least for the selected row selection line at the time of reading The first feature is that at least one of row voltage displacement suppression circuits that suppress displacement of the supplied voltage level is provided. Further, the row voltage displacement suppression circuit may suppress the displacement of the supplied voltage level with respect to each of the row selection lines at the time of reading.

  According to the semiconductor device of the first aspect of the present invention, since the displacement of the voltage level of the column selection line is suppressed by the column voltage displacement suppression circuit, the leakage induced by the displacement of the voltage level of the column selection line. The current can be reduced and the read margin can be improved. Further, by providing a row voltage displacement suppression circuit instead of or in addition to the column voltage displacement suppression circuit, the leakage current induced by the displacement of the voltage level of the row selection line can be further reduced, and the read margin can be improved. In particular, by providing both the column voltage displacement suppression circuit and the row voltage displacement suppression circuit, the read margin can be improved more effectively.

  Furthermore, in the semiconductor device according to the first aspect of the present invention, a plurality of the memory cell arrays are arranged in at least the row direction, and the plurality of row selection lines of the memory cell arrays select the memory cell array. Each of the plurality of row selection lines of the memory cell array selected by the array selection transistor is connected to each corresponding global row selection line via the array selection transistor. The second voltage can be supplied via the corresponding global row selection line, and the row voltage displacement suppression circuit is separately provided between the row selection line and the array selection transistor. The second feature.

  In the semiconductor device according to the second aspect of the present invention, a plurality of memory cell arrays are arranged in the row direction, and each of the plurality of row selection lines of each memory cell array has a corresponding global row selection line. In the configuration in which the row voltage displacement suppression circuit is directly connected to the row selection line, the voltage level displacement can be effectively suppressed with respect to the row selection line of each memory cell array. In other words, when the row voltage displacement suppression circuit is configured to be connected to the row selection line via the array selection transistor, although the voltage level displacement can be effectively suppressed for the global row selection line, Since the suppression effect on the row selection line of the memory cell array is hindered by the array selection transistor, the second characteristic configuration can eliminate such inconvenience.

  Furthermore, in the semiconductor device according to the present invention, when the sense circuit reads a high resistance memory cell in which the current flowing through the selected row selection line and the electrical resistance of the selected memory cell are in a high resistance state, A first current state in which a current flowing through the selected row selection line is maximized depending on a distribution pattern of electrical resistance states of the other non-selected memory cells in the memory array; and the selected memory cell The current flowing through the selected row selection line at the time of reading of the low-resistance memory cell whose electrical resistance is in the low-resistance state depends on the distribution pattern of the electrical resistance state of the other non-selected memory cells in the memory array. A third feature is that the current in the intermediate state of the second current state, which is the minimum state, can be compared.

  Furthermore, in the semiconductor device according to the third aspect of the present invention, the sense circuit converts the current flowing through the selected row selection line into a read voltage level, and the first current-voltage conversion circuit unit. A first reference current generating circuit that approximately realizes a current state; a second reference current generating circuit that approximately realizes the second current state; and an intermediate state between the first current state and the second current state It is preferable that a second current-voltage conversion circuit unit that converts a current into a reference voltage level and a comparison circuit that compares the read voltage level with the reference voltage level are provided.

  According to the semiconductor memory device of the third aspect of the present invention, the row selection line in the intermediate state between the two resistance states of the memory cell to be read and in which the influence of the respective leakage currents is maximized. Since the flowing current is used as a reference value, the read current of the row selection line connected to the memory cell to be read can be compared with the reference value, so that for any of the two resistance states of the memory cell to be read, The maximum read margin can be obtained, and the read margin can be improved. In particular, by combining with the first feature, the read margin is further improved.

  Furthermore, the semiconductor device according to the third aspect of the present invention includes a first reference current generation circuit that approximately realizes the first current state, and a second reference current that approximately realizes the second current state. Each of the first reference current generation circuit and the second reference current generation circuit is equivalent to the memory cell array including a reference memory cell including the same variable resistance element as the memory cell. A first reference memory cell array, a reference column read voltage supply circuit having a configuration equivalent to the column read voltage supply circuit, and a reference row read voltage supply circuit having a configuration equivalent to the row read voltage supply circuit. Electricity of the reference memory cell in the reference memory cell array of the current generation circuit The resistance distribution pattern is set to the first distribution pattern in which the current flowing through the row selection line of the selected reference memory cell array is in the first current state, and the second reference current generating circuit includes the reference memory cell array. The distribution pattern of the electric resistance state of the reference memory cell is set to a second distribution pattern in which the current flowing through the row selection line of the selected reference memory cell array is set to the second current state. And

  According to the semiconductor memory device of the fourth feature of the present invention, the first reference that approximately realizes the first current state in the second feature by two reference memory cell arrays set to different distribution patterns. Since the current generation circuit and the second reference current generation circuit that approximately realizes the second current state are reliably and easily realized, the operational effects of the semiconductor memory device according to the second aspect of the present invention are specifically described. Can be played.

  Furthermore, the semiconductor device according to the fourth aspect of the present invention includes a plurality of the memory cell arrays, and the sense circuit for at least two of the memory cell arrays is a first reference current generating circuit. The fifth feature is that the second reference current generating circuit is used in common.

  According to the semiconductor memory device of the fifth aspect of the present invention, the first reference current generation circuit that approximately realizes the first current state and the second reference current generation that approximately realizes the second current state. Since the circuit is commonly used in a plurality of memory cell arrays, the relative circuit scale (that is, the occupied area on the semiconductor chip) of the first reference current generation circuit and the second reference current generation circuit can be reduced, and the semiconductor memory The cost of the apparatus can be reduced.

  An embodiment of a semiconductor memory device according to the present invention (hereinafter referred to as “the present invention device” as appropriate) will be described with reference to the drawings.

<First Embodiment>
FIG. 1 shows a block configuration of main parts related to a read operation of a memory cell in the memory cell array 10 of the device of the present invention. The memory cell array 10 is a cross-point type memory cell array structure, in which memory cells (not shown) made of variable resistance elements that store information by changing electrical resistance are arranged in a plurality of arrays in the row direction and the column direction, respectively. A plurality of data lines (row selection lines) extending in the row direction and a plurality of bit lines (column selection lines) extending in the column direction are provided, and each memory cell in the same row has the same data on one end side of the variable resistance element. Each memory cell in the same column is configured by connecting the other end of the variable resistance element to the same bit line. As an example, the memory cell array 10 has an array size of 16 rows × 16 columns, and in this case, there are 16 data lines and 16 bit lines.

  As shown in FIG. 1, the device of the present invention includes a data line drive circuit 11 that individually drives each data line, a bit line drive circuit 12 that individually drives each bit line, A row decoder 13 for selecting a selected data line to be connected to the selected memory cell to be read from among the data lines, and a column decoder 14 for selecting a selected bit line to be connected to the selected memory cell to be read from among a plurality of bit lines. Is provided.

  Furthermore, the device of the present invention uses two reference memory cell arrays 20a and 20b for generating a reference voltage using the same memory cell with the same array size as the memory cell array 10, and output voltages Vref0 and Vref1 of the reference memory cell arrays 20a and 20b. A reference voltage level is generated, a read voltage level is generated from the voltage level Vm of the selected data line of the memory cell array 10, and the storage state (resistance state) of the selected memory cell is determined by comparing the read voltage level with the reference voltage level. The sense circuit 15 is provided.

  The two reference memory cell arrays 20a and 20b include a data line drive circuit 21, a bit line drive circuit 12, and a data line drive circuit 21 and a bit line drive that have the same circuit configuration as the column decoder 14 provided for the memory cell array 10. A circuit 22 and a column decoder 24 are provided.

  As shown in FIG. 2, the data line drive circuit 11 provided in each data line includes a row read voltage supply circuit 30 that supplies a second voltage (for example, a power supply voltage Vcc) and a row read voltage supply circuit 30 at the time of reading. Is provided with a row voltage displacement suppression circuit 31 that suppresses the displacement of the voltage level supplied from. Specifically, the row read voltage supply circuit 30 is formed of a PMOS whose gate level is fixed to a predetermined bias level and set to operate in a saturation region, and the source of the PMOS is set to the second voltage and the drain is supplied to the drain. Are connected to an output node for outputting the voltage level Vm of the selected data line. The row voltage displacement suppression circuit 31 includes an N-channel MOSFET (hereinafter simply referred to as “NMOS”) 32 having a source connected to the data line and a drain connected to the output node, and a gate voltage of the NMOS 32 of the data line. A feedback circuit unit including an inverter 33 that adjusts the on-resistance of the NMOS 32 by changing the voltage level according to the voltage level Vd is provided. As shown in FIG. 2, the voltage level Vd supplied to the data line is a voltage obtained by subtracting the voltage drop of the PMOS 30 and the row voltage displacement suppression circuit 31 from the second voltage (for example, the power supply voltage Vcc). Is adjusted by the inversion level of the inverter 33 of the row voltage displacement suppression circuit 31 and the threshold voltage of the NMOS 32.

  As shown in FIG. 3, the bit line drive circuit 12 provided in each bit line supplies a predetermined first voltage (for example, ground voltage Vss) when reading is selected, and is different from the first voltage when reading is not selected. A column read voltage supply circuit 40 that supplies two voltages (for example, the power supply voltage Vcc) and a column voltage displacement suppression circuit 41 that suppresses displacement of the voltage level supplied from the column read voltage supply circuit 40 are configured. Specifically, the column read voltage supply circuit 40 includes a load circuit formed of a PMOS 42 and a column selection circuit 45 formed of two sets of CMOS transfer gates 43 and 44. When the bit line is selected by the decode output of the column decoder 14, the column selection circuit 45 turns on the right CMOS transfer gate 44, supplies the first voltage to the bit line, and the bit line is not selected. The left CMOS transfer gate 43 is turned on, and the second voltage is supplied via the PMOS 42, the CMOS transfer gate 43 and the column voltage displacement suppression circuit 41. The PMOS 42 is set so that the source is connected to the power supply voltage Vcc, the drain is connected to one end of the CMOS transfer gate 43, and the gate is fixed at a predetermined bias level and operates in the saturation region. The other end of the CMOS transfer gate 43 is connected to the bit line via the column voltage displacement suppression circuit 41. The CMOS transfer gate 44 has one end connected to the ground voltage Vss and the other end connected to the bit line. The column voltage displacement suppression circuit 41 has an NMOS 46 whose source is connected to the bit line and whose drain is connected to the other end of the CMOS transfer gate 43, and the gate voltage of the NMOS 46 is changed according to the bit voltage level Vb to turn on the NMOS 46. A feedback circuit unit including an inverter 47 for adjusting the resistance is provided. When the bit line is not selected, the voltage level Vb supplied to the bit line is, as shown in FIG. 3, from the second voltage (for example, the power supply voltage Vcc), the PMOS 42, the CMOS transfer gate 43, and the column voltage displacement suppression. The voltage is obtained by subtracting the voltage drop of the circuit 41, and is specifically adjusted by the inversion level of the inverter 47 and the threshold voltage of the NMOS 46 of the column voltage displacement suppression circuit 41. Note that the second voltage supplied to the non-selected bit line is at the same voltage level as the second voltage supplied to the data line.

  The row voltage displacement suppression circuit 31 shown in FIG. 2 and the column voltage displacement suppression circuit 41 shown in FIG. 3 are the problems of the cross-point type memory cell array that have already been described with reference to FIG. 26 or FIG. This is provided in order to suppress fluctuations in the current measured on the selected data line (see Equations 2 and 3) due to a sneak current passing through the selected memory cell and to improve the read margin.

  Next, the operation of the row voltage displacement suppression circuit 31 will be described with reference to FIG. When the resistance value of the selected memory cell to be read is high, the voltage of the selected data line rises. When the voltage Vd of the selected data line increases, the input level of the inverter 33 in the row voltage displacement suppression circuit 31 increases and the output level of the inverter 31 decreases. Therefore, when the output level of the inverter 31 is lowered, the gate-source voltage of the NMOS 32 is lowered, the on-resistance of the NMOS 32 is lowered, and the driving ability for the selected data line is lowered, so that the leakage current supply ability is also lowered. It will be.

  On the other hand, when the resistance value of the selected memory cell is low, the voltage of the selected data line becomes lower than the voltage of the data line connected to the other memory cell having a high resistance value. A sneak current (leakage current) is generated from the level (non-selected data line) to the selected data line having a low data line voltage level. Thus, when the voltage of the selected data line decreases, the input level of the inverter 33 in the row voltage displacement suppression circuit 31 decreases, and the output level of the inverter 33 increases. Therefore, when the output level of the inverter 33 is increased, the gate-source voltage of the NMOS 32 is increased, the on-resistance of the NMOS 32 is increased, and the driving capability for the selected data line is increased. Increases, and the leakage current to the above-mentioned non-selected data lines is substantially reduced.

  Regardless of the resistance value of the selected memory cell, the leakage current (sneak current) tends to increase as the size of the memory cell array increases. Therefore, the effect of reducing the leakage current of the row voltage displacement suppression circuit 31 becomes more prominent in a large memory cell array in which the sneak current tends to increase.

  Next, the operation of the column voltage displacement suppression circuit 41 will be described with reference to FIG. The column voltage displacement suppression circuit 41 reduces the voltage level of the non-selected bit line when the voltage of the non-selected bit line is higher than the voltages of the data line and the other non-selected bit lines, and the non-selected bit line. When the voltage of the bit line is lower than the voltages of the data line and other unselected bit lines, the bit line functions to increase the level of the unselected bit line. Since the operation principle is the same as that of the row voltage displacement suppression circuit 31, duplicate description is omitted.

  Next, in the row read voltage supply circuit 30, the voltage level Vm of the selected data line output to the output node, that is, the drain voltage of the PMOS forming the row read voltage supply circuit 30, and the select data measured at the output node The relationship between the current flowing through the line, that is, the drain current of the PMOS will be described.

  FIG. 4 shows load characteristics (IV characteristics: indicated by “L” in the figure) with the PMOS operating in the saturation region as load resistance, and various distribution patterns (pattern A) of the memory cells in the memory cell array. The IV characteristics (indicated by “A” to “H” in the figure) of the memory cell array in FIG.

    Next, various distribution patterns (patterns A to H) of resistance states of the memory cells in the memory cell array will be described with reference to FIG. FIG. 5 shows a simple array size of 8 rows × 12 columns in order to explain the characteristics of each distribution pattern, but this array size does not necessarily indicate an actual array size.

  Now, in FIG. 5, the pattern A is such that any one row of memory cells connected to one data line and any one column of memory cells connected to one bit line have high resistance. A distribution pattern is shown in which the memory cells in the region excluding the high-resistance memory cell region have low resistance. When the selected memory cell has a high resistance, the sneak current becomes the largest and the read current becomes the largest when the high resistance memory cell at the position where the row and the column made of the high resistance are crossed is read. If the selected memory cell has a low resistance, one of the low resistance memory cells is selected. The pattern B is an arbitrary row of memory cells connected to one data line and an arbitrary column of memory cells connected to one bit line. A distribution pattern is shown in which the memory cells except for the memory cells connected to both of the bit lines have high resistance, and the memory cells in the region excluding the high resistance memory cell region have low resistance. If the selected memory cell has a high resistance, one of the high resistance memory cells is selected. When the selected memory cell has a low resistance, when the low resistance memory cell connected to both the one data line and the one bit line is read, the sneak current becomes the largest, and the low resistance memory cell The read current becomes the largest. In the pattern C, an arbitrary row of memory cells connected to one data line and an arbitrary column of memory cells connected to one bit line have a low resistance, and the low resistance memory cell region A distribution pattern in which the memory cells in the region excluding have high resistance is shown. If the selected memory cell has a high resistance, one of the high resistance memory cells is selected. When the selected memory cell has a low resistance, the read current becomes the smallest when the low resistance memory cell at the position where the row and the column in which the low resistance memory cells are distributed is read is read. That is, the pattern C is a reverse pattern of the pattern A. The pattern D is an arbitrary row of memory cells connected to one data line and an arbitrary column of memory cells connected to one bit line. A distribution pattern is shown in which the memory cells except for the memory cells connected to both of the bit lines have a low resistance, and the memory cells in the region excluding the low resistance memory cell region have a high resistance. When the selected memory cell has a high resistance, when the high resistance memory cell connected to both the one data line and the one bit line is read, the sneak current becomes the largest, and the high resistance memory cell Read current is minimized. If the selected memory cell has a low resistance, one of the low resistance memory cells is selected.

  Pattern E shows a distribution pattern in which only one memory cell has high resistance and the other memory cells have low resistance. When the selected memory cell has a high resistance, the one high resistance memory cell is selected. If the selected memory cell has a low resistance, one of the other low resistance memory cells is selected. Pattern F shows a distribution pattern in which only one memory cell has a low resistance and the other memory cells have a high resistance. When the selected memory cell has a low resistance, the one low resistance memory cell is selected. If the selected memory cell has a high resistance, one of the other high resistance memory cells is selected. That is, the pattern F is an inverted pattern of the pattern E. Pattern G shows a distribution pattern in which only one row of memory cells connected to one data line has a low resistance, and other rows of memory cells have a high resistance. When the selected memory cell has a low resistance, it is selected from the low-resistance memory cells in one row. When the selected memory cell has a high resistance, it is selected from the high resistance memory cells in other rows. The pattern H shows a distribution pattern in which only one row of memory cells connected to one data line has a high resistance, and other rows of memory cells have a low resistance. When the selected memory cell has a high resistance, it is selected from the one row of high resistance memory cells. When the selected memory cell has a low resistance, it is selected from the low resistance memory cells in other rows. That is, the pattern H is a reverse pattern of the pattern G.

  As a result of the circuit simulation performed on each pattern, as shown in FIG. 4, when the selected memory cell is in a high resistance state, the pattern A (particularly, the pattern A in FIG. 8B described later) In this case, when the memory cell at the cross point between the row and the column in the high resistance state is read, the read current in the high resistance state is maximized, which is the worst case. Further, when the selected memory cell is in the low resistance state, it is the case of the pattern C (particularly, the pattern C in FIG. 10B described later), and the cell at the cross point of the row and column in the low resistance state is read. In this case, the read current in the low resistance state is minimized, which is the worst case.

  Next, as a factor that affects the read current, there is location dependence of the selected memory cell in the memory cell array. FIG. 6A shows the position on the bit line and the current path of the selected memory cell when reading the memory cell. This read current drives the data line currents Id0 to Idn of the data lines d0 to dn from the data line drive circuit 11, and flows to the selected bit line bn. That is, the current Ibn flowing through the selected bit line bn is the sum of the data line currents Idi (i = 0 to n) in all the data lines, as shown in the following formula 6.

(Equation 6)
Ibn = Id0 + Id1 +... + Idn

  Therefore, the bit line potential differs between the case where the selected memory cell X0 farthest from the bit line drive circuit 12 of the selected bit line bn is selected and the case where the selected memory cell Xn closest to the bit line drive circuit 12 is selected.

  FIG. 6B shows the relationship between the bit line length (distance between the selected memory cell and the bit line drive circuit 12) and the bit line potential. As shown in FIG. 6B, when selecting a memory cell closer to the bit line drive circuit 12, when selecting a memory cell with a lower bit line potential and far from the bit line drive circuit. The bit line potential becomes high. Therefore, the read current when the high resistance memory cell X0 farthest from the bit line drive circuit 12 is selected is smaller than the read current when the high resistance memory cell Xn closest to the bit line drive circuit 12 is selected.

  FIG. 7A shows the position on the data line and the current path of the selected memory cell when reading the memory cell. When the memory cell Y0 closest to the data line drive circuit 11 in FIG. 7A is selected, the current from the data drive circuit 11 passes through the selected memory cell Y0 and the bit line b0 to the bit line drive circuit 12. It reaches. When the memory cell Yn farthest from the data line drive circuit 11 is selected, the current from the data drive circuit 11 reaches the bit line drive circuit 12 through the selected memory cell Yn and the bit line bn. The difference between selecting the memory cell X and selecting the memory cell Y is the length of the data line dx (distance between the selected memory cell and the data line drive circuit 11). When the memory cell Y0 is selected, since the data line dx is shorter than when the memory cell Yn is selected, the data line potential increases due to the line length difference of the data line dx, that is, the resistance difference of the data line dx. As a result, the amount of current flowing increases as the potential increases.

  FIG. 7B shows the potential difference between the data lines when accessing the memory cell Y0 and when accessing the memory cell Yn, that is, the relationship between the length of the data line and the data line potential.

  From the above, the location dependency of the selected memory cell on the bit line shown in FIGS. 6A and 6B, and the location dependency of the selected memory cell on the data line shown in FIGS. 7A and 7B. Are considered, the location dependence of the selected memory cell is as follows for the various distribution patterns (patterns A to D) shown in FIG.

  First, the location dependency of the selected memory cell on the bit line shown in FIGS. 6A and 6B is considered. Regarding the pattern A, when the read currents of the memory cells a shown in FIGS. 8A, 8D, and 8E are compared with each other, the read current of the memory cell a of the pattern A shown in FIG. Maximum. Regarding the pattern B, when the read currents of the memory cells b shown in FIGS. 9A, 9D, and 9E are compared with each other, the read current of the memory cell b of the pattern B shown in FIG. Maximum. Regarding the pattern C, when the read currents of the memory cells c shown in FIGS. 10A, 10D, and 10E are compared with each other, the read current of the memory cell c of the pattern C shown in FIG. Minimal. Regarding the pattern D, when the read currents of the memory cells d shown in FIGS. 11A, 11D, and 11E are compared with each other, the read current of the memory cell d of the pattern D shown in FIG. Minimal.

  Next, the location dependency of the selected memory cell on the data line shown in FIGS. 7A and 7B is considered. Regarding the pattern A, when the read currents of the memory cells a shown in FIGS. 8A and 8B are compared with each other, the read current of the memory cell a of the pattern A shown in FIG. Regarding the pattern B, when the read currents of the memory cells b shown in FIGS. 9A and 9B are compared with each other, the read current of the memory cell b of the pattern B shown in FIG. 9B is maximized. Regarding the pattern C, when the read currents of the memory cells c shown in FIGS. 10A and 10B are compared with each other, the read current of the memory cell c of the pattern C shown in FIG. 10B is minimized. Regarding the pattern D, when the read currents of the memory cells d shown in FIGS. 11A and 11B are compared with each other, the read current of the memory cell d of the pattern D shown in FIG. 11B is minimized.

  In FIG. 4, the operating point is the intersection of the load characteristic L and the IV characteristic of the memory cell array. Let Vj be the voltage level at the intersection J between the load characteristic L and the IV characteristic (pattern A) of the memory cell array when the selected memory cell has a high resistance. The voltage level at the intersection K between the load characteristic L and the IV characteristic (pattern C) of the memory cell array when the selected memory cell has a low resistance is Vk. The voltage difference between the intersections J and K is Vjk. The voltage difference Vjk indicates the read margin voltage when the selected memory cell has a high resistance and a low resistance.

  On the other hand, a case where the PMOS forming the row read voltage supply circuit 30 operates in the linear region instead of the saturation region will be described with reference to FIG. In this case, the PMOS gate of the load resistor is connected to the drain instead of a predetermined bias level. The load characteristic L ′ operating in this linear region is Vm at the voltage level at the intersection M with the IV characteristic (pattern A) of the memory cell array when the selected memory cell has a high resistance. The voltage level at the intersection N between the load characteristic L ′ and the IV characteristic (pattern C or H) of the memory cell array when the selected memory cell has a low resistance is defined as Vn. A voltage difference between the intersections M and N is defined as Vmn. The voltage difference Vmn indicates the read margin voltage when the selected memory cell has a high resistance and a low resistance.

  As is clear from FIGS. 4 and 12, the voltage difference Vjk between the intersections J and K with the load characteristic L operating in the saturation region is the intersection M with the load characteristic L ′ operating in the linear region (as a resistance element). , A result (Vjk> Vmn) larger than the voltage difference Vmn between N is obtained. Therefore, based on this result, a larger read margin can be secured by operating in the saturation region with the gate voltage of the PMOS of the row read voltage supply circuit 30 and the column read voltage supply circuit 40 being set to a predetermined bias level (intermediate level). Is possible.

  Next, FIG. 13 shows IV characteristics of the memory cell array when the row voltage displacement suppression circuit 31 and the column voltage displacement suppression circuit 41 shown in FIGS. 2 and 3 are used. FIG. 13 shows only the patterns A and C, which are worst case patterns when the selected memory cell has a high resistance and a low resistance, respectively.

  As shown in FIG. 13, the IV characteristic C ′ of the memory cell array of the pattern C when the selected memory cell has a low resistance is when the row voltage displacement suppression circuit 31 and the column voltage displacement suppression circuit 41 shown in FIG. 4 are not used. As compared with the IV characteristic C of the memory cell array having the same pattern, the influence of the leakage current is suppressed and the current characteristic is improved. Further, the IV characteristic A ′ of the memory cell array of pattern A when the selected memory cell is high resistance is the same pattern memory when the row voltage displacement suppression circuit 31 and the column voltage displacement suppression circuit 41 shown in FIG. 4 are not used. Compared with the IV characteristic A of the cell array, the influence of the leakage current is suppressed, the drain current is suppressed with respect to the rise of the drain voltage, and the characteristics are improved. Therefore, the voltage difference between the intersections O and P obtained from the intersections O and P of the IV characteristics C ′ and A ′ and the load characteristic L of the memory cell array having the row voltage displacement suppression circuit 31 and the column voltage displacement suppression circuit 41. It can be seen that Vop is larger than the voltage difference Vjk when the row voltage displacement suppression circuit 31 and the column voltage displacement suppression circuit 41 are not used (Vop> Vjk), and the read margin is improved.

  Next, reference memory cell arrays 20a and 20b used in the device of the present invention will be described.

  As described above, as a result of the circuit simulation, when the selected memory cell is in the high resistance state as shown in FIG. 4 (or FIG. 12), the distribution pattern of the resistance state of the other non-selected memory cells is pattern A. When the selected memory cell is in the low resistance state, the worst case occurs when the distribution pattern of the resistance state of the other unselected memory cells is the pattern C. From this result, when the selected memory cell in the high resistance state is read in various distribution patterns in the memory cell array 10, the measured current value on the selected data line has a drain smaller than the IV characteristic A in FIG. It becomes current. When the selected memory cell in the low resistance state is read, the measured current value on the selected data line is a drain current larger than the IV characteristic C in FIG. Therefore, when the resistance state of the selected memory cell is determined, the selected memory cell is determined by setting the IV characteristics A and IV characteristics C (Ref level in FIG. 4) in FIG. 4 as the determination reference levels. Both resistance states can be determined.

  Therefore, in one of the reference memory cell arrays 20a and 20b, the distribution pattern of the resistance state of each memory cell is set to pattern A, and the other is set to pattern C. For example, when the reference memory cell array 20a is set to the pattern A and the reference memory cell array 20b is set to the pattern C, the current flowing through the selected data line when the reference memory cell array 20a reads the selected memory cell in the high resistance state is different. The first current state which becomes the maximum state depending on the distribution pattern of the electric resistance state of the non-selected memory cells is realized, and functions as a first reference current generation circuit. In the reference memory cell array 20b, the current flowing through the selected data line at the time of reading the selected memory cell in the low resistance state becomes the minimum state depending on the distribution pattern of the electric resistance state of the other non-selected memory cells. A two-current state is realized and functions as a second reference current generation circuit.

  Here, since the memory cells for the reference memory cell arrays 20a and 20b must be selected so as to have the predetermined pattern A or C, a data line drive circuit provided for the reference memory cell arrays 20a and 20b. 21, the bit line drive circuit 22, and the column decoder 24 are set so as to satisfy the condition.

  Next, the sense circuit 15 of the device of the present invention will be described. FIG. 14 shows a circuit block diagram of the sense circuit 15. As shown in FIG. 14, the sense circuit 15 includes a first current-voltage conversion circuit unit 51 that converts the current of the selected data line into a read voltage level, and an intermediate state between the first current state and the second current state. The second current-voltage conversion circuit unit 52 that converts the current to a reference voltage level, and a comparison circuit 53 that compares the converted read voltage level with the reference voltage level. The reference memory cell arrays 20a and 20b are configured separately from the sense circuit 15. However, the reference memory cell arrays 20a and 20b can be regarded as a part of the sense circuit 15 substantially.

  As shown in FIG. 14, the second current-voltage conversion circuit unit 52 inputs the output voltage Vref0 of the reference memory cell array 20a to the gate of the PMOS 54, and inputs the output voltage Vref1 of the reference memory cell array 20b to the gate of the PMOS 55, The combined current I2 of the drain current I0 of the PMOS 54 and the drain current I1 of the PMOS 55 flows to the NMOS 56, and the current I3 which is half of the combined current I2 flows to the NMOS 57 by the current mirror circuit of the NMOS 57 and the NMOS 56 which is set to half the current amount of the NMOS 56. The reference voltage level Vref is output to the drain of the NMOS 57.

  On the other hand, in the first current-voltage conversion circuit unit 51, the output voltage Vm of the memory cell array 10 is input to the gate of the PMOS 58, the drain current I4 of the PMOS 58 flows to the NMOS 59, and the current mirror circuit of the NMOS 60 and NMOS 59 equivalent to the NMOS 59 The current I4 flows through the NMOS 60, and the read voltage level Vread is output to the drain of the NMOS 60. The NMOS 57, NMOS 59, and NMOS 60 are set to the same current capability.

  By comparing the read voltage level Vread generated by the first current-voltage conversion circuit unit 51 with the reference voltage level Vref generated by the second current-voltage conversion circuit unit 52 by the comparison circuit 53, the memory of the selected memory cell is stored. Perform data judgment.

15 shows the IV characteristic H of the load transistor (PMOS 30) shown in FIG. 2 and the I of the memory cell array in various distribution patterns (patterns A to H) of the resistance states of the memory cells in the memory cell array shown in FIG. -V characteristics are also shown. The I-V characteristic H of the load transistor shown in FIG. 15 indicates that the potential Vref0 at the intersection with the IV characteristic C _L (when reading the low-resistance memory cell of the pattern C) indicates the L (low) level. The potential Vref1 at the intersection with A _H (when reading the high-resistance memory cell of pattern A) needs to have an IV characteristic such that it indicates an H (high) level, and an intermediate level between Vref0 and Vref1 is set as a reference level Vref create.

  The memory cell of the device of the present invention may have any structure and characteristics as long as it is a variable resistance element that stores information by a change in electrical resistance. Further, the electric resistance changing method (that is, the writing method) is not necessarily limited to the electric method. Further, the memory retention characteristics of the memory cell may be volatile or nonvolatile. In addition, since the device of the present invention is applied to a nonvolatile memory, the density of the memory cell array can be increased, so that a large-capacity nonvolatile memory can be realized.

  As an example of the memory cell, the following is assumed. For example, the present invention is also applied to a state change memory (Phase Change memory) that uses a state change between a crystalline phase (low resistance) and an amorphous phase (high resistance) due to a phase change of a phase change material such as a chalcogenide compound. In addition, using a fluororesin-based material for the memory cell, a polymer memory and a polymer ferroelectric RAM in which the ferroelectric polarization state changes by the polarization orientation of the fluororesin-based material molecule (polar conductive polymer molecule) (PFRAM) can also be applied.

Further, the present invention can also be applied to a case where a memory cell is formed of a Mn oxide material such as PCMO (Pr _(1-x) Ca _x MnO ₃ ) having a perovskite structure having a CMR effect (Cossal Magnetic Resistance). .
This is based on the fact that the resistance value of a Mn oxide material such as PCMO that constitutes a memory cell element changes due to the change of state in two phases of a ferromagnetic metal body and a diamagnetic insulator. To do.

  In addition, the present invention can be applied to a memory including a memory cell whose resistance value changes depending on an electric pulse using a metal oxide containing a transition metal such as Ni, Ti, Hf, or Zr.

In addition, a memory cell is composed of metal oxides such as STO (SrTiO ₃ ), SZO (SrZrO ₃ ) and SRO (SrRuO ₃ ) and metal fine particles, and an application is made at the interface between the metal oxide and the metal fine particles. The present invention can also be applied to a memory using an interface phenomenon in which the resistance value of the memory cell changes according to the voltage.

In a broader sense, it can be applied to the following memories.
1) The resistance element constituting the memory cell can be applied to a memory made of a semiconductor material.
2) The present invention can be applied to a memory in which a resistive element constituting a memory cell is made of an oxide or a nitride.
3) The present invention can be applied to a memory in which a resistance element constituting a memory cell is made of a compound of a metal and a semiconductor.
4) The resistance element constituting the memory cell can be applied to a memory made of a fluorine resin material.
5) It can be applied to a polymer ferroelectric RAM (PFRAM) in which a resistance element constituting a memory cell is made of a conductive polymer.
6) The present invention can be applied to a memory (OUM) in which a resistance element constituting a memory cell is made of a chalcogenide material.
7) The present invention can be applied to a memory in which a resistive element constituting a memory cell is made of a compound having a perovskite structure having a CMR effect.
8) The present invention can be applied to an MRAM in which a resistance element constituting a memory cell is formed by a spin-dependent tunnel junction element.

Second Embodiment
In the first embodiment, the sense circuit 15 having the circuit configuration shown in FIG. 14 is exemplified as the sense circuit of the device of the present invention. However, the sense circuit is not necessarily limited to the circuit configuration shown in FIG.

  For example, as shown in FIG. 16, the sense circuit may be composed of one or more inverter circuits 15a. In FIG. 16, the output Vm of the data drive circuit 11 read from a desired memory cell in the memory cell array 10 shown in FIG. 1 is input to the first stage of the inverter circuit 15a having two stages of inverters. Since this inverter circuit 15a has a voltage amplification function and a current amplification function, it passes through the inverter circuit 15a, thereby discriminating binary data with reference to a normal sense amplifier (reference level for discriminating binary data and outputting it) The circuit for amplifying the level) can be omitted. The number of stages of the inverter circuit 15a may be at least one. Here, the inversion level of the first stage inverter of the inverter circuit 15a may be set to an intermediate level between potentials Vk and Vj shown in FIG.

  FIG. 17 shows a block configuration of main parts related to the read operation of the device of the present invention when the inverter circuit 15a shown in FIG. 16 is used as a sense circuit. As shown in FIG. 17, by using the inverter circuit 15a as a sense circuit, the circuit configuration of the sense circuit itself is simplified, and a circuit for generating the reference level Vref as shown in FIG. The circuit scale associated with the readout system can be greatly reduced.

  FIG. 18 shows the read output Vout and the inverter 15a when the output Vm of the data line drive circuit 11 read from a desired memory cell in the memory cell array 10 in FIG. 17 is input to the inverter circuit 15a. The relationship with the variation range of the inversion level of the first stage inverter is shown. In FIG. 18, it is assumed that the inversion level of the first-stage inverter varies from VrefL to VrefH.

Here, the potential of the intersection between the I-V characteristic _{C L} of the I-V characteristic H and the memory cell of the PMOS load transistors and Vk, PMOS load transistors of the I-V characteristic H and the memory cells the I-V characteristic _{A H} When the potential at the intersection with Vj is Vj, the condition shown by the following two inequalities must be established.

(Equation 7)
VrefL> Vk
VrefH <Vj

  Here, the voltage level indicated by (VrefL−Vk) becomes the read voltage margin of the low resistance memory cell, and the voltage level indicated by (Vj−VrefH) becomes the read voltage margin of the high resistance memory cell.

<Third Embodiment>
Next, a third circuit configuration of the sense circuit of the device of the present invention will be described with reference to FIG. As shown in FIG. 19, in the third embodiment, the sense circuit 15b is configured such that the voltage level Vm of the selected data line and the current flowing through the selected data line at the time of reading from the high-resistance memory cell are other unselected memories in the memory cell array. A first comparison circuit 16 that compares the first current state, which is the maximum state depending on the distribution pattern of the electric resistance state of the cell, into a voltage, and a voltage level Vm of the selected data line, A second voltage obtained by converting a second current state in which the current flowing through the selected data line at the time of reading of the resistive memory cell becomes a minimum state depending on the distribution pattern of the electrical resistance state of the other non-selected memory cells in the memory cell array into a voltage The second comparison circuit 17 that compares Vref1 and the output voltage VrefA of the first comparison circuit 16 and the output voltage VrefB of the second comparison circuit 17 are compared. It is configured to include a comparator circuit 18.

  In the third embodiment, as in the first embodiment, two reference levels Vref0 and Vref1 are used. However, since it is not necessary to generate a reference level Vref by an intermediate level between the two reference levels Vref0 and Vref1, the first level is used. A circuit such as the second current-voltage conversion circuit unit 52 shown in FIG. 14 of the embodiment is not necessary.

  In FIG. 19, when the voltage level Vm of the selected data line read from the desired memory cell is equal to or higher than the reference level Vref1, the output voltage VrefA of the first comparison circuit 16 and the output voltage of the second comparison circuit 17 Since the relationship of VrefB is as shown in the following equation 8, the output Vout of the sense circuit 15b is at a high level.

(Equation 8)
VrefA> VrefB

  Further, when the voltage level Vm of the selected data line read from the desired memory cell is equal to or lower than the reference level Vref0, the relationship between VrefA and VrefB is as shown in the following equation 9, so that the sense circuit The output Vout of 15b becomes a low level.

(Equation 9)
VrefA <VrefB

Hereinafter, another embodiment of the device of the present invention will be described.
In each of the above embodiments, the case where there is one memory cell array 10 is illustrated in FIGS. 1, 17 and 19, but in order to realize a large capacity memory, the array size of the memory cell array 10 needs to be increased. However, in the cross-point type memory cell array structure, as the array size increases, the read margin deteriorates and reading becomes impossible, so there is a maximum allowable size for the array size of the single memory cell array 10. Therefore, in order to realize a large capacity exceeding the maximum allowable size, for example, it is preferable to adopt a bank structure composed of a plurality of memory cell arrays as shown in FIG.

  In this case, it is not necessary to provide the reference memory cell arrays 20a and 20b separately for each bank (memory cell array), and the reference memory cell arrays 20a and 20b can be shared among a plurality of banks. Note that the array size of each bank and the array size of the reference memory cell arrays 20a and 20b are preferably the same.

  In the first embodiment, the case where one data line is selected from one memory cell array 10 and the data of one memory cell is read out is described in FIG. It may be configured to select and read data from a plurality of memory cells. In this case, it is necessary to provide the same number of sense circuits 15 as the number of memory cells to be read simultaneously, but one sense circuit 15 may be used when reading serially. When a plurality of sense circuits 15 are provided, the reference memory cell arrays 20 a and 20 b can be shared between the plurality of sense circuits 15.

  In the first embodiment, the current flowing through the selected data line at the time of reading the selected memory cell in the high resistance state becomes the maximum state depending on the distribution pattern of the electrical resistance state of the other non-selected memory cells. The first reference current generating circuit for realizing the current state and the current flowing through the selected data line at the time of reading the selected memory cell in the low resistance state depend on the distribution pattern of the electric resistance state of the other non-selected memory cells. The reference memory cell arrays 20a and 20b set in the pattern A and the pattern C, respectively, are used as the second reference current generating circuit that realizes the second current state that is the minimum state, and the first reference current generating circuit, As the second reference current generation circuit, the first current state and the second current state can be realized in different array sizes. File may be adopted Reference memory cell array. For example, a plurality of unselected memory cells having the same resistance state may be combined and combined.

  When adopting a bank structure composed of a plurality of memory cell arrays, the row voltage displacement suppression circuit 31 (see FIG. 2) employed in each of the above embodiments selects a memory cell array as shown in FIGS. It is preferable that each bank select transistor 70 (corresponding to the array select transistor) and the data line DL are inserted separately. In FIG. 20, a global data line GDL extends in the row direction and is connected to a data line DL in each bank (memory cell array) via a bank selection transistor 70 and a row voltage displacement suppression circuit 31, and a row read voltage supply circuit. 30 is connected to the global data line GDL. Therefore, in the bank structure shown in FIG. 20, in the data line drive circuit 11 shown in FIG. 2, the row read voltage supply circuit 30 and the row voltage displacement suppression circuit 31 are separated by the bank selection transistor 70.

  In the bank structure illustrated in FIG. 29, when the row read voltage supply circuit 30 and the row voltage displacement suppression circuit 31 of the data line drive circuit 11 are not separated by the bank selection transistor 70, the insertion position of the row voltage displacement suppression circuit 31 is used. As shown in FIG. 22, this is between the row read voltage supply circuit 30 and the global data line GDL. In this case, when the resistance value of one of the variable resistance elements connected to the data lines DL0 and DLm and the selected bit line BL is high and the other is low, a difference occurs in the currents Id0 and Idm flowing through the data lines DL0 and DLm. . Here, due to the voltage displacement suppression effect of the row voltage displacement suppression circuit 31, a large voltage difference does not occur between the voltages Vdg0 and Vdgm of the global data lines GDL, but between the voltages Vd0 and Vdm of the data lines DL0 and DLm. A voltage difference occurs. This voltage difference is caused by the difference in voltage drop between the source and drain of the bank selection transistor 70 due to the difference between the currents Id0 and Idm flowing through the bank selection transistor 70. That is, since the current on the variable resistance element side having the lower resistance value (Id0 in the example of FIG. 22) is large, the voltage drop due to the bank selection transistor 70 on the data line DL0 side becomes large, and Vd0 <Vdm. As a result, a sneak current from the line DLm to the data line DL0 is generated. That is, the voltage displacement suppression effect of the row voltage displacement suppression circuit 31 is reduced by the bank selection transistor 70 being interposed.

  On the other hand, as shown in FIGS. 20 and 21, when the row voltage displacement suppression circuit 31 is inserted between the bank selection transistor 70 and the data line DL, the voltages Vd0, DLm of the data lines DL0, DLm, Since the voltage displacement of Vdm is directly suppressed by the voltage displacement suppression effect of the row voltage displacement suppression circuit 31, the voltage difference (Vdm−Vd0) between the data lines DL0 and DLm is compared with the configuration shown in FIG. This reduces the sneak current caused by the voltage difference between the data lines DL0 and DLm.

  Next, FIG. 23 shows an example of the layout configuration in the bank structure in the case where a plurality of memory cell arrays are arranged in the column direction in the memory cell array configuration shown in FIGS.

  As shown in FIG. 23, the global data line GDL extends in the row direction and is connected to the data line DL in each bank (memory cell array) via the bank selection transistor 70 and the row voltage displacement suppression circuit 31 to read the row. The voltage supply circuit 30 is connected to the global data line GDL. Here, the odd-numbered global data line GDL is connected to the odd-numbered corresponding data line DL from one side of each bank, and the even-numbered global data line GDL is connected to the other side of each bank. To the even-numbered corresponding data line DL. The global bit line GBL extends in the column direction and is connected to the bit line BL in each bank via the bank selection transistor 70, and the bit line drive circuit 12 (see FIG. 3) is connected to the global bit line GBL. . Here, the odd-numbered global bit line GBL is connected to the odd-numbered corresponding bit line BL from one side of each bank, and the even-numbered global bit line GBL is connected to the other side of each bank. To the even-numbered corresponding bit line BL.

  In the case of the bit line drive circuit 12 having the circuit configuration shown in FIG. 3, the column read voltage supply circuit 40 and the column voltage displacement suppression circuit 41 have an integral configuration that cannot be separated, so that the layout as shown in FIG. It has a configuration. In order to suppress the decrease in the voltage displacement suppression effect of the column voltage displacement suppression circuit 41 in the same manner as the row voltage displacement suppression circuit 31, for example, the bit line drive circuit 12 is provided in units of banks, or the bit line drive circuit The twelve circuit configurations may be changed to match the hierarchical bit line structure. By using a bit line drive circuit adapted to such a hierarchical bit line structure, the column voltage displacement suppression circuit 41 can be directly connected to the bit lines of each bank.

  In each of the above embodiments, the row direction of the memory cell array is set to the horizontal direction in each figure, and the column direction is set to the vertical direction. However, the relationship between the rows and the columns can be exchanged. That is, at the time of reading, the sense circuit may be configured such that the current flowing through the selected column selection line can be detected separately from the current flowing through the non-selected column selection line. In each of the above embodiments, the column voltage displacement suppression circuit and the row voltage displacement suppression circuit are provided for both the column selection line and the row selection line of the memory cell array. The voltage displacement suppression circuit may be configured to include only one of them.

  In each of the above embodiments, the first voltage supplied to the selected bit line is set lower than the second voltage supplied to the unselected bit line and the data line, but the first voltage is set higher than the second voltage. It doesn't matter. Further, the first voltage and the second voltage may be voltages other than the ground voltage and the power supply voltage.

As described above in detail, in the device of the present invention, the data line drive circuit 11 includes the row read voltage supply circuit 30 and the bit line drive circuit 12 includes the column voltage displacement suppression circuit 41. Leakage current generated depending on the resistance value of the memory cell can be suppressed, and the read margin can be improved. In addition, with the improvement of the read margin, the read speed can be improved.

  According to the device of the present invention, for example, even when the array size in the memory cell array (bank) is 128 rows × 128 columns, a read margin of about several tens mV to 200 mV can be secured. Further, when one memory cell array (1 bank) is configured by 128 rows × 128 columns (16 kbits), a memory cell array region is configured by 8 banks × 8 banks of 64 banks, thereby allowing a 1 Mbit memory. Capacitance can be realized, which has a great effect on reducing the total area of the memory cell array.

1 is a circuit block diagram showing an embodiment of a semiconductor memory device according to the present invention. 1 is a circuit diagram showing an example of a data line drive circuit, a row read voltage supply circuit, and a row voltage displacement suppression circuit of a semiconductor memory device according to the present invention. 1 is a circuit diagram showing an example of a bit line drive circuit, a column read voltage supply circuit, and a column voltage displacement suppression circuit of a semiconductor memory device according to the present invention. Load characteristics with PMOS operating as a load resistance in the saturation region, IV characteristics of the memory cell array in various distribution patterns of resistance states of the memory cells in the memory cell array, and static characteristics indicating the output voltage of the row read voltage supply circuit Figure The figure explaining various distribution patterns of the resistance state of the memory cell in the cross-point type memory cell array The figure explaining the location dependence on the bit line of the selected memory cell in the memory cell array, and the figure showing the relationship between the distance between the selected memory cell and the bit line drive circuit and the bit line potential The figure explaining the location dependence on the data line of the selected memory cell in the memory cell array, and the figure showing the relationship between the distance between the selected memory cell and the data line drive circuit and the data line potential The figure which shows the modification by the difference in the position of the selection memory cell of the same distribution pattern as the pattern A shown in FIG. The figure which shows the modification by the difference in the position of the selection memory cell of the same distribution pattern as the pattern B shown in FIG. The figure which shows the modification by the difference in the position of the selection memory cell of the same distribution pattern as the pattern C shown in FIG. The figure which shows the modification by the difference in the position of the selection memory cell of the same distribution pattern as the pattern D shown in FIG. Load characteristics with PMOS operating as a load resistance in the linear region, IV characteristics of the memory cell array in various distribution patterns of resistance states of the memory cells in the memory cell array, and static characteristics indicating the output voltage of the row read voltage supply circuit Figure Static characteristic diagram showing IV characteristics of memory cell array when row voltage displacement suppression circuit and column voltage displacement suppression circuit are used 1 is a circuit block diagram showing an example of a sense circuit of a semiconductor memory device according to the present invention. The I-V characteristics of the PMOS load transistor shown in FIG. 2 and the I of the memory cell array in various distribution patterns of the resistance state of the memory cell in the memory cell array having the column voltage displacement suppression circuit shown in FIG. Static characteristic diagram showing -V characteristics 4 is a circuit block diagram showing another example of the sense circuit of the semiconductor memory device according to the present invention. The circuit block diagram which shows 2nd Embodiment of the semiconductor memory device based on this invention using the sense circuit shown in FIG. When the load characteristics of the data line drive circuit, the IV characteristics of the memory cell array in various distribution patterns of the resistance states of the memory cells in the memory cell array, and the output voltage of the data line drive circuit are input to the sense circuit shown in FIG. Static characteristic diagram showing the relationship of the tolerance range of the input inversion level of the sense circuit 4 is a circuit block diagram showing another example of the sense circuit of the semiconductor memory device according to the present invention. 1 is a circuit block diagram showing a memory cell array configuration capable of selecting a plurality of memory cell arrays in a bank unit of a semiconductor memory device according to the present invention; FIG. 20 is a circuit diagram showing a configuration example of a data line drive circuit in the memory cell array configuration of the semiconductor memory device according to the present invention shown in FIG. Circuit diagram showing another configuration example of a data line drive circuit in a memory cell array configuration capable of selecting a plurality of memory cell arrays in units of banks 20 is a circuit diagram showing a layout example when the memory cell array configuration of the semiconductor memory device according to the present invention shown in FIG. 20 is expanded in the column direction. A circuit diagram showing a circuit configuration of a memory cell array of a conventional cross-point memory, a setting level of a supply voltage to a data line and a bit line, and a current path In a memory cell array of a conventional cross-point memory, when reading the resistance value of the memory cell where the data line D0 and the bit line B0 cross each other, a circuit showing the voltage setting and current path of each data line and each bit line Figure A circuit diagram showing a current path of a leakage current generated when measuring a read current Id of a memory cell Md in a memory cell array of a conventional cross-point memory In the memory cell array of the conventional cross-point memory, the current path and direction of the leak current that occurs when measuring the read current Id1 of the memory cell Md1, and the leak current that occurs when measuring the read current Id2 of the memory cell Md2 Circuit diagram showing current path and direction The figure explaining the reason why leak current occurs in the memory cell array of the conventional cross-point memory A circuit block diagram showing a memory cell array configuration in which a memory cell array can be selected in units of banks Circuit diagram showing an example of a data line driver / amplifier circuit used in a memory cell array of a conventional cross-point memory Circuit diagram showing an example of a bit line drive circuit used in a memory cell array of a conventional cross-point memory In the memory cell array of the conventional cross-point memory, the voltage setting of each data line and each bit line and the current path when reading the memory cell in the high resistance state at the intersection of the data line D0 and the bit line B0 are shown. circuit diagram In the memory cell array of the conventional cross-point memory, the voltage setting of each data line and each bit line and the current path when reading the memory cell in the low resistance state where the data line D0 and the bit line B0 intersect are shown. circuit diagram

Explanation of symbols

10: Memory cell array 11: Data line drive circuit 12: Bit line drive circuit 13: Row decoder 14: Column decoder 15, 15b: Sense circuit 15a: Inverter circuit (sense circuit)
16: first comparison circuit 17: second comparison circuit 18: third comparison circuit 20a: reference memory cell array 20b: reference memory cell array 21: data line drive circuit 22: bit line drive circuit 24: column decoder 30: row read voltage supply Circuit 31: Row voltage displacement suppression circuit 32: N-channel MOSFET
33: Feedback circuit (inverter)
40: Column read voltage supply circuit 41: Column voltage displacement suppression circuit 42: P-channel MOSFET
43, 44: CMOS transfer gate 45: Column selection circuit 46: N-channel MOSFET
47: Feedback circuit (inverter)
51: First current-voltage conversion circuit unit 52: Second current-voltage conversion circuit unit 53: Comparison circuits 54, 55, 58: P-channel MOSFET
56, 57, 59, 60: N-channel MOSFET
70: Bank selection transistor (array selection transistor)
Vcc: power supply voltage Vss: ground voltage BL: bit line DL: data line GBL: global bit line GDL: global data line

Claims (23)

A plurality of memory cells composed of variable resistance elements that store information according to changes in electrical resistance are arranged in the row direction and the column direction, respectively, and a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction are provided. Each of the memory cells in the same row connects one end side of the variable resistance element to the same row selection line, and each of the memory cells in the same column has the same other end side of the variable resistance element. A semiconductor memory device having a memory cell array connected to a column selection line,
Each of the column selection lines includes a column read voltage supply circuit that supplies a predetermined first voltage when reading is selected and supplies a second voltage different from the first voltage when reading is not selected,
Each of the row selection lines includes a row read voltage supply circuit that supplies the second voltage at the time of reading,
A sense circuit for detecting a current flowing through the selected row selection line separately from a current flowing through the non-selected row selection line and detecting an electrical resistance state of the selected memory cell at the time of reading; Prepared,
A semiconductor memory device, comprising: a column voltage displacement suppression circuit that suppresses a displacement of a supplied voltage level for each of the unselected column selection lines at the time of reading.   In the column voltage displacement suppression circuit, one of a drain and a source is connected to the column selection line, the other is connected to the column readout voltage supply circuit, and the gate voltage of the MOSFET is set according to the voltage level of the column selection line. The semiconductor memory device according to claim 1, further comprising: a feedback circuit unit that adjusts the on-resistance of the MOSFET by changing.   3. The semiconductor memory device according to claim 1, further comprising a row voltage displacement suppression circuit that suppresses displacement of a supplied voltage level at least for the selected row selection line at the time of reading. .   3. The semiconductor memory device according to claim 1, further comprising a row voltage displacement suppression circuit that suppresses displacement of a supplied voltage level in each of the row selection lines during reading. A plurality of memory cells composed of variable resistance elements that store information according to changes in electrical resistance are arranged in the row direction and the column direction, respectively, and a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction are provided. Each of the memory cells in the same row connects one end side of the variable resistance element to the same row selection line, and each of the memory cells in the same column has the same other end side of the variable resistance element. A semiconductor memory device having a memory cell array connected to a column selection line,
Each of the column selection lines includes a column read voltage supply circuit that supplies a predetermined first voltage when reading is selected and supplies a second voltage different from the first voltage when reading is not selected,
Each of the row selection lines includes a row read voltage supply circuit that supplies the second voltage at the time of reading,
A sense circuit for detecting a current flowing through the selected row selection line separately from a current flowing through the non-selected row selection line and detecting an electrical resistance state of the selected memory cell at the time of reading; Prepared,
A semiconductor memory device comprising: a row voltage displacement suppression circuit that suppresses displacement of a supplied voltage level at least for the selected row selection line at the time of reading. A plurality of memory cells composed of variable resistance elements that store information according to changes in electrical resistance are arranged in the row direction and the column direction, respectively, and a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction are provided. Each of the memory cells in the same row connects one end side of the variable resistance element to the same row selection line, and each of the memory cells in the same column has the same other end side of the variable resistance element. A semiconductor memory device having a memory cell array connected to a column selection line,
Each of the column selection lines includes a column read voltage supply circuit that supplies a predetermined first voltage when reading is selected and supplies a second voltage different from the first voltage when reading is not selected,
Each of the row selection lines includes a row read voltage supply circuit that supplies the second voltage at the time of reading,
A sense circuit for detecting a current flowing through the selected row selection line separately from a current flowing through the non-selected row selection line and detecting an electrical resistance state of the selected memory cell at the time of reading; Prepared,
A semiconductor memory device comprising a row voltage displacement suppression circuit that suppresses displacement of a supplied voltage level in each of the row selection lines during reading.   In the row voltage displacement suppression circuit, one of a drain and a source is connected to the row selection line, the other is connected to the row read voltage supply circuit, and the gate voltage of the MOSFET is set according to the voltage level of the row selection line. The semiconductor memory device according to claim 3, further comprising: a feedback circuit unit that changes the on-resistance of the MOSFET by changing. A plurality of the memory cell arrays are arranged in at least the row direction,
The plurality of row selection lines of each memory cell array are connected to corresponding global row selection lines via array selection transistors for selecting the memory cell array, and the row read voltage supply circuit includes the array selection Each of the plurality of row selection lines of the memory cell array selected by the transistor is configured to be able to supply the second voltage via the global row selection line corresponding to each of the plurality of row selection lines;
8. The semiconductor memory device according to claim 3, wherein the row voltage displacement suppression circuit is provided separately between the row selection line and the array selection transistor.   The semiconductor memory device according to claim 1, wherein the memory cell includes an electrically rewritable nonvolatile variable resistance element.   10. The memory cell according to claim 1, wherein one memory cell is arranged at each intersection of the plurality of row selection lines and the plurality of column selection lines. 11. Semiconductor memory device.   When the first voltage is lower than the second voltage, the column read voltage supply circuit and the row read voltage supply circuit supply the second voltage via a P-channel MOSFET that operates in a saturation region, respectively. The semiconductor memory device according to claim 1, wherein: The sense circuit is
A current flowing through the selected row selection line;
The current flowing through the selected row selection line at the time of reading of the high resistance memory cell in which the electrical resistance of the selected memory cell is in the high resistance state is the electrical resistance state of the other non-selected memory cells in the memory array Current flowing through the selected row selection line at the time of reading from the low resistance memory cell in which the electrical resistance of the selected memory cell is in the low resistance state. A current in an intermediate state of the second current state that becomes a minimum state depending on a distribution pattern of electrical resistance states of the other non-selected memory cells in the memory array,
The semiconductor memory device according to claim 1, wherein the semiconductor memory devices are configured to be comparable with each other. The sense circuit is
A first current-voltage conversion circuit unit for converting a current flowing through the selected row selection line into a read voltage level;
A first reference current generating circuit that approximately realizes the first current state;
A second reference current generating circuit that approximately realizes the second current state;
A second current-voltage conversion circuit unit that converts a current in an intermediate state between the first current state and the second current state into a reference voltage level;
A comparison circuit for comparing the read voltage level and the reference voltage level;
The semiconductor memory device according to claim 12, comprising:   The semiconductor memory device according to claim 1, wherein the sense circuit includes only one or a plurality of stages of inverter circuits. The sense circuit is
A read voltage obtained by converting a current flowing through the selected row selection line into a voltage, and the row selection line selected at the time of reading the high resistance memory cell in which the electrical resistance of the selected memory cell is in a high resistance state. A first comparison circuit for comparing a first voltage obtained by converting a first current state in which a flowing current becomes a maximum state depending on a distribution pattern of electrical resistance states of other non-selected memory cells of the memory cell array into a voltage. When,
The read voltage and the current flowing through the row selection line selected at the time of reading of the low resistance memory cell in which the electrical resistance of the selected memory cell is in the low resistance state are other unselected memories in the memory cell array. A second comparison circuit for comparing a second voltage obtained by converting the second current state, which is a minimum state depending on the distribution pattern of the electric resistance state of the cell, into a voltage;
A third comparison circuit for comparing the output voltage of the first comparison circuit with the output voltage of the second comparison circuit;
The semiconductor memory device according to claim 1, comprising: A first reference current generation circuit that approximately realizes the first current state; and a second reference current generation circuit that approximately realizes the second current state;
Each of the first reference current generation circuit and the second reference current generation circuit includes a reference memory cell array having a configuration equivalent to the memory cell array including a reference memory cell including the same variable resistance element as the memory cell; A reference column read voltage supply circuit having a configuration equivalent to the column read voltage supply circuit, and a reference row read voltage supply circuit having a configuration equivalent to the row read voltage supply circuit,
The distribution pattern of the electrical resistance state of the reference memory cell in the reference memory cell array of the first reference current generation circuit is such that the current flowing through the row selection line of the selected reference memory cell array becomes the first current state. Set to distribution pattern,
The distribution pattern of the electrical resistance state of the reference memory cell in the reference memory cell array of the second reference current generation circuit is such that the current flowing through the row selection line of the selected reference memory cell array becomes the second current state. 14. The semiconductor memory device according to claim 12, wherein the semiconductor memory device is set to a distribution pattern. In the first distribution pattern, one row of the reference memory cells connected to one row selection line and one column of the reference memory cells connected to one column selection line have a high resistance, and the high resistance The reference memory cell in the region excluding the reference memory cell region is a distribution pattern having a low resistance,
In the second distribution pattern, one row of the reference memory cells connected to one row selection line and one column of the reference memory cells connected to one column selection line have low resistance, and the low resistance 17. The semiconductor memory device according to claim 16, wherein the reference memory cells in a region excluding the reference memory cell region have a distribution pattern having a high resistance. The high-resistance reference memory cell in the first distribution pattern is connected to a row selection line closest to the row voltage displacement suppression circuit and a column selection line closest to the column voltage displacement suppression circuit,
The low-resistance reference memory cell in the second distribution pattern is connected to a row selection line farthest from the row voltage displacement suppression circuit and a column selection line farthest from the column voltage displacement suppression circuit. The semiconductor memory device according to claim 17. A plurality of memory cells composed of variable resistance elements that store information according to changes in electrical resistance are arranged in the row direction and the column direction, respectively, and a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction are provided. Each of the memory cells in the same row connects one end side of the variable resistance element to the same row selection line, and each of the memory cells in the same column has the same other end side of the variable resistance element. A semiconductor memory device having a memory cell array connected to a column selection line,
The memory cell array includes a column read voltage supply circuit that supplies a predetermined first voltage to each of the column selection lines when reading is selected and supplies a second voltage different from the first voltage when reading is not selected. A row read voltage supply circuit for supplying the second voltage at the time of reading to each of the selection lines;
A high-resistance memory cell in which the current flowing through the selected row selection line is separated from the current flowing through the non-selected row selection line at the time of reading, and the electrical resistance of the selected memory cell is in a high-resistance state A first current state in which the current flowing through the selected row selection line at the time of reading is maximized depending on the distribution pattern of the electrical resistance states of the other non-selected memory cells in the memory array is selected. Further, the current flowing through the selected row selection line at the time of reading of the low resistance memory cell in which the electric resistance of the memory cell is in the low resistance state is a distribution of the electric resistance state of the other non-selected memory cells in the memory array. A sense circuit for detecting an electrical resistance state of the selected memory cell as compared with a current in an intermediate state of a second current state that becomes a minimum state depending on a pattern;
Each of the first reference current generation circuit that approximately realizes the first current state and the second reference current generation circuit that approximately realizes the second current state are formed from the same variable resistance element as the memory cell. A reference memory cell array having a configuration equivalent to the memory cell array, a reference column read voltage supply circuit having a configuration equivalent to the column read voltage supply circuit, and a configuration equivalent to the row read voltage supply circuit. A reference row read voltage supply circuit.
The distribution pattern of the electrical resistance state of the reference memory cell in the reference memory cell array of the first reference current generation circuit is such that the current flowing through the row selection line of the selected reference memory cell array becomes the first current state. Set to distribution pattern,
The distribution pattern of the electrical resistance state of the reference memory cell in the reference memory cell array of the second reference current generation circuit is such that the current flowing through the row selection line of the selected reference memory cell array becomes the second current state. A semiconductor memory device having a distribution pattern.   The number of the reference memory cell, the row selection line, and the column selection line of the reference memory cell array corresponds to the number of the memory cell, the row selection line, and the column selection line of the memory cell array. The semiconductor memory device according to claim 16, wherein the semiconductor memory device is the same as the semiconductor memory device according to claim 16. A plurality of the memory cell arrays;
17. The sense circuit for at least two of the plurality of memory cell arrays uses the first reference current generation circuit and the second reference current generation circuit in common. , 17, 18, 19 and 20. The semiconductor memory device according to any one of the above. In the first distribution pattern, one row of the reference memory cells connected to one row selection line and one column of the reference memory cells connected to one column selection line have a high resistance, and the high resistance The reference memory cell in the region excluding the reference memory cell region is a distribution pattern having a low resistance,
In the second distribution pattern, one row of the reference memory cells connected to one row selection line and one column of the reference memory cells connected to one column selection line have low resistance, and the low resistance The semiconductor memory device according to claim 19, wherein the reference memory cells in a region excluding the reference memory cell region have a high distribution pattern. The variable resistance element includes a metal oxide having a perovskite structure, a metal oxide containing a transition metal, a chalcogenide compound, a metal oxide such as STO (SrTiO ₃ ) or SZO (SrZrO ₃ ) or SRO (SrRuO ₃ ), and metal fine particles. The semiconductor memory device according to claim 1, comprising a material selected from a fluorine resin material, a conductive polymer, and a spin-dependent tunnel junction element.