JP2004234816A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up a writing speed and to reduce power consumption by preventing a period before a write current reaches a prescribed value from being prolonged by a parasitic capacitor. <P>SOLUTION: A semiconductor memory is equipped with a memory element which stores information, a constant current source 103 which is mounted in order to write information in the memory element by making a current flow through the memory element and a boost circuit 101 for charging a parasitic capacitor whilst an amount of current made to flow through the element by the constant current source reaches the amount of current required for writing information in the element at the prescribed position related with the element. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device that writes information to a memory element by flowing a current, and more particularly to a semiconductor memory device that writes information to a tunnel magnetoresistive element by a magnetic field generated by flowing a current.

  In recent years, with the rapid spread of mobile phones and the like, there is an increasing demand for memories having nonvolatile characteristics, large storage capacity, low voltage operation, and low power consumption characteristics. MRAM (Magnetic Random Access Memory) is expected as a memory having these characteristics. The memory element of the MRAM is composed of a TMR (tunnel magnetoresistive) element, and each TMR element has a structure as shown in FIG. 16, for example. The TMR element is configured by sequentially laminating a fixed ferromagnetic layer (pinned layer) 901, a tunnel insulating layer 902, and a free ferromagnetic layer (free layer) 903. The magnetization direction of the pinned layer 901 is fixed at the time of manufacture. On the other hand, the magnetization direction of the free layer 903 can be reversed by a magnetic field generated by the wiring current. For example, the current flowing through the bit line BL and the word line WL disposed above and below the TMR element is generated. It can be reversed by a magnetic field. “1” or “0” is assigned depending on the magnetization direction. When the relative directions of magnetization of the pinned layer 901 and the free layer 903 are parallel (“0” in FIG. 16), the electric resistance is small, and when the relative directions are antiparallel (“1” in FIG. 16), the electric resistance is large. By detecting this difference in electrical resistance, the state of the memory element can be read out.

A semiconductor memory device using the TMR element having such a configuration as a memory cell has a configuration in which a plurality of memory cells 904 are arranged in a matrix as shown in FIG. 17A, and above each memory cell. A plurality of bit lines BL905 extending in the horizontal direction and a plurality of word lines WL906 extending in the vertical direction below each memory cell are used as components. Each memory cell 904 is composed of the above-described TMR element, and a combination of magnetic fields H _Y and H _X generated when current flows through the bit line BL and the word line WL existing above and below the selected cell. When a predetermined condition is satisfied, the magnetization direction of the free layer can be reversed. The combination of the minimum magnetic fields necessary for this magnetization reversal forms a curve called an asteroid curve as shown in FIG. 17B (in FIG. 17B, reversal from “0” to “1” is considered). ing). When a magnetic field outside the asteroid curve (“Reversal” region and “Multiple Write” region) is applied, writing to the selected cell S is performed. For example, in FIG. 17B, when the X-direction magnetic field H _DX and the Y-direction magnetic field H _DY are added, the magnetic field vector (H _X , H _Y ) = (H _DX , H _DY ) in the selected cell S is in the inversion region. Therefore, magnetization reversal occurs. In other words, data reversal of “0” or “1” can be performed by reversing the magnetization direction. At this time, the selected bit line in the unselected memory cell U _X, U _Y of the selected word line, only the magnetic field H _DX to fit inside the asteroid curve ( "Retention" area), or only the H _DY exists Therefore, magnetization reversal does not occur. That is, selective writing is performed.

The magnetic fields (H _X , H _Y ) in FIG. 17B are based on the Ampere's law (I = H / 2πr, r is the distance between the wiring center and the magnetic material center), and the word line current I _DY and the bit line current I You can rewrite about _DX . The rewritten result is shown in FIG. Word line current I _DY, the flow bit line current I _DX current, a combination of the current in the selected cell _{S (I BL, I WL)} = (I DX, I DY) Because in the inversion region, the magnetization reversal occurs. In other words, data reversal of “0” or “1” can be performed by reversing the magnetization direction. At this time, only the currents I _DX and I _DY that fit inside the asteroid curve (the “hold” region) flow in the non-selected memory cells U _X and U _Y on the selected bit line and the selected word line. Magnetization reversal does not occur. That is, selective writing is performed.

However, in the case of the MRAM, as shown in FIG. 17A, since many non-selected cells are connected to the selected bit line BL905 and the selected word line WL906, when a current flows through the wiring, these non-selected cells You will receive a disturbing magnetic field. For example, when a write current in the lattice pattern region (“Multiple Write” region) in FIG. 17C is passed, current I _BL in unselected memory cell U _X , current I in unselected memory cell U _{Y Since WL} goes outside the asteroid curve, writing is also performed on the unselected memory cells U _X and U _Y. That is, erroneous writing occurs. Therefore, in order to perform selective writing, it is necessary to pass the current in the white portion “Reversal” region in FIG. 17C, and it is necessary to accurately adjust the write current value.

In addition, there are the following as prior art documents related to the present invention.
JP 2001-195878 A JP 2001-325791 A Japanese Patent Laid-Open No. 2002-008367 JP 2002-074974 A JP 2002-170374 A JP 2002-170375 A JP 2002-170376 A JP 2002-197852 A

  Since the magnetization reversal time of the magnetic material is as high as 1 nanosecond or less, one of the advantages of MRAM is that high-speed writing is possible in principle. However, as described in the above prior art, since the write current of the MRAM needs to be accurate, it is necessary to use a constant current source as the write current source. However, in the conventional constant current write circuit as described above, immediately after the write current source is turned on, charges are accumulated in the parasitic capacitors existing in the wiring and the selector. A certain time is required until a constant current flows to the position of the selected cell of the selected word line WL906. For this reason, there has been a problem that power consumption during writing increases. This problem will be described with reference to FIGS. FIG. 18 shows a memory cell array (4 × 4 cells are shown in the figure), and constant current source circuits are prepared on the X side and the Y side, respectively. Ideally, as shown in FIG. 19A, the constant currents ICX and ICY output from the constant current source flow as constant currents IAX and IAY as they are in the array. For this reason, it is expected that the write current rises instantaneously. However, in an actual circuit, there exist parasitic capacitors CLX, CLY, CX1,..., CXm, CY1,... CYm as shown in FIG. Therefore, even if the constant current source supplies the constant currents ICX and ICY outside the array, the current in the array is consumed to charge the parasitic capacitor immediately after the current is supplied. It becomes dull as shown in FIG. In particular, in the case of MRAM, since a current below a specific value does not have a writing capability, it is necessary to wait until the current value becomes a required value. For this reason, not only high-speed writing becomes difficult, but a wasteful current is generated as shown by the hatched portion in FIG. For this reason, particularly in the case of the MRAM, there is a problem that the power consumption increases due to the fact that the write current value is large (several mA).

This problem becomes more prominent as the memory capacity increases. FIG. 20 is a block diagram showing a configuration when a current is supplied to a large storage capacity array using a conventional constant current source circuit. It is assumed that the large storage capacity array is composed of N × M small arrays. In order to increase the memory occupation area, the current source on the X side writes to the M small arrays in the same row, and the current source on the Y side writes to the N small arrays in the same column. It has become. For this reason, for example, with respect to the X-side write current, the current path I when a current is passed through the small array (1, 1) and the current path M when a current is passed through the small array (1, M) are: The length of the route is different. Since these current paths are accompanied by the wiring resistance Rp and the parasitic capacitor Cp, a delay time given by the time constant Δt = Cp Rp is generated even when a constant current is passed. When the current path is different, not only the wiring resistance and the parasitic capacitor are different, but also the amount of electric charge required to charge the parasitic capacitor is different depending on the wiring potential. This difference will be described with reference to FIG. The terminal potential V _0, the combined resistance of the small array 921 and the selector 922 r, a capacitance of synthesis parasitic capacitors of small array 921 and the selector 922 and C _A, assuming that selected small array k (1 <k <M) The amount of charge accumulated in the parasitic capacitor when the current I flows is

となり、アレイ位置ｋに関して２次式、電流値Ｉに関して１次式となる。

Thus, a quadratic expression for the array position k and a linear expression for the current value I are obtained.

  However, it is difficult to flow the write current in a short time by minimizing the influence of the parasitic capacitor depending on the location of the selected array only by using the conventional constant current source. Further, since the size of the capacitance of the parasitic capacitor also depends on the write current value, it is difficult to minimize the influence of the parasitic capacitor in accordance with the actual current value to flow and to flow the write current in a short time. Furthermore, since the parasitic capacitor that actually accompanies may vary from chip to chip, it is difficult to minimize the influence of the parasitic capacitor and allow the write current to flow in a short time.

  An object of the present invention is to increase the writing speed and reduce the power consumption by preventing the parasitic capacitor from prolonging the time until the write current reaches a predetermined value.

  In order to solve the above problems, a semiconductor memory device of the present invention is a circuit in which a write current source path accumulates charges during a write standby and instantaneously releases the charges during a write operation (hereinafter, referred to as a circuit). (Referred to as a boost circuit). By using this boost circuit, it is possible to instantaneously charge the parasitic capacitor that exists in the wiring and selector gate. As a result, the current flowing from the constant current source circuit that exists separately from the boost circuit flows to the parasitic capacitor. Since the amount to be charged can be reduced, the write current can rise in a short time. As a result, writing can be performed in a short time, and an increase in power consumption can be prevented.

  The boost circuit of the semiconductor memory device includes a plurality of boost capacitors and a capacitor selector, and has a configuration in which the capacitance can be selected depending on the location of the cell array and the current value. It is the structure which can give an effect in writing.

  Furthermore, the boost circuit of this semiconductor memory device divides the boost capacitor in a geometric series according to the selection pattern, so that all the capacitor capacitors for boost are used at the time of maximum boost (farthest array write, maximum current). It becomes the composition which is done. For this reason, there is no waste in the area occupied by the boost capacitor, and the area occupied by the array can be increased.

  According to the present invention, a storage element for storing information, a constant current source provided for writing information to the storage element by flowing current, and the constant current source at a predetermined position associated with the storage element And a boost circuit for charging a parasitic capacitor until the amount of current passed by the capacitor reaches the amount of current necessary to write information to the storage element. Is provided.

  In the semiconductor memory device, the storage element may be a tunnel magnetoresistive element, and the predetermined position may be a position where a magnetic field due to current is applied to the tunnel magnetoresistive element.

  In the semiconductor memory device, the boost circuit may include a capacitor that accumulates electric charge for charging the parasitic capacitor.

  The semiconductor memory device may further include a circuit for setting a voltage between both electrodes of the capacitor to a power supply voltage or higher.

  In the semiconductor memory device described above, the capacitor may include a plurality of capacitors, and the boost circuit includes a switching unit that switches a capacitor used for charging according to an amount of charge necessary to charge the parasitic capacitor. May be.

  In the semiconductor memory device, the switching unit may switch a combination of capacitors used for charging according to an amount of electric charge necessary for charging the parasitic capacitor.

  In the semiconductor memory device, at least some of the plurality of capacitors may have a geometric series relationship with each other.

  In the above semiconductor memory device, the capacitance of at least some of the plurality of capacitors may be determined according to the capacitance of the parasitic capacitor depending on the amount of current necessary for writing information to the storage element. Good.

  In the above semiconductor memory device, the capacitance of at least a part of the plurality of capacitors may be determined according to the capacitance of the parasitic capacitor depending on the position of the storage element.

  In the semiconductor memory device described above, the capacitance of at least some of the plurality of capacitors may be determined according to the capacitance of the parasitic capacitor depending on process conditions.

  Since the semiconductor memory device of the present invention has the circulating means for returning the charge of the parasitic capacitance existing in the current path to the node for storing the charge of the boost circuit, an MRAM with low current consumption can be obtained.

  In the semiconductor memory device of the present invention, since the time for accumulating charges in the boost circuit is set after the end of the activation period of the current source, the constant current source circuit can be stably operated, and thus the yield can be increased. A high MRAM can be obtained.

  Since the semiconductor memory device of the present invention has charge holding means for holding a part of the charge of the parasitic capacitance existing in the current path depending on the history of the operation mode and suppressing the discharge of the boost circuit, the current consumption is small. MRAM can be obtained.

  According to the present invention, the capacitor is charged from the power supply during standby, and the charge accumulated in the capacitor is discharged during operation, so that the parasitic capacitor is charged in a short time and the writing time is shortened. Can do. In general, the size of these parasitic capacitors depends on the position and current value of the write cell, but a plurality of capacitor arrays and a capacitor selector for selecting an appropriate capacitor are added to the write constant current source circuit. Thus, the parasitic capacitor can be charged at an appropriate speed. That is, since high-speed writing can be realized, it is particularly effective for increasing the storage capacity of the MRAM.

  In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[First Embodiment]
A semiconductor memory device according to a first embodiment of the present invention will be described.

FIG. 1 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment. In the X-side boost circuit 101 of FIG. 1, one end of the boost capacitor CBX is grounded, and the other end is connected to the PMOS transistor MSX and the PMOS transistor MBX via the terminal VBX. The other end of the PMOS transistor MBX is connected to the power supply voltage Vdd. In boost standby (VBSTX = L level (GND)), the PMOS transistor MSX is off and the PMOS transistor MBX is on, so the charge QB = CBX × Vdd is stored in the boost capacitor CBX. The same applies to the Y-side boost circuit 102. The X-side write constant current circuit 103 and the Y-side write constant current circuit 104 are current sources having a large output impedance, and can pass a constant current without being affected by wiring resistance or the like (this setting) The current value finally becomes the current value desired to flow through the cell array). The configuration of the write constant current circuits 103 and 104 can be realized, for example, by making a cascode connection of transistors as shown in FIG. Input voltages Vb1 and Vb2 to the gates of the PMOS transistors are voltages that enable all transistors to operate in the saturation region, and are generated by a bias circuit. The current value can be set by switching the selection switches SW1,..., SWn (logical product of the write start signal WENX and the current selection signal). Since consisting FIG n bits in 2, the current sources in binary, ^{2 n} as (i, 2i, 3i, ... , (2 n -1) it) will be able to set the current value.

  The operation and effect of the constant current control circuit will be described with reference to timing charts shown in FIGS. The operation on the X side will be mainly described, but it is clear that the same is true on the Y side.

  When the constant current source circuit is activated and the signal WENX and the signal VBSTX are switched from the L level to the H level (Vdd), the PMOS transistor MBX is turned off and the PMOS transistor MSX is turned on. Since the potential of the node VBX is substantially the power supply voltage Vdd and the potential of the wiring NLX is a potential lower than this, for example, GND, the charge accumulated in the boost capacitor CBX suddenly flows to the selection wiring. This current is an instantaneous overshoot current reflecting the discharge phenomenon, and the current flows for several nanoseconds while charging the parasitic capacitors CLX, CX1,..., CXm. Eventually, when the potential of the node VBX and the wiring potential NLX become equal, the flow of the boost current stops. This state is indicated by a current waveform IBX in FIG. While the signal VBSTX is at the H level, the potential drop of ΔVBX occurs in the node VBX. On the contrary, the potential NLX of the selected wiring rises from the GND potential to Vdd−ΔVBX.

  If the boost circuit 101 is off, the current from the X-side write constant current source circuit 103 flows into the parasitic capacitor, so that the current IAX at the end of the wiring becomes dull (see FIG. 3). (See (B) in IAX). However, when the boost circuit 101 is on, the parasitic capacitor can be charged with the boost current IBX as described above, so that the dullness of the current waveform is reduced. If the capacity of the boost capacitor CBX is appropriately designed, the current IAX = ICX + IBX that actually flows through the cell array can be started up in a short time (about 2 nanoseconds) like the signal in the bottom row of FIG. it can. Therefore, writing is completed in a short time, and an increase in power consumption can be prevented.

[Second Embodiment]
A semiconductor memory device according to a second embodiment of the invention will be described. In the second embodiment, by increasing the voltage applied to the boost capacitors CBX and CBY described in the first embodiment, the amount of charge that can be accumulated is increased, and the writing time is further shortened. It is an object. Further, according to the present circuit configuration, the amount of charge per unit area of the capacitor stored in the boost capacitors CBX and CBY increases, so that there is an advantage that the areas of the boost capacitors CBX and CBY can be reduced.

First, the operation of the booster circuit will be described with reference to FIG. When the threshold voltage of the diode is Vt, the potential of the input terminal A1 is V (A1) = 0, the potential of the output terminal VBT is V (VBT) = Vdd−2Vt, and the potential of the node A2 is V (A2) = Vdd-Vt. When V (A1) = Vdd in this state, since the coupling of the capacitor _{C B,} the potential of the node A2 V (A2) attempts to increase the moment 2 Vdd-Vt (where that is discharged through the same time diode D2, The actual potential is 2Vdd-Vt or less). Thus, the diode D1 is off, D2 is turned on, the stabilizing capacitor _{C L} is paired charged. For this reason, the output voltage VBT rises. Then at V (A1) = GND, to drop to the potential for a moment GND nearby nodes A2, diode D1 is turned on, until D2 is turned off, the V (A2) = Vdd-Vt , the capacitor C _B Is charged. In the same manner, when the periodic pulse voltage is input to the node A1, stabilizing capacitor C _B is V (A1) = GND time is charged, V (A1) = Vdd when is discharged. Eventually, V (A2) -Vt = current flows from A2 until the VBT to the output terminal VBT, charges the stabilizing capacitor _{C L.} The output potential at this time is VBT = 2Vdd−2Vt.

  Next, the operation of the level shift circuit will be described with reference to FIG. In the level shift circuit of FIG. 4B, when the input terminal IN is at the L level, the NMOS transistor MN1 and the PMOS transistor MP2 are turned on, and the NMOS transistor MN2 and the PMOS transistor MP1 are turned off, so that the output potential OUT is at the L level. It becomes. On the other hand, when the input terminal IN is at the H level, the NMOS transistor MN2 and the PMOS transistor MP1 are turned on, and the NMOS transistor MN1 and the PMOS transistor MP2 are turned off, so that the output potential OUT becomes VBT. That is, level conversion from Vdd to VBT is performed.

  FIG. 5 is a block diagram showing a configuration of the semiconductor memory device according to the second embodiment. In the X-side boost circuit 101B of FIG. 5, one end of the boost capacitor CBX is grounded, and the other end is connected to the transistors MSX and MBX via the terminal VBX. The other end of the transistor MBX is connected to a boosted voltage VBT obtained by boosting the power supply voltage Vdd by the booster circuit 101B-1. Further, the gate voltages of the PMOS transistors MSX and MBX need to be VBT in order to prevent current from leaking when the transistor is off. Therefore, the power supply voltage of the inverter 101B-2 that controls the gate voltage of the PMOS transistor MSX is VBT, and the input voltage of the gate of the PMOS transistor MBX is VBT obtained by converting Vdd by the level shift circuit 101B-3. During boost standby (VBSTX = L level), the PMOS transistor MSX is off and MBX is on, so that the charge QB = CBX × VBT is stored in the boost capacitor CBX. The same applies to the Y-side boost circuit 102B. The X-side write constant current circuit 103 and the Y-side write constant current circuit 104 are current sources having a large output impedance, and can pass a constant current without being affected by wiring resistance or the like (this setting) The current value finally becomes the current value desired to flow through the cell array). This configuration can be realized, for example, by making a cascode connection of transistors as shown in FIG.

  The operation of this circuit will be described with reference to timing charts shown in FIGS. The operation on the X side will be mainly described, but it is clear that the same is true on the Y side.

  When the constant current source circuit 103 enters an operating state and the write start signal WENX and the boost start signal VBSTX are switched from the L level to the H level, the PMOS transistor MBX is turned off and the PMOS transistor MSX is turned on. Since the potential of the node VBX immediately before the switching is almost the boosted voltage VBT and the potential of the wiring NLX is a voltage lower than this, for example, the ground potential, the potential is accumulated in the boost capacitor CBX at the moment when the MSX is turned on. The charged charges suddenly flow to the selected wiring. This current is an instantaneous overshoot current, and the current flows for several nanoseconds while charging the parasitic capacitors CLX, CX1,..., CXm. When the potential of the node VBX is equal to the wiring potential NLX, the flow of the boost current stops. This state is shown by the current waveform in FIG. While the signal VBSTX is on, the potential drop of ΔVBX occurs in the node VBX. On the contrary, the potential NLX of the selected wiring rises from GND to VBT−ΔVBX.

  If the boost circuit 101B is off, the current from the X-side write constant current source circuit 103 flows into the parasitic capacitor, so that the rise in the array current IAX is slow (FIG. 6B). See inside). However, when the boost circuit 101B is turned on, since the parasitic capacitor can be charged with the boost current IBX as described above, the dullness of the current waveform is reduced. If the capacity of the boost capacitor CBX is appropriately designed, the current IAX = ICX + IBX that actually flows through the cell array can be raised in a short time (about 2 nanoseconds) as shown in the bottom row of FIG. . Therefore, writing is completed in a short time, and an increase in power consumption can be prevented.

[Third Embodiment]
A semiconductor memory device according to a third embodiment of the present invention will be described.

  In the third embodiment, a method of applying a current boost circuit to the large storage capacity array of FIG. 20 is described. FIG. 7 shows a write circuit diagram used in this embodiment. X-side current boost capacitor array 111 and X-side capacitor selector 112 are connected to X-side main wiring 113, and Y-side current boost capacitor array 114 and capacitor selector 115 are connected to Y-side main wiring 116. It is a feature of the third embodiment that they are connected. In addition, the switching of writing “0” and “1” is performed by switching the writing current direction on the Y side, so that a boost current can be applied to the bidirectional writing current, A capacitor array and a capacitor selector of L and R) are prepared. Since the X-side write and Y-side write operations are basically the same, only the X-side write will be described below.

  Assume that the X-side write constant current source 103 shown in FIG. 7 can output n current values of IX1, IX2,. This is because the magnetization reversal current of the MRAM varies depending on the process conditions and the designed current value may not be the optimum current value, and it is necessary to adjust the current value at the time of manufacture and shipment. Since the parasitic capacitor Qk changes according to the equation (1) according to the n write current values, it is necessary to prepare n current boost capacitors. In addition, although M small arrays XA1,..., XAM are arranged in the X direction, the parasitic capacitor Qk varies according to the equation (1) depending on the X direction write array position k (k = 1, 2,..., M). Therefore, it is necessary to prepare M current boost capacitors. Furthermore, since the actual parasitic capacitor may be different from the design value depending on the process conditions and the like, it is necessary to correct the current boost amount. For this purpose, it is necessary to prepare s boost capacitors. From the above requirements, if the X-side capacitor array 111 in each row of FIG. 7 is configured with M × n × s capacitors, the area occupied by the current boost capacitors may become enormous.

  However, it is possible to approximate the floating capacitor equation (1) by using the charge charged in all the boost capacitors at the time of maximum boost (when the current value is maximum, when selecting the farthest array, when the correction boost amount is maximum). If the relationship between capacitors is made a geometric series, the number of boost capacitors can be reduced, and therefore the area occupied by the boost capacitors can be reduced. For example, in the present embodiment, the block shown in FIG. 8 is used as the block of the X-side capacitor array and the X-side capacitor selector (the same configuration is possible on the Y side). The blocks shown in FIG. 8 are prepared for each row of the array. Here, the number of X-direction write array positions M = 4, the number of current values n = 4, and the number of correction values s = 4.

  Then, in accordance with the X-direction write array position number M = 4, the capacitance of the boost capacitor is adjusted at the terminals XA2 to XA4. As is apparent from the configuration of the logic gate that controls the terminal “ARRAY” in FIG. 8, when an array having an X-direction position of 1 and a Y-direction position of j is selected and the write start signal WENX becomes H level, Capacitors # 1 to # 6 connected to the capacitor selector (A) are candidates for use, an array having an X-direction position of 2 and a Y-direction position of j is selected, and the write start signal WENX is at the H level. In some cases, capacitors # 1 to # 6 connected to the capacitor selector (A) and capacitors # 7 to # 14 connected to the capacitor selector (B) are candidates for use, and the position in the X direction is 3 and the position in the Y direction is When the array of j is selected and the write start signal WENX becomes H level, capacitors # 1 to # 6 connected to the capacitor selector (A), the capacitor selector Capacitors # 7 to # 14 connected to B) and capacitors # 13 to # 18 connected to the capacitor selector (C) are candidates for use, and an array having an X-direction position of 4 and a Y-direction position of j is selected. When the write start signal WENX becomes H level, capacitors # 1 to # 6 connected to the capacitor selector (A), capacitors # 7 to # 14 connected to the capacitor selector (B), capacitor selector ( Capacitors # 13 to # 18 connected to C) and capacitors # 19 to # 24 connected to the capacitor selector (D) are use candidate capacitors.

  Along with the number of current values n = 4, a capacitor to be actually used is selected from the capacitors connected to the capacitor selectors at the terminals I1 and I2. In addition, with the correction value number s = 4, a capacitor to be actually used is selected from the capacitors connected to each capacitor selector at the terminals S1 and S2. Together, these are used to select a capacitor to be actually used among the capacitors connected to each capacitor selector at terminals I1, I2, S1, and S2. Since there are # 1 to # 24 boost capacitors, the total number of boost capacitors is 24. Since M × n × s = 4 × 4 × 4 = 64, it can be seen that the number of boost capacitors is reduced as compared with this. Boost current output terminals of each capacitor selector are IB1, IB2, and IB3, which are connected to the X-side main wiring 113 (corresponding to the wiring NLX). Therefore, the current output from the terminals IB1, IB2, and IB3 is added to the adjusted constant current output from the X-side constant current source 103. In FIG. 8, the transistor sizes in the capacitor selectors (A) to (D) are not particularly defined, but MBXj, MSXj (j = 1,..., 6) according to the size of the current boost capacitor (see FIG. 9). It is easy to adjust the gate width etc.).

  Each capacitor selector 121 is shown in FIG. 9, and the capacitor array is shown in FIG. The “ARRAY” terminal in FIG. 9 corresponds to the “ARRAY” terminal shown in FIG.

  The “I1” and “I2” terminals in FIG. 9 correspond to the “I1” and “I2” terminals shown in FIG. 8, and the boost amount is set according to the formula (1) according to the adjusted write constant current value. Used to adjust. For example, when I1 = L and I2 = L, the boost capacitor (# 1, # 7, # 13 or # 19) connected to the output terminal C1 in FIG. 9 and the boost capacitor connected to the output terminal C2 The capacitor (# 2, # 8, # 14 or # 20) is the selection candidate T. When I1 = H and I2 = L, the boost capacitor (# 1, # 7, # 13 or # 19) connected to the output terminal C1 in FIG. 9, and the boost capacitor connected to the output terminal C2 ( # 2, # 8, # 14 or # 20), a boost capacitor (# 3, # 9, # 15 or # 21) connected to the output terminal C3 and a boost capacitor (# 4) connected to the output terminal C4 , # 10, # 16 or # 22) are selection candidates. When I1 = L and I2 = H, the boost capacitor (# 1, # 7, # 13 or # 19) connected to the output terminal C1 in FIG. 9, and the boost capacitor connected to the output terminal C2 ( # 2, # 8, # 14 or # 20), a boost capacitor (# 5, # 11, # 17 or # 23) connected to the output terminal C5 and a boost capacitor (# 6) connected to the output terminal C4 , # 12, # 18 or # 24) are selection candidates. When I1 = H and I2 = H, the boost capacitor (# 1, # 7, # 13 or # 19) connected to the output terminal C1 in FIG. 9 and the boost capacitor connected to the output terminal C2 ( # 2, # 8, # 14 or # 20), a boost capacitor (# 3, # 9, # 15 or # 21) connected to the output terminal C3 and a boost capacitor (# 4) connected to the output terminal C4 , # 10, # 16 or # 22), a boost capacitor (# 5, # 11, # 17 or # 23) connected to the output terminal C5 and a boost capacitor (# 6, # 23) connected to the output terminal C4 12, # 18 or # 24) are selection candidates.

  The “S1” and “S2” terminals in FIG. 9 correspond to the “S1” and “S2” terminals shown in FIG. 8 and are used to compensate the process condition dependency of the parasitic capacitor Qk. For example, when S1 = L and S2 = L, the boost capacitor is not selected. When S1 = H and S2 = L, the boost capacitor (# 1, # 7, # 13 or # 19) connected to the output terminal C1 in FIG. 9 and the boost capacitor connected to the output terminal C3 ( # 3, # 9, # 15 or # 21) and the boost capacitor (# 5, # 11, # 17 or # 23) connected to the output terminal C5 are selection candidates. When S1 = L and S2 = H, the boost capacitor (# 2, # 8, # 14 or # 20) connected to the output terminal C2 in FIG. 9 and the boost capacitor connected to the output terminal C4 ( # 4, # 10, # 16 or # 22) and the boost capacitor (# 6, # 12, # 18 or # 24) connected to the output terminal C6 are selection candidates. When I1 = H and I2 = H, the boost capacitor (# 1, # 7, # 13 or # 19) connected to the output terminal C1 in FIG. 9 and the boost capacitor connected to the output terminal C2 ( # 2, # 8, # 14 or # 20) and a boost capacitor (# 3, # 9, # 15 or # 21) connected to the output terminal C3, a boost capacitor (# 4) connected to the output terminal C4 , # 10, # 16 or # 22), a boost capacitor connected to the output terminal C5 (# 5, # 11, # 17 or # 23) and a boost capacitor connected to the output terminal C6 (# 6, # 22) 12, # 18 or # 24) are selection candidates.

  A boost capacitor obtained by taking the logical product of the above three types of selection candidates is actually used. That is, an optimum boost capacitor is selected by a combination of the above XAj (j = (1), 2,..., 4), I1, I2, S1, and S2. All combinations are shown in FIG. In FIG. 11, I (j) = I (I1 + 2 × I2), A (j) = XAj, S (j) = S (S1 + 2 × S2) (however, L = 0, H for quantification) = 1). For example, when I1 = 1 and I2 = 0, I (j) = I (1 + 2 × 0) = I (1), and when XA1, A (j) = A (1), S1 = 1, S2 = When 0, S (j) = S (1 + 2 × 0) = S (1).

  There are 24 capacities # 1 to # 24, which are divided as shown in FIG. The total capacitance is 20.4 pF, and all boost capacitors are used during maximum boost (described above). When boost capacitors are prepared for (small array number M) × (current value n ways) × (boost adjustment 4 ways) = 4 × 4 × 4 = 64 ways, the total capacity of 306.8 pF in FIG. Necessary. That is, in this embodiment, the use area can be reduced to about 6.6%.

  Referring to FIG. 10, the width of # 1 + # 2: the width of # 3 + # 4: the width of # 5 + # 6 = 1: 1: 2, and the width of # 3 + # 4 and the width of # 5 + # 6 are equal. It is related to the ratio series. # 1 width: # 2 width = 1: 2, and # 1 width and # 2 width are in a geometric series relationship. The width of # 3: the width of # 4 = 1: 2, and the width of # 3 and the width of # 4 have a geometric series relationship. The width of # 5: the width of # 6 = 1: 2, and the width of # 5 and the width of # 6 are in a relation of geometric series. # 1 height: # 7 height: # 13 height: # 19 height = 4: 1: 2: 4, # 7 height, # 13 height and # 19 height S is in a geometric series relationship.

  FIG. 12 shows a simulation result when a write current having a set value of 8 mA is supplied to an MRAM cell array having a capacity of 1 Mbit. When the write current of 8 mA continues for 6 nanoseconds, the write cell is written, but when the write current is less than 8 mA, the write cell cannot be written. When the writing time after the current value reaches 8 mA is 5 nanoseconds and the boost circuit is not used (A), it takes about 80 nanoseconds as the time for supplying the writing current. Here, about 70% (shaded portion) is a wasteful current. On the other hand, when an appropriate boost current is used (B), the writing time can be reduced to about 15 nanoseconds, and the wasteful current is also about 40% (shaded area). However, if the boost amount is large, a current greater than or equal to a desired current (8 mA in this case) flows and causes erroneous writing. Therefore, an accurate capacity design is required. In the case of the present invention, the boost amount can be adjusted using the capacitance adjustment terminal of FIG.

[Fourth Embodiment]
A semiconductor memory device according to a fourth embodiment of the present invention will be described.

  FIG. 13 shows a circuit diagram of the fourth embodiment 101 of the present invention. In this figure, only the circuit on the X side is taken out for easy explanation. S1 to S6 represent signals, and / S5 and / S6 represent inverted signals of S5 and S6, respectively. N1 and N2 represent node potentials.

  Referring to FIG. 14, the current supply from the boost capacitor ends at time t100, but unlike the first embodiment, the boost capacitor is not charged immediately. Therefore, unlike the first embodiment, the signal S1 is separated from the signal VBSTX. When the node (VBX) of the boost circuit is charged, current flows out from the power supply Vdd, thereby generating power supply noise. This power supply noise reduces the accuracy of the constant current of the X-side write constant current source circuit that uses the same power supply Vdd. In this embodiment, since the boost capacitor is not charged during the operation of the constant current source circuit, this problem does not occur.

  When the constant current source circuit stops at time t101, the node NLX is not reset and holds a potential (charge). Next, at time t102, the signal S3 becomes “Low”, and the node N1 enters a floating state. Next, at time t103, the signal NLX electrically connects the node NLX and the node N1, and charges are transferred from the node NLX to N1. After N1 becomes floating again at time t104, the node N2 is brought into floating state at time t105. Next, at time t106, the node N2 and the node NLX are electrically connected. At this time, since the node N1 is floating, the potential of the node NLX is increased by the coupling of the capacitor CRX. Next, at time t107, the signal S2 is activated and charges are transferred from the node N1 to the node NLX. At this time, since the potential of the node NLX decreases due to the coupling of the capacitive element CRX, the charge at the node NLX is substantially transferred to the node VBX of the boost circuit. Each signal is reset between times t108 and t110. Finally, the node VBX is charged to the potential of the power supply Vdd at time t111, but the power required for charging is smaller than that in the first embodiment.

[Fifth Embodiment]
A semiconductor memory device according to a fifth embodiment of the present invention will be described.

    A circuit diagram of the fifth embodiment of the present invention is shown in FIG. In the present embodiment, even when the write mode ends, the signal S10 is not activated, so the node NLX is not reset and the potential of the node NLX does not become the ground potential. Although the reset transistor M103 is omitted in the drawings of the first to fourth embodiments, it is clear from the operation waveform that a circuit having such an action exists. If the reset is not performed, charge is held in the parasitic capacitance of the NLX. When the writing mode is continued after the writing mode, the operation mode determination circuit 105 detects continuous writing, sets the continuous detection signal S11 to “Low”, and does not activate the boost capacitor. This is because NLX is already charged and does not need to be charged. In this case, power for charging the boost capacity is saved. When the operation mode determination circuit 105 determines the read mode, the signal S10 is activated and the node NLX is reset.

  The present invention can be used for a write operation in an MRAM.

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a constant current source circuit used in a semiconductor memory device according to a first embodiment of the present invention. 3 is a timing chart showing an operation during writing of the semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a circuit diagram showing an example of a booster circuit and a level shift circuit used in a semiconductor memory device according to a second embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor memory device by the 2nd Embodiment of this invention. 7 is a timing chart showing an operation at the time of writing in the semiconductor memory device according to the second embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor memory device by the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the boost circuit used with the semiconductor memory device by the 3rd Embodiment of this invention. FIG. 9 is a circuit diagram showing a configuration of a capacitor selector in the boost circuit shown in FIG. 8. It is a capacity | capacitance block diagram which shows the division | segmentation method of the current boost capacity | capacitance in the 3rd Embodiment of this invention. It is a table | surface which shows the selection method of the current boost capacity | capacitance in the 3rd Embodiment of this invention. It is a comparison figure of the simulation waveform of the current which shows the effect of the present invention. It is a block diagram which shows the structure of the semiconductor memory device by the 4th Embodiment of this invention. 14 is a timing chart showing an operation at the time of writing in the semiconductor memory device according to the fourth embodiment of the present invention; It is a block diagram which shows the structure of the semiconductor memory device by the 5th Embodiment of this invention. It is a figure which shows the structure of a TMR memory cell. (A) is a plan view showing a memory cell array, (B) is a graph showing an asteroid curve by magnetic field display, and (C) is a graph showing an asteroid curve by current display. It is a block diagram which shows the structure of the semiconductor memory device by a prior art example. It is a graph which shows the write-in current waveform in the semiconductor memory device by a prior art example. It is a block diagram which shows the structure of the semiconductor memory device by a prior art example. It is a circuit diagram which shows the influence of the parasitic capacitor in a large storage capacity array.

Explanation of symbols

101, 101B X-side boost circuit 102, 102B Y-side boost circuit 103 X-side write constant current source circuit 104 Y-side write constant current source circuit 105 Operation mode determination circuit

Claims (13)

A storage element for storing information;
A constant current source provided for writing information to the storage element by passing a current;
For charging a parasitic capacitor at a predetermined location associated with the storage element until the amount of current passed by the constant current source reaches the amount of current required to write information to the storage element Boost circuit,
A semiconductor memory device comprising: The semiconductor memory device according to claim 1,
2. The semiconductor memory device according to claim 1, wherein the memory element is a tunnel magnetoresistive element, and the predetermined position is a position that applies a magnetic field by current to the tunnel magnetoresistive element. The semiconductor memory device according to claim 1,
2. The semiconductor memory device according to claim 1, wherein the boost circuit includes a capacitor that accumulates charges for charging the parasitic capacitor. The semiconductor memory device according to claim 3.
A semiconductor memory device, further comprising a circuit for setting a voltage between both electrodes of the capacitor to a power supply voltage or higher. The semiconductor memory device according to claim 3.
There are multiple capacitors,
2. The semiconductor memory device according to claim 1, wherein the boost circuit includes switching means for switching a capacitor used for charging according to an amount of electric charge necessary for charging the parasitic capacitor. The semiconductor memory device according to claim 5.
The semiconductor memory device, wherein the switching unit switches a combination of capacitors used for charging in accordance with an amount of electric charge necessary for charging the parasitic capacitor. The semiconductor memory device according to claim 5.
The semiconductor memory device according to claim 1, wherein at least some of the plurality of capacitors have a geometric series relationship with each other. The semiconductor memory device according to claim 5.
The capacity of at least a part of the plurality of capacitors is determined according to the capacitance of the parasitic capacitor depending on the amount of current necessary for writing information to the storage element. . The semiconductor memory device according to claim 5.
A capacity of at least a part of the plurality of capacitors is determined in accordance with a capacitance of the parasitic capacitor depending on a position of the storage element. The semiconductor memory device according to claim 5.
The capacity of at least a part of the plurality of capacitors is determined according to the capacitance of the parasitic capacitor depending on process conditions.   4. The semiconductor memory device according to claim 3, further comprising a circulating means for returning at least a part of a charge of a parasitic capacitor existing in a current path of a current for writing to the storage element to a node for storing the charge of the boost circuit. Semiconductor memory device.   4. The semiconductor memory device according to claim 3, wherein a time for accumulating charges in the boost circuit is set after the operation period of the constant current source is ended.   2. The semiconductor memory device according to claim 1, wherein a part of the charge of the parasitic capacitor existing in the current path of the current for writing to the memory element is retained depending on the history of the operation mode, and the boost circuit is discharged. A semiconductor memory device having charge holding means for suppressing.

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