KR100844947B1 - Multiple valued dynamic random access memory cell and thereof array using single electron transistor - Google Patents

Abstract

A multiple value DRAM and a multiple valued DRAM cell array using a single electron transistor are provided to store information above two bits as minimizing power consumption. One end of a first MOS transistor(M1) is connected to a bit line(BL) and the first MOS transistor has a gate connected to a read word line(RWL). One end of a second MOS transistor(M2) is connected to the other end of the first MOS transistor and the other end is connected to a charge charging node(SN), and the second MOS transistor has a gate connected to a write word line(WWL). A third MOS transistor(M3) has one end connected to a common port of the first MOS transistor and the second MOS transistor, and has a gate connected to the charge charging node. A fourth MOS transistor(M4) has one end connected to the charge charging node and has a gate receiving a refresh signal(SSG). A fifth MOS transistor(M5) has one end connected to the charge charging node and has a gate receiving the refresh signal. A SET(Single Electron Transistor) has one end connected to the other end of the fifth MOS transistor and the other end connected to a second power supply port(Vss) and has a gate connected to the charge charging node. A storage capacitor(Cs) has one end connected to the charge charging node and the other end connected to the second power supply port.

Description

Multiple Valued Dynamic Random Access Memory Cell and Various Array using Single Electron Transistor}

1 is a circuit diagram of a universal literal gate using a single gate SET and a MOS transistor.

FIG. 2 illustrates a relationship between an input voltage Vin of the ULG and a current Id flowing through the SET shown in FIG. 1.

FIG. 3 illustrates a relationship between an input voltage Vin and an output voltage Vout of the ULG shown in FIG. 1.

FIG. 4 is a circuit diagram of a quantizer using the ULG shown in FIG. 1.

FIG. 5 illustrates a relationship between an input voltage Vin of the quantizer illustrated in FIG. 4 and a current Id flowing through the SET.

FIG. 6 illustrates a relationship between an input voltage Vin and an output node Vout of the quantizer illustrated in FIG. 4.

FIG. 7 illustrates a multivalued SRAM cell using the quantizer shown in FIG. 4.

FIG. 8 is a waveform diagram of a signal used to store data or read stored data in the multi-value SRAM shown in FIG. 7.

9 is a circuit diagram of a multi-value DRAM cell using a SET according to the present invention.

10 illustrates a multi-valued DRAM cell array in accordance with the present invention.

FIG. 11 shows waveforms of respective signals when data is stored in the multi-value DRAM cell shown in FIG. 9.

FIG. 12 illustrates waveforms of signals in the standby state and the refresh operation of the multi-value DRAM cell shown in FIG. 9.

FIG. 13 shows waveforms of signals when reading data stored in the multi-value DRAM cell shown in FIG. 9.

FIG. 14 is a waveform diagram of signals used to store or read stored data in a multi-value DRAM cell according to the present invention.

15 is a diagram illustrating a method of reading data stored in a multi-value DRAM cell in accordance with the present invention.

FIG. 16 is a waveform diagram of signals used to read data stored in the multi-value DRAM cell shown in FIG. 15.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DRAM, and more particularly, to a multi-valued dynamic random access memory (DRAM) using a single electron transistor (SET).

Single electron transistor (SET) has a very special characteristic that the current flowing between the drain and the source periodically repeats the increase and decrease according to the voltage level of the bias voltage applied to the gate electrode. In addition to the SET, research on the applied circuit applying the electrical characteristics of the SET is currently in progress. K.K. Likharev, "Correlated discrete transfer of single electrons in ultrasmall tunnel junctions", IBM J. Res. Develop., Vol. 32, pp. 144-158, Jan. 1988, J.R. Tucker, "Complementary digital logic based on the Coulomb blockade". J. Appl. Phys., Vol. 72, pp. 4399-4413, Nov, 1992]

1 is a circuit diagram of a universal literal gate using a single gate SET and a MOS transistor.

Referring to FIG. 1, the ULG 100 includes a current source CS, a first MOS transistor M1, and a SET (SET).

The current source CS supplies a constant amount of current Io to the first MOS transistor M1 and SET (SET) connected in series. The first MOS transistor M1 transfers the current Io supplied from the current source CS connected to one terminal to the SET connected to the other terminal in response to the bias voltage Vgg applied to the gate. SET (SET) changes the amount and phase of the current Id supplied through one terminal according to the voltage level of the input voltage Vin applied to the gate.

FIG. 2 illustrates a relationship between an input voltage Vin of the ULG and a current Id flowing through the SET shown in FIG. 1.

FIG. 3 illustrates a relationship between an input voltage Vin and an output voltage Vout of the ULG shown in FIG. 1.

Referring to FIGS. 2 and 3, as the input voltage Vin increases, the amount Id of the current flowing through the ULG 100 repeats increasing and decreasing, and the voltage of the output terminal at the same period as the repetition period described above. Vout) also changes. At this time, the amount Io of the current that can be supplied from the current source CS is always constant.

1, 2 and 3, according to the value of the input voltage Vin, the amount of current Id flowing in the ULG 100 is greater than the fixed amount Io supplied from the current source CS. There is an increasing section A. In this case, the voltage of the output terminal Vout so that a current equal to the difference between the two currents Id-Io can be supplied to the ULG 100 through the first MOS transistor M1. The level should be lowered. In addition, there is a period B in which the amount of current flowing in the ULG 100 decreases from the fixed amount Io supplied from the current source CS according to the value of the input voltage Vin, in which case two currents The voltage level of the output terminal Vout should be increased so that a current equal to the difference Io-Id can be blocked through the first MOS transistor M1.

FIG. 4 is a circuit diagram of a quantizer using the ULG shown in FIG. 1.

Referring to FIG. 4, the quantizer is obtained by adding one second MOS transistor M2 to the ULG 100 shown in FIG. The input signal Vin is simultaneously applied to the gate terminal Cg and the output terminal Vout of the SET through the second MOS transistor M2 in response to the control clock signal CLK.

FIG. 5 illustrates a relationship between an input voltage Vin of the quantizer illustrated in FIG. 4 and a current Id flowing through the SET.

FIG. 6 illustrates a relationship between an input voltage Vin and an output node Vout of the quantizer illustrated in FIG. 4.

5 is the same as FIG. 2 previously described and will not be described any further. Referring to FIG. 6, as the input voltage Vin increases, the voltage level Vout of the output node takes the form of a step. The logic high and logic low of FIG. Instead of representing only two values, a multiple-valued quantizer that represents multiple values.

The multi-valued quantizer can be implemented by using the second MOS transistor M2 and the control clock signal CLK shown in FIG. 4, wherein a neighboring step showing one voltage level and another voltage level indicated by the step is a control clock signal. Each cycle of (CLK) can be distinguished. The input voltage Vin is transmitted not only to the gate terminal Cg of the SET but also to the output node Vout through the second MOS transistor M2 by the control clock signal CLK. The voltage level Vout of the terminal responds based on the input voltage Vin once transmitted. Therefore, since the voltage level Vout of the output node is affected by the newly transmitted input signal Vin by the input signal Vin having another voltage level applied by the next control clock signal CLK, the control clock When the input voltage Vin received by the signal CLK is changed, the voltage level Vout of the output node is also changed correspondingly. If the input voltage Vin continues to increase, the voltage level Vout of the output node may increase in plural as it increases.

FIG. 7 illustrates a multivalued SRAM cell using the quantizer shown in FIG. 4.

Referring to FIG. 7, the multi-valued SRAM includes five MOS transistors M1 to M5 and one SET (SET).

One terminal of the third MOS transistor M3 is connected to the bit line BL, and a gate thereof is connected to the word line WL. One terminal of the second MOS transistor M2 is connected to the first power supply terminal Vdd, and the other terminal and the gate of the second MOS transistor M2 are connected to the charge charging node SN. One terminal of the first MOS transistor M1 is connected to the charge charging node SN and a gate thereof is connected to the second power supply terminal Vss. SET (SET) has one terminal connected to the other terminal of the first MOS transistor M1, the other terminal connected to the second power supply terminal Vss, and the gate connected to the charge charging node SN. The fourth MOS transistor M4 has one terminal connected to the second power supply terminal Vss and a gate connected to the charge charging node SN. One terminal of the fifth MOS transistor M5 is connected to the SL line SL, the other terminal of the fifth MOS transistor M5 is connected to the other terminal of the fourth MOS transistor M4, and a gate thereof is connected to the SWL line SWL.

FIG. 8 is a waveform diagram of a signal used to store data or read stored data in the multi-value SRAM shown in FIG. 7.

Referring to FIG. 8, in order to store data in the multi-value SRAM, a voltage to be stored in the multi-value SRAM needs to be precharged to the bit line BL. The voltage to be stored is determined according to the number of bits to be expressed by the multi-value SRAM, and assuming two bits, there are four different voltage levels. Four cases that can be represented by two bits are '00', '01', '10', and '11'. In this case, the voltage levels corresponding to the four cases may be assumed to be the lowest voltage when '00' and the largest voltage when '11'.

After precharging the voltage to be stored in the bit line BL, when the word line WL is enabled in a logic high state, the third MOS transistor M3 is turned on so that the precharge voltage becomes a charge charging node. SN). Since the transferred voltage is applied to the gate, a constant current flows in the SET based on the transferred voltage, but unless the power supply is deliberately cut off from the first power supply terminal Vdd, the second MOS transistor M2, Since a constant current flows to the second power supply terminal Vss via the first MOS transistor M1 and SET (SET), the charges stored in the charge charging node SN are not lost. Therefore, the device shown in Fig. 7 is an SRAM which does not need refreshing, and because the stored voltage value can be varied, it is precisely a multi-value SRAM.

In order to read the data stored in the multi-value SRAM, when the SWL line SWL is enabled, the data stored in the charge-charging node SN of the multi-value SRAM can be detected through the SL line SL which is precharged with a constant voltage. That is, since the charge charging node SN is applied to the gate of the fourth MOS transistor M4, the amount of current that can flow through the fourth MOS transistor M4 is determined by the charge charging node SN. The current flowing through the precharged SL line SL is also changed by the charge charging node SN. By detecting this, the data value stored in the multi-value SRAM can be known.

Referring to FIG. 7, since the multiple-valued SET SRAM has to continuously flow current as much as I _d as a SET per cell in order to preserve data, the standby current increases as the density increases. I have a problem.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a multi-value DRAM cell capable of storing more than two bits of information with minimum power consumption.

Another technical problem to be achieved by the present invention is to provide a multi-value DRAM cell array capable of storing at least two bits of information with minimum power consumption.

The multi-value DRAM cell using SET according to the present invention for achieving the above technical problem is provided with five MOS transistors (M1 ~ M5), one SET (SET) and one storage capacitor (Cs). One terminal of the first MOS transistor M1 is connected to a bit line BL and a read word line RWL is connected to a gate thereof. One terminal of the second MOS transistor M2 is connected to the other terminal of the first MOS transistor M1, the other terminal is connected to the charge charging node SN, and the gate is connected to the write word line WWL. do. One terminal of the third MOS transistor M3 is connected to the common terminal of the first MOS transistor M1 and the second MOS transistor M2, and a gate thereof is connected to the charge charging node SN. One terminal of the fourth MOS transistor M4 is connected to the charge charging node SN, and a refresh signal SSG is applied to a gate thereof, and the other terminal of the fourth MOS transistor M4 supplies a constant current Io. Is connected to. One terminal of the fifth MOS transistor M5 is connected to the charge charging node SN, and the refresh signal SSG is applied to a gate thereof. The SET (SET) has one terminal connected to the other terminal of the fifth MOS transistor M5, the other terminal connected to the second power supply terminal Vss, and the gate connected to the charge charging node SN. do. One terminal of the storage capacitor Cs is connected to the charge charging node SN, and the other terminal of the storage capacitor Cs is connected to the second power supply terminal Vss.

In the multi-value DRAM cell array according to the present invention, a plurality of multi-value DRAM cells shown in FIG. 9 are two-dimensionally arranged, and a plurality of bit lines BL0 to BL3 are read. Word lines RWL0 to RWL3, a plurality of write word lines WWL0 to WWL3, a plurality of refresh lines SSG0 to SSG3, and a read auxiliary block 1010. Each of the multi-valued DRAM cells is connected to a corresponding bit line, a corresponding read word line, a corresponding write word line, and a corresponding refresh line, and another terminal of the third MOS transistor M3 is connected to the read auxiliary block 1010. The read assist block 1010 operates in response to the read assist signal SCEN. Among the plurality of multi-valued DRAM cells arranged in two dimensions, the other terminals of the third MOS transistors included in the multi-valued DRAM cells arranged on each line in the vertical direction or each line in the horizontal direction form one common line to read the read. It is connected to the auxiliary block 1010.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

9 is a circuit diagram of a multi-value DRAM cell using a SET according to the present invention.

Referring to FIG. 9, a multi-valued DRAM cell using SET includes five MOS transistors M1 to M5, one SET (SET), and one storage capacitor Cs.

One terminal of the first MOS transistor M1 is connected to a bit line BL and a read word line RWL is connected to a gate thereof. One terminal of the second MOS transistor M2 is connected to the other terminal of the first MOS transistor M1, the other terminal is connected to the charge charging node SN, and the gate is connected to the write word line WWL. . One terminal of the third MOS transistor M3 is connected to the common terminal of the first MOS transistor M1 and the second MOS transistor M2, and a gate thereof is connected to the charge charging node SN. The fourth MOS transistor M4 has one terminal connected to the charge charging node SN and a refresh signal SSG is applied to a gate thereof, and the other terminal is connected to a current source (not shown) that supplies a constant current Io. Connected. One terminal of the fifth MOS transistor M5 is connected to the charge charging node SN and the refresh signal SSG is applied to a gate thereof. SET (SET) has one terminal connected to the other terminal of the fifth MOS transistor M5, the other terminal connected to the second power supply terminal Vss, and the gate connected to the charge charging node SN. . One terminal of the storage capacitor Cs is connected to the charge charging node SN, and the other terminal of the storage capacitor Cs is connected to the second power supply terminal Vss.

The other terminal of the third MOS transistor M3 is connected to the switch M6. The switch M6 has one terminal connected to the other terminal of the third MOS transistor M3, and the other terminal connected to the ground voltage GND or the second power supply terminal Vss, and a read auxiliary signal at the gate. It can be implemented by the MOS transistor M6 to which (SCEN) is applied. The read auxiliary signal SECN is a signal enabled only when reading data stored in a multi-value DRAM cell.

10 illustrates a multi-valued DRAM cell array in accordance with the present invention.

Referring to FIG. 10, in the multi-value DRAM cell array, a plurality of multi-value DRAM cells shown in FIG. 9 are two-dimensionally arranged, a plurality of bit lines BL0 to BL3, and a plurality of read word lines RWL0. RWL3), a plurality of write word lines WWL0 to WWL3, a plurality of refresh lines SSG0 to SSG3, and a read auxiliary block 1010.

Each of the multi-valued DRAM cells is connected to a corresponding bit line, a corresponding read word line, a corresponding write word line, and a corresponding refresh line, and another terminal of the third MOS transistor M3 is connected to the read auxiliary block 1010. The read assist block 1010 operates in response to the read assist signal SCEN.

Among the plurality of multi-valued DRAM cells arranged in two dimensions, the other terminals of the third MOS transistors included in the multi-valued DRAM cells arranged on each line in the vertical direction or each line in the horizontal direction form one common line to read the read. It is connected to the auxiliary block 1010.

The read auxiliary block 1010 includes a plurality of MOS transistors M6 to M9 having one terminal connected to a second power supply terminal Vss and the other terminal connected to a corresponding common line. The read auxiliary signal SCEN is commonly applied to gates of the transistors.

Although the refresh signal SSG is shown in parallel with the two word lines WWL and RWL in FIG. 10, in some cases, the refresh signal SSG may be implemented in parallel with the bit line BL.

Hereinafter, the operation of storing data in the multi-value DRAM cell, in the standby state of the multi-value DRAM cell and the refresh operation mode, and finally reading the data stored in the multi-value DRAM cell will be described in order.

FIG. 11 shows waveforms of respective signals when data is stored in the multi-value DRAM cell shown in FIG. 9.

Referring to FIG. 11, in order to store data in the multi-value DRAM cell (FIG. 9), a voltage to be stored in the multi-value DRAM cell must be precharged in the bit line BL. For convenience of description, it is assumed that all the MOS transistors shown in FIG. 9 are N-type. The voltage applied to the bit line BL is passed through the first and second MOS transistors M1 and M2 which are both turned on by the enabled write word line WWL and the read word line RWL. It is delivered to the charge charging node (SN). The fourth MOS transistor M4 and the fifth MOS transistor M5 are simultaneously operated in order for the multi-value DRAM cell (FIG. 9) to operate based on a voltage precharged to the bit line BL and transferred to the charge charging node SN. The refresh signal SSG must have a voltage level greater than or equal to Vthn because it must be turned on. Here, Vthn means the threshold voltage of SET (SET).

Although not shown in the drawing, the read auxiliary signal SCEN has a voltage level of the ground voltage GND or the second power supply voltage Vss to turn off the sixth MOS transistor M6 to turn off the third MOS transistor. The common terminal SC of M3 and the sixth MOS transistor M6 should be floated. Due to the signals as described above, a current of Io [A] flows through the SET. Here, the current Io does not mean a constant current value Io flowing from the current source CS, which is indicated when describing the conventional invention, but means an amount of an arbitrary current that varies according to the voltage precharged to the bit line BL. .

FIG. 12 illustrates waveforms of signals in a standby state and a refresh operation of the multi-value DRAM cell shown in FIG. 9.

Referring to FIG. 12, in the waveform of each signal, when the multi-value DRAM cell (FIG. 9) is operating in the refresh mode, the condition of the center section among the three sections separated by two dotted lines must be satisfied and is in a standby state. , The conditions of the remaining two sections must be satisfied.

In the standby state, the write word line WWL, the read word line RWL, the refresh signal SSG, and the read assist signal SCEN are all disabled. Therefore, the write word line WWL, the read word line RWL, the refresh signal SSG, and the read auxiliary signal SCEN have a voltage level of the ground voltage GND or the second supply power source Vss. The common terminal SC of the third MOS transistor M3 and the sixth MOS transistor M6 should be floated. Since the two MOS transistors M4 and M5 are turned off by the disabled refresh signal SSG, the current i (SET) flowing in the SET (SET) becomes 0 (zero) ampere. At this time, the charge stored in one terminal of the storage capacitor Cs, that is, the charge charging node SN, leaks through various paths. Therefore, refresh must be performed within a certain time.

In the state of performing the refresh, the voltage level of the read word line RWL and the write word line WWL is the same as the standby state described above, but the refresh signal SSG is the fourth MOS transistor M4 and the fifth. The MOS transistor M5 should have a voltage level at which it can be turned on, which is the same as the voltage level shown in FIG. 11. At this time, the current Io [A] corresponding to the previously stored data value flows in SET (SET), and the multi-valued DRAM cell (Fig. 9) is refreshed.

The period of the refresh signal SSG and the width of the signal vary depending on the capacity of the storage capacitor Cs.

FIG. 13 shows waveforms of signals when reading data stored in the multi-value DRAM cell shown in FIG. 9.

Referring to FIG. 13, in order to read data stored in the multi-value DRAM cell (FIG. 9), the read word line RWL and the read auxiliary signal SCEN are enabled so that the first MOS transistor M1 and the sixth MOS transistor 6 are read. Turn M6) on respectively. Although the refresh signal SSG has a voltage level for turning off the fourth MOS transistor M4 and the fifth MOS transistor M5 in FIG. 13, the fourth MOS transistor M4 and the fifth MOS transistor are reversed. There may be no problem even if (M5) is turned on. Since the second MOS transistor M2 is turned off by the write word line WWL having the voltage level of the ground voltage GND, the second MOS transistor M3 is turned off according to the voltage level of the charge charging node SN. The amount of current that can flow is determined. Although not shown in the figure, a constant comparison voltage is precharged on the bit line BL to read data stored in the multi-value DRAM cell (FIG. 9). Therefore, the voltage level of the charge charging node SN may be determined by detecting a difference between the voltage level of the charge charging node SN and the voltage precharged in the bit line BL. A method of detecting the voltage level of the charge charging node SN will be described later.

FIG. 14 is a waveform diagram of signals used to store or read stored data in a multi-value DRAM cell according to the present invention.

Referring to FIG. 14, in order to store data in a multi-value DRAM cell, a constant voltage should be applied to the bit line BL while both the write word line WWL and the read word line RWL are enabled. In this case, the constant voltage depends on the number of bits to be stored in the multi-value DRAM cell. In the case of storing 2 bits of data in the multi-value DRAM cell, 4 voltages are stored and 3 bits of data are stored. If desired, eight voltages will be stored.

Hereinafter, an example in which data corresponding to two bits is to be stored will be described. Referring to FIG. 14, four cases that can be implemented with 2 bits are '00', '01', '10', and '11', and the voltage corresponding to '00' is the lowest and corresponds to '11'. It is assumed that the voltage to be relatively high.

In the period between t1 and t2, both the write word line WWL and the read word line RWL are enabled. In this period, the data voltage to be stored in the multi-value DRAM cell is precharged to the bit line BL. The data voltage is transferred to and stored in the charge charging node SN. It has already been described that the read word line RWL and the read storage signal SCEN are turned on to read the stored data voltage. Therefore, the read word line RWL is enabled not only when storing data but also when reading data.

15 is a diagram illustrating a method of reading data stored in a multi-value DRAM cell in accordance with the present invention.

Referring to FIG. 15, when the Y decoding signal YA is enabled in order to read data stored in a multi-value DRAM cell, the main current Imain from the precharge transistor P0 may be a bit line BL, The second power supply terminal Vss flows through the first MOS transistor M1, the third MOS transistor M3, and the sixth MOS transistor M6 of the multi-value DRAM cell. Determining the amount of the main current Imain is the voltage level of the charge charging node SN applied to the gate of the third MOS transistor M3.

In order to detect the amount of main current Imain flowing in the multi-value DRAM cell, a reference cell having the same structure as the multi-value DRAM cell and storing a reference voltage Vref is used. do. When the reference Y decoding signal RYA is enabled while the Y decoding signal YA is enabled, the reference current Iref from the precharge transistor P3 is the reference bit line RBL and the first MOS of the reference cell. It flows to the second power supply terminal Vss via the transistor RM1, the third MOS transistor RM3, and the sixth MOS transistor RM6.

The gate voltage Vm of the precharge transistor P0 generating the main current Imain is buffered to generate the main voltage Vmain, and the gate voltage V of the reference voltage transistor P3 generating the reference current Iref. V _R ) is buffered to generate a reference voltage Vref. Since the two MOS transistors P0 and P1 are related to the current mirrors, two MOS transistors have the same gate width and gate length of the two MOS transistors P0 and P1. The currents flowing through the transistors P0 and P1 will be the same, so that the two voltages Vm and Vmain have the same voltage level. Since the other two MOS transistors P2 and P3 also have a current mirror relationship, for the same reason as described above, the two voltages V _R and Vref also have the same voltage level. The sense amplifier (S / A) receives the main voltage (Vmain) and the reference voltage (Vref) and compares the magnitudes of the main voltage (Vmain) and the reference voltage (Vref), the sense amplifier (S / A) of the The data stored in the multi-value DRAM cell (Main Cell) is detected using the output signal Vout.

If the detection result that the voltage level of the main voltage (Vmain) is higher than the reference voltage (Vref) is output, the voltage level of the reference voltage (Vref) is increased by one step and compared again, this process is compared to the reference voltage (Vref) On the contrary, the above process is continued until the main voltage Vmain is the same or smaller, thereby detecting the digital data represented by the main voltage Vmain. When the voltage level of the reference voltage Vref is to be changed, the voltage to be changed may be stored in the reference cell shown in FIG. 15.

FIG. 16 is a waveform diagram of signals used to read data stored in the multi-value DRAM cell shown in FIG. 15.

Referring to FIG. 16, when reading data stored in a multi-value DRAM cell, the relationship between the gate voltage Vm of the precharge transistor P0 and the gate voltage V _R of the reference transistor P3 is represented by Equation 1 below. can do. For convenience of explanation, it is assumed that binary data is stored in a multi-value DRAM cell.

V _{m'1 '} <V _R <V _m'0'

Where V _{m'1 '} is the gate voltage Vm of the precharge transistor P0 when the value of logic' 1 'is stored in the multi-value DRAM cell, and V _m'0' is the value of logic '0'. It means when it is saved. Therefore, the voltage level of the main voltage Vmain may be represented by Equation 2 as the voltage level of the reference voltage Vref.

V _{main'1 '} <V _ref <V _main'0'

Where V _{main'1 '} is the voltage (Vmain) input to the sense amplifier when the value of logic' 1 'is stored in the multi-value DRAM cell, and V _main'0' is the voltage when the value of logic '0' is stored. Means.

If the storage voltage corresponding to logic '0' is _referred to as V _SN'0 and the storage voltage corresponding to logic '1' is referred to as V _{SN'1 '} , the charge charging node RSN of the reference cell The relationship between the voltage V _RSN and the voltage V _SN of the charge charging node SN of the multi-value DRAM cell Main Cell may be expressed as shown in Equation 3 below.

V _{SN'0 '} <V _RSN <V _SN'1'

The main current Imain and the reference current Iref are respectively determined by the voltage level of the charge charging node SN of the multi-valued DRAM cell and the voltage level of the charge charging node RSN of the reference cell. It is determined and can be expressed as Equation 4.

I _{main'0 '} <I _ref <I _main'1'

In this case, the comparison result between the main voltage Vmain and the reference voltage Vref may be determined as the comparison signal Vout output from the sense amplifier.

The following briefly summarizes the present invention.

In order to store data in a multi-value DRAM cell according to the present invention, the write word line WWL and the read word line RWL are enabled at the same time to enable multiple valued data to the charge charging node SN. Ensure that the voltage level corresponding to) is stored.

In this case, a voltage equal to or higher than the voltage Vthn is applied to the gates of the fourth and fifth MOS transistors M4 and M5 that control the current flowing in the SET. For example, if the voltage level of the refresh signal SSG is Vthn + 10 [mV], the voltage level of the common node of the fifth MOS transistor M5 and SET (SET) becomes 10 [mV] and thus the coulomb blockcade (coulomb). blockade is enabled. Here, the Coulomb Blockade is an effect of the Coulomb repulsion between electrons in the fine nano structure.

While the stored data is held (Standby), the voltage of the refresh signal SSG is set to 0 V so that no current flows in the SET (SET). This minimizes the power consumption of multi-value DRAM cells in standby.

During the data refresh period, a voltage equal to or greater than the voltage Vthn is applied to the gates of the fourth and fifth MOS transistors M4 and M5 so that a current flowing from the SET (SETA) becomes a storage capacitor. It is possible to recharge the electric charges discharged at (Cs). In this case, 0 V is applied to the write word line WWL and the read word line RWL to turn off the first and second MOS transistors M1 and M2. When the refresh of the charge charging node SN is completed, the fourth MOS transistor M4 and the fifth MOS transistor M5 are turned off again to prevent current from flowing in the SET.

When reading data stored in the multi-value DRAM cell, the first MOS transistor M1 and the third MOS transistor M3 are turned on. At this time, if a current is connected by connecting the precharge transistor P0 to the bit line BL, the current flows in the bit line BL according to the voltage of the charge charging node SN applied to the gate of the third MOS transistor M3. As the current varies, the changed current enables the detection of data stored in the multi-value DRAM cell.

Conventional DRAMs use a method of detecting charged charges by charging the charges stored in the storage capacitor Cs with bit line capacitors. The charge had to be restored. However, the method proposed in the present invention does not need to replenish charges because the stored data, i.e., the distribution of charges, is not made when reading the stored data, so that a separate charge replenishment cycle is not required after reading the data. In addition, the power consumption is also relatively reduced.

The fourth MOS transistor M4 and the fifth MOS transistor M5 act as a switch for flowing or blocking current through the SET (SETA) and at the common node of the SET (SET) and the fifth MOS transistor M5. It also plays a role to ensure that the voltage is low enough to maintain the Coulomb blockcade condition.

When the voltage of about Vthn is applied to the gate of the fifth MOS transistor M5, the drain and the drain of SET (SET) are maintained so that the common node of the fifth MOS transistor M5 and SET (SET) maintain a voltage level of about several tens of mV. The voltage V _DS between the sources becomes several tens of mV.

The difference between the core idea of the present invention and the conventional embodiment (Fig. 7) is that one storage capacitor Cs is used to store a plurality of different voltage levels corresponding to the plurality of digital data. In order to preserve the current, the fourth MOS transistor M4 and the fifth MOS transistor M5 are periodically turned on and off at a predetermined cycle instead of continuously flowing current to the SET.

In general, since the charges stored in one capacitor can be maintained for several msec to several tens of msec, they should be refreshed with a period of several msec to several tens of msec. If the current consumed by the SET in the unit cell is 100 pA to refresh the data, the standby current of a semiconductor device having a 256M cell array is about 30 [mA], and the standby current of a general DRAM is 1 [mA]. In consideration of the following, it becomes a very large value.

However, in the case of a DRAM cell having a structure according to the present invention, assuming that the refresh cycle is about 1 msec and the time required for data refresh is about 100 ns (nano-seconds), the average standby current is represented by the following equation (5). Similarly, it is several microampere (uA) or less.

          (100pA x 256M cell x 100ns) / 1msec = 3uA

Common area SRAM occupies in the layout as compared to the DRAM Whereas characterized in that the lower large, while the power consumption, in the case of a DRAM cell using a SET in accordance with the present invention, can lower the power consumption compared to the SRAM using the SET at least 10 ⁵ times Will be.

In the above description, the technical idea of the present invention has been described with the accompanying drawings, which illustrate exemplary embodiments of the present invention by way of example and do not limit the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

As described above, the multi-value DRAM cell according to the present invention has an advantage of minimizing power consumption and storing two or more bits of information.

Claims (13)

A first MOS transistor M1 having one terminal connected to a bit line BL and a read word line RWL connected to a gate thereof; A second MOS transistor M2 having one terminal connected to the other terminal of the first MOS transistor M1, the other terminal connected to the charge charging node SN, and the gate connected to the write word line WWL; A third MOS transistor M3 having one terminal connected to a common terminal of the first MOS transistor M1 and the second MOS transistor M2 and having a gate connected to the charge charging node SN; A fourth MOS transistor M4 having one terminal connected to the charge charging node SN and a refresh signal SSG applied to a gate thereof; A fifth MOS transistor M5 having one terminal connected to the charge charging node SN and a refresh signal SSG applied to a gate thereof; SET (SET) having one terminal connected to the other terminal of the fifth MOS transistor (M5), the other terminal connected to the second power supply terminal (Vss), and the gate connected to the charge charging node (SN); And A multi-value DRAM cell using a SET, wherein one terminal has a storage capacitor Cs connected to the charge charging node SN and the other terminal connected to the second power supply terminal Vss. The method of claim 1, The other terminal of the fourth MOS transistor is a multi-value DRAM cell using a SET, characterized in that connected to any current source (Io). The method of claim 1, And a switch for switching another terminal of the third MOS transistor (M3) to a ground voltage or a second power supply terminal (Vss). The method of claim 3, wherein the switch, A first terminal connected to the other terminal of the third MOS transistor M3, the other terminal connected to the ground voltage or the second power supply terminal Vss, and a read auxiliary signal SCEN applied to a gate thereof; A multi-valued DRAM cell using SET, characterized in that it is a six MOS transistor M6. The method of claim 4, wherein And the read assist signal SCEN is enabled only when reading data stored in the multi-value DRAM cell. The bit line BL of claim 1, further comprising: A multi-valued DRAM cell using a SET, characterized in that it is connected to a voltage source that outputs at least two different voltage levels. The method of claim 1, The refresh signal periodically changes its voltage value to open and close the fourth and fifth MOS transistors M4 and M5, and the period of the refresh signal discharges the charge stored in the storage capacitor. A multi-value DRAM cell using SET, which is determined by time. The plurality of multi-valued DRAM cells of claim 1 are two-dimensionally arranged, a plurality of bit lines BL0 to BL3, a plurality of read word lines RWL0 to RWL3, and a plurality of write word lines WWL0 to WWL3), a plurality of refresh lines SSG0 to SSG3, and a read auxiliary block 1010, Each of the multi-valued DRAM cells is connected to a corresponding bit line, a corresponding read word line, a corresponding write word line, and a corresponding refresh line, and another terminal of the third MOS transistor M3 is connected to the read auxiliary block 1010. , And the read assist block 1010 operates in response to a read assist signal SCEN. The method of claim 8, Among the plurality of multi-valued DRAM cells arranged in two dimensions, the other terminals of the third MOS transistors included in the multi-valued DRAM cells arranged on each line in the vertical direction or each line in the horizontal direction form one common line to read the read. A multi-valued DRAM cell array using a SET, characterized in that connected to the auxiliary block. The method of claim 9, wherein the read auxiliary block, One terminal is connected to the second power supply terminal Vss, and the other terminal has a plurality of MOS transistors connected to a corresponding common line, and the read auxiliary signal SCEN is commonly applied to the gates of the plurality of MOS transistors. A multi-value DRAM cell array using SET, characterized in that the. The method of claim 10, And the read assist signal (SCEN) is enabled only when reading data stored in the multi-value DRAM cell array. The method of claim 8, A multivalued DRAM reference cell having the same structure as the multivalued DRAM cell; And Further comprising a sense amplifier, The sense amplifier compares a current flowing in a bit line BL connected to the multi-value DRAM cell and a current flowing in a reference bit line RBL connected to the multi-value DRAM reference cell. . The method of claim 12, wherein the multi-value DRAM reference cell, And a voltage value equal to any one of a plurality of different voltage values stored in the multi-value DRAM cell.

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