WO2006083085A1

WO2006083085A1 - Memory cell employing single electron transistor and memory device using the same

Info

Publication number: WO2006083085A1
Application number: PCT/KR2006/000256
Authority: WO
Inventors: Hun Woo Kye; Bok Nam Song; Chuel Hun Choi
Original assignee: Excel Semiconductor Inc.
Priority date: 2005-02-07
Filing date: 2006-01-24
Publication date: 2006-08-10
Also published as: KR20060090074A; KR100673408B1

Abstract

Disclosed herein is a memory cell employing a single electron transistor, and a memory device using the same. The memory cell of the present invention includes a single electron transistor and first to fifth transistors. The first transistor is connected at a source thereof to a drain of the single electron transistor, and at a gate thereof to ground voltage. The second transistor is connected at a source thereof to the drain of the first transistor, at a drain thereof to power supply voltage and at the source and a gate thereof to a gate of the single electron transistor. The third transistor is connected at a gate thereof to a first word line, and at a source thereof to the gate of the single electron transistor. The fourth transistor is connected at a gate thereof to the gate of the single electron transistor, and at a drain thereof to a drain of the third transistor. The fifth transistor is connected at a drain thereof to a bit line, at a gate thereof to a second word line, and at a source thereof to the drain of the third transistor.

Description

Description MEMORY CELL EMPLOYING SINGLE ELECTRON

TRANSISTOR AND MEMORY DEVICE USING THE SAME

Technical Field

[1] The present invention relates generally to a semiconductor memory device and, more particularly, to a memory cell employing a single electron transistor, and a memory device using the same.

Background Art

[2] A single electron transistor (hereinafter referred to an 'SET') has become a principal element of electronic devices.

[3] FIG. 1 is a diagram illustrating an enlarged SET, and FIG. 2 is a circuit diagram of the SET. Referring to HGS. 1 and 2, the SET 100 includes two leads, that is, a source lead 105 and a drain lead 110. The SET 100 further includes a small metal island 115 that connects to the source lead 105 and the drain lead 110 respectively via tunnel junctions 106 and 111 respectively having a large resistance and a small capacitance. Furthermore, the SET 100 includes a third lead 120 that is attached to a gate 125 that is capacitively coupled to the island 115. Voltage applied to the SET 100 induces current flowing through the island 115, which is controlled by voltage Vg applied to the gate 125, as in a Field Effect Transistor (EFT).

[4] The SET 100 operates using a coulomb blockade effect. When electrons are injected into the island 115 at a gate voltage V of 0, the energy of the SET 100 g increases by e² /2C_Σ

represents the total capacitance

C₅ + C_j0 + C_Q of the island 115.

Cs and

C_D respectively represent the capacitances of the two tunnel junctions 116 and 111, and represents a gate-island capacitance 125 between the gate 120 and the island 115.

When V =0, the energy barrier of g e²/2C_Σ must be overcome before current flows from the source lead 105 into the drain lead 110 via the island 115. The gate lead 120 of the SET 100 acts as an input lead. If a small amount of voltage is applied to the gate 120, a polarization charge will flow into the island 115. The energy barrier continuously decreases, so that current, which flows through the island 115, increases at a fixed bias voltage. As a result, I- V characteristic g is periodic with a cycle of e/C_ε

, where e is the charge of an electron. When the charge CgVg applied to the gate exceeds e

, the average number of electrons on the island 115 increases through the tunneling of the junctions.

[5] The SET 100 has a special characteristic in which the drain current periodically increases and decreases depending on the gate bias. Research into increasing the functionality of a circuit with a small number of transistors using the special characteristic are actively being conducted. When the SET 100 is used, there are advantages in that the integration of circuits can be improved, and power consumption is low. In particular, the SET 100 has characteristics very suitable for the application of a multiple- valued logic circuit, and great efforts are underway to apply the SET to the multiple- valued logic circuit.

[6] FIG. 3 is a circuit diagram illustrating a universal literal gate in which the SET 100 and a MOS transistor are combined together. Referring to FIG. 3, when a fixed voltage is applied to the gate of a transistor Ml, the drain voltage Vds of the SET 100 is maintained at an almost constant voltage of Vgg-Vth. The voltage Vgg-Vth is low enough to maintain the coulomb blockade condition of the SET 100. The SET 100 exhibits a characteristic in which the drain current periodically increases and decreases. At this time, the drain voltage of the SET 100 is supplied by a constant current source 210. If an input voltage is applied such that a current, which is greater than the current Io supplied by the constant current source 210, flows through the SET 100, an output voltage Vout rapidly decreases from logic high to logic low. In contrast, if the input voltage is applied such that current, which is less than the current Io supplied by the constant current source 210, flows as the drain current Id of the SET 100, the output voltage Vout rapidly increases from logic low to logic high. Therefore, as illustrated in FlG. 4, when the input voltage Vin increases, the output voltage Vout of the universal literal gate 200 exhibits the same characteristic as a square wave having a very high voltage swing.

[7] FlG. 5 is a circuit diagram of a quantizer using the universal literal gate 200 of

FlG. 3, and FlG. 6 is a graph showing the operation characteristic of the quantizer. Referring to FIGS. 5 and 6, a plurality of stability points exist due to the current Io of the constant current source 210, and respective stability points are distinguished by respective dotted lines. The stability points allow the quantizer to operate within a stable range. That is, when a clock signal CLK is enabled, the input voltage Vin is delivered to a SN node, and then the clock signal CLK is disabled, so quantization is performed at a stability point corresponding to the voltage. Therefore, a Vin- Vout voltage characteristic similar to a step waveform is acquired, as illustrated in FlG. 6.

[8] The quantizer circuit 300 in which the SET 100 and the MOS transistor are combined together is applicable to memory. Particularly, the quantizer circuit 300 can store multiple levels of voltage without a refresh operation, so that it is very efficient for Multiple Valued Static memory (MV-SRAM).

[9] FIG. 7 is a diagram illustrating an MV-SRAM cell 400 to which the quantizer circuit 300 of FlG. 5 is applied, and FlG. 8 is a timing diagram illustrating the write and read operations of the MV-SRAM cell. Referring to FlG. 7, the MV-SRAM cell 400 includes a first transistor Ml connected between the SET and a storage node SN and connected at the gate thereof to ground voltage, a second transistor M2 connected between power supply voltage Vdd and the storage node SN and connected at the gate thereof to the storage node SN, a third transistor M3 connected between a bit line BL and the storage node SN and connected at the gate thereof to a first word line WL, a fourth transistor M4 connected at the gate thereof to the storage node SN and at the source thereof to ground voltage, and a fifth transistor connected at the source thereof to the drain of the fourth transistor M4, at the gate thereof to a second word line SWL, and at the drain thereof to a second bit line SL.

[10] Referring to FlG. 8, the first word line is enabled at timing t0 upon a write operation. After the first word line WL has been enabled, a voltage corresponding to a multiple logic value is applied to the first bit line BL at timing tl. The MV-SRAM cell 400 of FlG. 7 is an embodiment, which can store 2 bits. In order to store 2 bits, 4 levels of different voltages are applied to the first bit line BL, thus being stored in the SN node. After the corresponding voltages has been delivered to the SN node, the first word line WL is disabled at timing t2, and is precharged to the ground voltage at timing t3. Then, the voltage stored in the SN node is maintained at a stored level without a refresh operation according to the operation stability principle of the quantizer 300 of FlG. 6. During a read operation, the second word line SWL is enabled, so that constant current flows to the second bit line SL via the transistors M4 and M5 connected to the SN node. This current is proportionalto the voltage stored in the SN node, so that it is possible to read a stored logic value by sensing the amount of the current and converting it into a corresponding voltage.

[11] When the MV-SRAM cells are constructed in the form of an array, there is a disadvantage in that two word lines WL and SWL and two bit lines BL and SL are required per cell, and, as illustrated in FlG. 9, a memory area increases. The advantage of the multiple valued memory is that the number of stored bits per cell increases, so that the integration of memory is improved. However, the number of row lines used to implement the first and second word lines WL and SWL and the number of column lines used to implement the first and second word lines BL and SL increase, so that it is impossible to sufficiently use the advantage of the MV-SRAM.

[12] As a result, a new MV-SRAM cell that can improve the integration of memory is required to replace a conventional MV-SRAM cell using two row lines and two column lines. Disclosure of Invention

Technical Problem

[13] Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a memory cell that includes a SET and uses two row lines and one column line.

[14] Another object of the present invention is to provide a memory device, which senses the data of the memory cell.

Technical Solution

[15] In order to accomplish the above object, the memory cell of the present invention includes a single electron transistor; a first transistor connected at a source thereof to a drain of the single electron transistor, and at a gate thereof to ground voltage; a second transistor connected at a source thereof to the drain of the first transistor, at a drain thereof to power supply voltage and at the source and a gate thereof to a gate of the single electron transistor; a third transistor connected at a gate thereof to a first word line, and at a source thereof to the gate of the single electron transistor; a fourth transistor connected at a gate thereof to the gate of the single electron transistor, and at a drain thereof to a drain of the third transistor; and a fifth transistor connected at a drain thereof to a bit line, at a gate thereof to a second word line, and at a source thereof to the drain of the third transistor.

[16] According to the referred embodiments, the first and second transistors are respectively depletion type NMOS transistors, and the third and fifth transistors are re- spectively NMOS transistors. Furthermore, the single electron transistor includes a source and the drain formed on a semiconductor substrate; a metal island configured to form a tunnel junction between the source and the drain of the single electron transistor, and located between the source and the drain of the single electron transistor; and the gate located adjacent to the metal island and configured to control current flowing through the metal island.

[17] In order to accomplish another object, the memory device includes a main memory cell having a first single electron transistor; a reference memory cell having a second single electron transistor; a first precharge unit connected to a bit line of the main memory cell and configured to generate a cell voltage depending on data stored in the main memory cell; a second precharge unit connected to a reference bit line of the reference memory cell and configured to generate reference voltage depending on data stored in the reference memory cell; and a sense amplifier configured to sense and amplify the cell voltage and the reference voltage.

[18] According to the referred embodiments, the first precharge unit includes a first

PMOS transistor connected at a source thereof to power supply voltage, and configured to have a gate and a drain connected to each other; a first NMOS transistor connected at a drain thereof to the drain of the first PMOS transistor and at a source thereof to the bit line; an inverter connected at an input thereof to the bit line, and at an output thereof to the gate of the first NMOS transistor; a second PMOS transistor connected at a source thereof to the power supply voltage and at a gate thereof to the gate of the first PMOS transistor, and configured to generate the cell voltage at a drain thereof; and a second NMOS transistor connected at a drain and a gate thereof to the drain of the second PMOS transistor, and at a source thereof to ground voltage.

Advantageous Effects

[19] As a result, according to the present invention, an MV-SRAM cell having an SET operates only using two row lines and one column line, so that memory integration is improved and manufacturing cost per memory bit decreases.

Description of Drawings

[20] The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[21] FIGS. 1 and 2 are diagrams illustrating a SET;

[22] FIGS. 3 and 4 are diagrams illustrating the circuit and operation characteristics of a universal literal gate in which the SET and a MOS transistor are combined together;

[23] FIGS. 5 and 6 are diagrams illustrating the circuit and operation characteristics of a quantizer using the universal literal gate; [24] FIGS. 7 and 8 are diagrams illustrating the circuit and operation characteristics of a conventional MV-SRAM cell. [25] FlG. 9 is a diagram illustrating the memory array of the MV-SRAM cells of the

FIG. 7; [26] FlG. 10 is a diagram illustrating a memory cell employing an SET according to an embodiment of the present invention; [27] FlG. 11 is a diagram illustrating a memory array including the memory cells of

FlG. 10; [28] FlG. 12 is a diagram illustrating the operation timing of the memory cell of FlG.

10; [29] FlG. 13 is a diagram of a memory device according to an embodiment of the present invention; and [30] FlG. 14 is a diagram illustrating the operation timing of the memory device of FlG.

13.

Best Mode [31] Reference now should be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components. [32] FlG. 10 is a diagram illustrating an MV-SRAM cell 600 according to an embodiment of the present invention. Referring to FlG. 10, the MV-SRAM cell 600 includes a SET 100 and first to fifth transistors Ml, M2, M3, M4 and M5. [33] The first transistor Ml is composed of a depletion type NMOS transistor that is connected at the source thereof to the drain 105 of the SET 100, at the gate thereof to ground voltage VSS, and at the drain thereof to the source of the second transistor M2. [34] The second transistor M2 is composed of a depletion type NMOS transistor that is connected at the source thereof to the drain of the first transistor Ml, at the drain thereof to power supply voltage Vdd, and at the drain and gate thereof to the gate 120 of the single-electron transistor 100. [35] The third transistor M3 has connected at the gate thereof to a first word line WL, and at the source thereof to the gate 120 of the single-electron transistor 100 and the drains of the first and second transistors. [36] The fourth transistor M4 is composed of an NMOS transistor that is connected at the gate thereof to the gate 120 of the single-electron transistor 100, the drains of the first and second transistors and the source of the third transistor M3, and at the drain thereof to the drain of the third transistor M3. The source of the fourth transistor M4 is connected to the ground voltage VSS via the sixth transistor M6 of FlG. 11, which will be described below. [37] The fifth transistor M5 is composed of an NMOS transistor that is connected at the drain thereof to a bit line BL, at the gate thereof to a second word line SWL, and at the source thereof to the drains of the third and fourth transistors.

[38] A node, to which the drain of the first transistor Ml, the source of the second transistor M2, the source of the third transistor M3, and the gate of the single-electron transistor 100 are connected, is a storage node SN for storing the data of the MV- SRAM cell.

[39] FlG. 11 is a diagram illustrating a cell array in which the MV-SRAM cells of FlG.

10 are arranged. Referring to FlG. 11, the MV-SRAM cells 600 are arranged in columns and rows. The cells are respectively connected to first and second word line pairs WLO and SWLO, WLl and SWLl, WL2 and SWL2, and WL3 and SWL3 in a column direction, and to a bit line BLO, BLl, BL2, BL3 and BL4 in a row direction. The cells are connected to the sixth transistor in common. The sixth transistor is connected at the gate thereof to a control signal SC, is connected at the drain thereof to the sources of the fourth transistors M4 in the cell 600, and is connected at the source thereof to the ground voltage VSS. The sources of the fourth transistors M4 are connected to the sixth transistor M6 in common and used, so that area penalty is low.

[40] During a write operation, the sixth transistor M6 is turned off so that the level of the data stored in the SN node is not decreased, and power consumption is decreased. During a read operation, the sixth transistor M6 is turned on, so that the sources of the fourth transistors M4 have a ground level, and therefore current flows from a precharge circuit (not shown) connected to the bit line BL to transistors M5, M4 and M6 via the bit line BL.

[41] FlG. 12 is a timing diagram illustrating the operation of the MV-SRAM of FlG. 10.

Referring to FlG. 12, upon a write operation, the first and second word lines WL and SWL are simultaneously enabled at timing tl. When voltage corresponding to a two- bit of logic data value, for example, '11', '10', ¹Ol', or '00', is applied to the bit line BL at timing tθ, the corresponding voltage is stored in the SN node. At this time, since the sixth transistor M6 is turned off, current does not flow through the fourth transistor M4, so that additional power consumption and the voltage loss of the SN node do not occur. After the write operation has been performed on the SN node, the first word line WL is disabled at timing t2 and the bit line is precharged to ground voltage VSS at timing t3, the write operation is completed. According to the write operation, the second word line SWL and the control signal SC are enabled while the first word line WL is maintained at ground voltage VSS. Then, current flows from a precharge transistor (FlG. 13) connected to the bit line BL into the fourth transistor M4 via a column decoder (not shown) and the bit line BL.

[42] FlG. 13 is a circuit diagram illustrating the operation of sensing current flowing into the cell via the precharge transistor and the column decoder during the above- described write operation. Referring to FlG. 13, a first precharge unit 910A and a second precharge unit 910B are connected to a sense amplifier 900. The first precharge unit 910A is connected to the bit line BL of a main MV-SRAM cell 920 via the NMOS transistor 921 of a column decoder 920. The second precharge unit 910B is connected to the reference bit line RBL of a reference MV-SRAM cell 600B via the NMOS transistor 922 of the column decoder 920.

[43] The first precharge unit 910A includes a first PMOS transistor 911 connected at the source thereof to power supply voltage VDD and configured to have a gate and a drain connected to each other, a first NMOS transistor 912 connected at the drain thereof to the drain of the first PMOS transistor 911, and at the source thereof to the drain of the NMOS transistor 921 of the column decoder 920, an inverter connected at the input thereof to the source of the column decoder 920, and at the output thereof to the gate of the first NMOS transistor 912, a second PMOS transistor 914 connected at the source thereof to power supply voltage VDD, at the gate thereof to the gate of the first PMOS transistor 911, and configured to generate cell voltage Vmain at the drain thereof, and a second NMOS transistor 915 connected at the drain and gate thereof to the drain of the second PMOS transistor 914, and at the source thereof to ground voltage VSS. The second precharge unit 910B is configured similar to the first precharge unit 910A.

[44] Each of the main MV-SRAM cell 600A and the reference MV-SRAM 600B is identical to the above-described MV-SRAM cell 600 of FIG. 10. The reference MV- SRAM cell 600B provides reference current Iref depending on a reference voltage value stored in an RSN node. The reference voltage value stored in the RSN node is a middle value between a logic '0' and a logic T which are stored in the SN node of the main MV-SRAM cell 600A. The main MV-SRAM cell 600A provides a predetermined cell current depending on a logic level stored in the SN node.

[45] When the first column selection signal YA and second column selection signal

RYA of the column decoder 920 are enabled, the cell voltage Vmain is generated based on the cell current Imain at the first precharge unit 910A, the reference voltage Vref is generated based on the reference current Iref at the second precharge unit 910B. The sense amplifier 900 compares the reference voltage Vref and the cell voltage, and generates an output signal as a comparison result. At this time, the generated output signal is data stored in the main MV-SRAM Cell 600A.

[46] FIG. 14 is a diagram illustrating the sensing operation of the circuit of FIG. 13. For convenience of description, a binary sensing operation is described as an example, rather than a multiple value sensing operation. When a stored voltage corresponding to the logic '0' is VSNO, and a stored voltage corresponding to the logic T is VSNl, the relationship between the cell current Imain and the reference current Iref during a read operation is determined as follows: [47] ImainO < Iref < Imainl (1)

[48] where ImainO is the cell current when the data stored in the main MV-SRAM cell

600A is the logic ¹O', and Imainl is the cell current when the data stored in the main MV-SRAM cell 600A is the logic T.

[49] The relationship between the first and node voltages VM and VR of the first and second precharge units 910A and 910B, and the cell voltage Vmain and the reference voltage Vref are as follows:

[50] VMl < VR < VMO

[51] Vmainl < Vref < VmainO

[52] where VMl and Vmainl are the first node voltage VM and the cell voltage Vmain when the data stored in the main MV-SRAM cell 600A is T, and VMO and VmainO are the first node voltage VM and the cell voltage Vmain when the data stored in the main MV-SRAM cell 600A is ¹O'.

[53] Referring to FlG. 14, when the second word line SWL and the second reference word line RSWL are enabled and the first and second column selection signals YA and RYA are activated, the first node voltage VM and the cell voltage Vmain are determined depending on the data stored in the main MV-SRAM cell 600A. The output voltage Vout corresponding to the data stored in the main VM-SRAM cell is generated by the sense amplifier 900 that senses and amplifies the cell voltage Vmain and the reference voltage Vref.

[54] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Industrial Applicability

[55] According to the above-described invention, an MV-SRAM cell having an SET uses two row lines and one column line, so that memory integration is improved and manufacturing cost per memory bit decreases.

Claims

[1] L A memory cell, comprising: a single electron transistor; a first transistor connected at a source thereof to a drain of the single electron transistor, and at a gate thereof to ground voltage; a second transistor connected at a source thereof to the drain of the first transistor, at a drain thereof to power supply voltage and at the source and a gate thereof to a gate of the single electron transistor; a third transistor connected at a gate thereof to a first word line, and at a source thereof to the gate of the single electron transistor; a fourth transistor connected at a gate thereof to the gate of the single electron transistor, and at a drain thereof to a drain of the third transistor; and a fifth transistor connected at a drain thereof to a bit line, at a gate thereof to a second word line, and at a source thereof to the drain of the third transistor.

2. The memory cell as set fourth in claim 1, wherein the first transistor is a depletion type NMOS transistor.

3. The memory cell as set fourth in claim 1, wherein the second transistor is a depletion type NMOS transistor.

4. The memory cell as set fourth in claim 1, wherein the third transistor is an NMOS transistor.

5. The memory cell as set fourth in claim 1, wherein the fourth transistor is an NMOS transistor.

6. The memory cell as set fourth in claim 1, wherein the fifth transistor is an NMOS transistor.

7. The memory cell as set fourth in claim 1, wherein the single electron transistor comprises: a source and the drain formed on a semiconductor substrate; a metal island configured to form a tunnel junction between the source and the drain of the single electron transistor, and located between the source and the drain of the single electron transistor; and the gate located adjacent to the metal island and configured to control current flowing through the metal island.

8. A memory device, comprising: a main memory cell having a first single electron transistor; a reference memory cell having a second single electron transistor; a first precharge unit connected to a bit line of the main memory cell and configured to generate a cell voltage depending on data stored in the main memory cell; a second precharge unit connected to a reference bit line of the reference memory cell and configured to generate reference voltage depending on data stored in the reference memory cell; and a sense amplifier configured to sense and amplify the cell voltage and the reference voltage.

9. The memory device as set fourth in claim 8, wherein the main memory cell comprises: the first single electron transistor; a first transistor connected at a drain thereof to a drain of the first single electron transistor, and at a gate thereof to ground voltage; a second transistor connected at a source thereof to the drain of the first transistor, at a drain thereof to power supply voltage, and at the source and a gate thereof to a gate of the first single electron transistor; a third transistor connected at a gate thereof to a first word line, and at a source thereof to the gate of the first single electron transistor; a fourth transistor connected at a gate thereof to the gate of the first single electron transistor, and at a drain thereof to a drain of the third transistor; and a fifth transistor connected at a drain thereof to the bit line, at a gate thereof to a second word line, and at a source thereof to the drain of the third transistor.

10. The memory device as set fourth in claim 8, wherein the reference memory cell comprises: the second single electron transistor; a first transistor connected at a drain thereof to a drain of the second single electron transistor, and at a gate thereof to ground voltage; a second transistor connected at a source thereof to the drain of the first transistor, at a drain thereof to power supply voltage, and at the source and a gate thereof to a gate of the second single electron transistor; a third transistor connected at a gate thereof to a first reference word line, and at a source thereof to the gate of the second single electron transistor; a fourth transistor connected at a gate thereof to the gate of the second single electron transistor, and at a drain thereof to a drain of the third transistor; and a fifth transistor connected at a drain thereof to the reference bit line, at a gate thereof to a second word line, and at a source thereof to the drain of the third transistor.

11. The memory device as set fourth in claim 8, wherein the first precharge unit comprises: a first PMOS transistor connected at a source thereof to power supply voltage, and configured to have a gate and a drain connected to each other; a first NMOS transistor connected at a drain thereof to the drain of the first

PMOS transistor and at a source thereof to the bit line; an inverter connected at an input thereof to the bit line, and at an output thereof to the gate of the first NMOS transistor; a second PMOS transistor connected at a source thereof to the power supply voltage and at a gate thereof to the gate of the first PMOS transistor, and configured to generate the cell voltage at a drain thereof; and a second NMOS transistor connected at a drain and a gate thereof to the drain of the second PMOS transistor, and at a source thereof to ground voltage.

12. The memory device as set fourth in claim 8, wherein the second precharge unit comprises: a first PMOS transistor connected at a source thereof to power supply voltage, and configured to have a gate and a drain connected to each other; a first NMOS transistor connected at a drain thereof to the drain of the first

PMOS transistor, and at a source thereof to the reference bit line; an inverter connected at an input thereof to the reference bit line and at an output thereof to the gate of the first NMOS transistor; a second PMOS transistor connected at a source thereof to the power supply voltage and at a gate thereof to the gate of the first PMOS transistor, and configured to generate the cell voltage at a drain thereof; and a second NMOS transistor connected at a drain and a gate thereof to the drain of the second PMOS transistor, and at a source thereof to ground voltage.