CN101572121A

CN101572121A - Method for reducing memory leakage current

Info

Publication number: CN101572121A
Application number: CNA2008100958320A
Authority: CN
Inventors: 张全仁
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2008-04-29
Filing date: 2008-04-29
Publication date: 2009-11-04

Abstract

The invention provides a method for reducing memory leakage current, which is suitable for a memory. The memory comprises a memory cell, an equipotential circuit, a current limiter, a word line and a pair of paratope lines. After the memory cell is in a precharge mode, the equipotential circuit and the current limiter operate normally to carry out the precharge operation for the paratope lines, and then, periodic control signals are applied to the current limiter to control the conducting state of the current limiter. When the current limiter is not conducted, the standby leakage current of the memory can be interdicted or reduced. The standby leakage current is caused by the short circuit among the word line and the paratope lines.

Description

Reduce the method for memory drain electric current

Technical field

The invention relates to a kind of method of reduction leakage current of storer, and be particularly to ON/OFF current limliting unit suitably to reduce the method for the leakage current of storer under standby mode.

Background technology

(dynamic random access memory DRAM) is present very general semiconductor memory component to dynamic RAM.A storage unit of a DRAM inside normally capacitor constitutes.This storage unit sees through transistor and is connected to bit line (bit line).This transistorized gate terminal is electrically connected to word line, and its source electrode then is to be electrically connected to bit line and capacitor respectively with drain electrode.

Usually under standby mode (standby mode), can carry out precharge (pre-charging), be used for bit line and paratope line (complementary bit line) are precharged to predetermined voltage potential storage unit.For example, bit line and paratope line are precharged to supply voltage VDD, partly supply voltage VDD/2, ground voltage VSS or other reference voltages.

When reading action, word line is a logic high, and making transistor is conducting state.The stored electric charge of capacitor then can transfer to bit line via transistor, so the voltage of bit line has slight change, but paratope line still Wei Te at predetermined voltage potential.Thereby the current potential of bit line and paratope line has small voltage differences, and this small voltage differences can be amplified via sensing amplifier (sense amplifier).

On practical layout, the position of bit line is adjacent to word line very much, so short circuit is easily arranged between bit line and the word line, causes leakage current to occur.When storer during at read-write operation, the power consumption that this leakage current caused is insignificant.But work as storer under standby mode, the power consumption that this leakage current caused preferably can be lowered.

So, the present invention propose a kind of can be under standby mode, reduce the leakage current of storer, to reduce the method for unnecessary power loss.

Summary of the invention

The invention provides a kind of method that reduces the memory drain electric current.ON time when utilizing periodic signal to control precharge.When periodic signal was logic low, precharge circuit was a not on-state.At this moment, then do not have the situation appearance of leakage current.

One of example of the present invention proposes a kind of method that reduces the memory drain electric current, be applicable to storer, this storer comprises at least: storage unit, equipotential circuit, current limliting unit, word line and a pair of paratope line, and the method comprises: make storage unit enter precharge mode; Make equipotential circuit and the normal running of current limliting unit, so that this is carried out precharge operation to paratope line; Apply cyclic control signal conducting or not conducting with control current limliting unit in the current limliting unit, wherein the not conducting meeting of current limliting unit reduces the standby leakage current of storer, and this standby leakage current is caused the short circuit between paratope line therewith by word line.

Another example of the present invention proposes a kind of method that reduces the memory drain electric current, be applicable to storer, this storer comprises at least: storage unit, equipotential circuit, current limliting unit, word line and a pair of paratope line, and method comprises: make storage unit enter a precharge mode; Make equipotential circuit and the normal running of current limliting unit, so that this is precharged to a reference voltage to paratope line; Apply one-period property control signal in the current limliting unit to reduce the ON time of current limliting unit, and the standby leakage current of reduction storer, standby leakage current sees through word line by a reference voltage and therewith the short circuit between paratope line is flowed out, and wherein the logic low potential of cyclic control signal is relevant for the negative pre-charge voltage of word line.

Comprehensive the above, example of the present invention utilizes cyclic control signal, makes storer under precharge pattern, intermittently a pair of paratope line is carried out precharge, with effective reduction leakage current.Simultaneously, also allow this a pair of paratope line remain on precharge state.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:

Fig. 1 is the synoptic diagram of storer.

Fig. 2 is for reducing the sequential chart of the control voltage Vint of leakage current according to being used in one embodiment of the invention.

The main element symbol description:

101: capacitor

102: word line switch

103: the equipotential circuit

103a, 103b and 103c: equipotential contactor

104: the current limliting unit

BL: bit line

BL: paratope line

VBLEQ: reference voltage

EQL: Equal-position Signal

Vint: control voltage

T: cycle

T1: the ON time of current limliting unit 104

T2: the shut-in time of current limliting unit 104

Embodiment

In embodiments of the present invention, see through and periodically to control the switch that voltage comes the current limliting unit of control store, when being reduced in standby mode, the leakage current between bit line and word line.

Fig. 1 is the part synoptic diagram of storer.As shown in Figure 1, storer comprises capacitor 101, word line switch 102, equipotential circuit 103, current limliting unit 104, word line WL, bit line BL and paratope line BL.Equipotential circuit 103 comprises

equipotential contactor

103a, 103b and 103c.Capacitor 101 can constitute a storage unit.

Word line switch 102 for example is a transistor, and its grid is electrically connected to word line WL, and its drain electrode is coupled to bit line BL, and its source electrode is coupled to capacitor 101.

When word line WL is logic high (represent this storage unit selected), word line switch 102 is a conducting state, is conducting between bit line BL and the capacitor 101.Thus, when storer when carrying out write activity, the data on the bit line BL can write to capacitor 101, and are reading when action when storer, the data of being deposited in the capacitor 101 can read out to bit line BL.

When word line WL is logic low (represent this storage unit not selected), 102 of word line switches are closed condition, then do not have electric connection between bit line BL and the capacitor 101.

Equipotential contactor 103a for example is a transistor, and its grid electrically is controlled by Equal-position Signal EQL, and its drain electrode is coupled to current limliting unit 104, and its source electrode is coupled to bit line BL.

Equipotential contactor 103b for example is a transistor, and its grid is controlled by Equal-position Signal EQL, and its drain electrode is coupled to current limliting unit 104, and its source electrode is coupled to paratope line BL.

Equipotential contactor 103c for example is a transistor, and its grid is controlled by Equal-position Signal EQL, and its drain electrode is coupled to bit line BL, and its source electrode is coupled to paratope line BL.

When Equal-position Signal EQL was logic high, these three

equipotential contactor

103a, 103b and 103c were all opening.At this moment, be short circuit between bit line BL and the paratope line BL, so bit line BL can share mutually with the electric charge on the paratope line BL.And bit line BL and paratope line BL can be electrically connected to current limliting unit 104, make bit line BL and paratope line BL all be precharged to reference voltage VBLEQ (if current limliting unit 104 is under the conducting state).

When Equal-position Signal EQL was logic low, for opening circuit, and bit line BL and paratope line BL did not have the current limliting of being electrically connected to unit 104 between bit line BL and the paratope line BL.

Current limliting unit 104 for example is a transistor, and its control end for example is a grid, is controlled by control voltage Vint.Current limliting unit 104 more couples reference voltage VBLEQ and

equipotential contactor

103a and 103b.

When control voltage Vint was logic high, current limliting unit 104 was an opening, and reference voltage VBLEQ then is electrically connected to

equipotential contactor

103a and 103b.

When control voltage Vint was logic low, current limliting unit 104 was a closed condition, and reference voltage VBLEQ then can't be electrically connected to

equipotential contactor

103a and 103b.

Reference voltage VBLEQ is generally half of bit line noble potential VBLH.Bit line noble potential VBLH is the voltage potential of bit line when logic high.

Then please be simultaneously with reference to Fig. 1 and Fig. 2, Fig. 2 is for reducing the sequential chart of the control voltage Vint of leakage current according to being used in one embodiment of the invention.As shown in the figure, control voltage Vint is a periodic signal, for example is square wave, and its cycle is T.In one-period T, the time that control voltage Vint maintains logic high is t1 (that is ON time of current limliting unit 104), and the time that control voltage Vint maintains logic low is t2 (that is shut-in time of current limliting unit 104).In principle, t1+t2=T.

When storer the time at standby mode, if Equal-position Signal EQL be logic high and control voltage Vint also at logic high, bit line BL and paratope line BL short circuit, and electrically connect with reference voltage VBLEQ.That is bit line BL and paratope line BL are precharged to reference voltage VBLEQ.At this moment, between word line WL and the bit line BL (perhaps, between word line WL and the paratope line BL) if there is situation of short circuit to occur, then this short circuit paths can cause reference voltage VBLEQ to flow out from word line WL via bit line BL.That is to say, have leakage current and occur.

Otherwise when controlling voltage Vint at logic low, reference voltage VBLEQ opens circuit in bit line BL and paratope line BL.So bit line BL and paratope line BL be not by precharge, and the leakage current that does not have from reference voltage VBLEQ flows out from word line WL.

Under the storer standby mode, maintain reference voltage VBLEQ for making bit line BL and paratope line BL as far as possible, and effectively reduce leakage current.Work period (duty cycle) and the frequency thereof of control voltage Vint need be controlled at suitable size.

Hold above-mentionedly,, then control the logic low potential of voltage Vint and can establish the negative voltage of identical size if when word line WL will be precharged to negative voltage.

In addition, it should be noted that control voltage Vint can be other synthetic string ripple,, get final product that present embodiment does not limit so that bit line BL and paratope line BL maintain reference voltage VBLEQ at the storer standby mode such as being triangular wave etc.

In sum, the present invention utilizes periodicity to control voltage Vint and controls current limliting unit 104, makes bit line BL and paratope line BL continue charging, uncharged the time, leakage current can not produce, to reduce the leakage current of storer at standby mode.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims

1. a method that reduces the memory drain electric current is applicable to a storer, and this storer comprises: at least one storage unit, an equipotential circuit, a current limliting unit, a word line and a pair of paratope line, and this method comprises:

Make this storage unit enter a precharge mode;

Make this equipotential circuit and this current limliting unit normal running, so that this is carried out a precharge operation to paratope line;

Apply one-period property control signal in this current limliting unit to control the conducting or the not conducting of this current limliting unit, wherein the not conducting of this current limliting unit reduces a standby leakage current of this storer, and this standby leakage current is caused the short circuit between paratope line by this word line and this.

2. the method for reduction memory drain electric current as claimed in claim 1 is characterized in that, also comprises:

Provide an equipotential signal to control the operation of this equipotential circuit.

3. the method for reduction memory drain electric current as claimed in claim 1 is characterized in that, when this equipotential circuit normal running, this is to being short circuit between the paratope line.

4. the method for reduction memory drain electric current as claimed in claim 1 is characterized in that, also comprises: apply a reference voltage to this current limliting unit.

5. the method for reduction memory drain electric current as claimed in claim 4 is characterized in that, when this equipotential circuit and the normal running of this current limliting unit, this is precharged to this reference voltage to paratope line.

6. the method for reduction memory drain electric current as claimed in claim 5 is characterized in that, this reference voltage is this to half of the logic high potential of paratope line.

7. the method for reduction memory drain electric current as claimed in claim 1 is characterized in that, this cyclic control signal is a square wave or a synthetic string ripple.

8. the method for reduction memory drain electric current as claimed in claim 1 is characterized in that, the logic low potential of this cyclic control signal is same as a negative pre-charge voltage of this word line.

9. a method that reduces the memory drain electric current is applicable to a storer, and this storer comprises: at least one storage unit, an equipotential circuit, a current limliting unit, a word line and a pair of paratope line, and this method comprises:

Make this storage unit enter a precharge mode;

Make this equipotential circuit and this current limliting unit normal running, so that this is precharged to a reference voltage to paratope line;

Apply one-period property control signal in this current limliting unit with an ON time that reduces this current limliting unit and a standby leakage current that reduces this storer, this standby leakage current sees through this word line by a reference voltage and this flows out the short circuit between paratope line, and wherein the logic low potential of this cyclic control signal is relevant for a negative pre-charge voltage of this word line.

10. the method for reduction memory drain electric current as claimed in claim 9 is characterized in that, also comprises:

11. the method for reduction memory drain electric current as claimed in claim 9 is characterized in that, when this equipotential circuit normal running, this is to sharing electric charge each other between the paratope line.

12. the method for reduction memory drain electric current as claimed in claim 9 is characterized in that, this reference voltage is this to half of the logic high potential of paratope line.

13. the method for reduction memory drain electric current as claimed in claim 9 is characterized in that, this cyclic control signal is a square wave or a synthetic string ripple.