JP7114097B2 - READ CIRCUIT FOR RESISTIVE MEMORY DEVICE AND METHOD FOR READ THE SAME - Google Patents

Description

The present invention relates to a read circuit for a resistive memory device and a read method thereof.

2. Description of the Related Art A resistance change memory device (hereinafter simply referred to as a memory device) in which memory cells are configured using resistance change storage elements is known. Such memory devices include, for example, a ReRAM (Resistive Random Access Memory) having a storage element whose electric resistance changes due to an electric field-induced giant resistance change, and a ferroelectric random access memory (FRAM) using a ferroelectric capacitor as a storage element. and a magnetoresistive memory device using a magnetic tunnel junction element as a storage element using the tunnel magnetoresistive effect. In any memory element, binary (1 or 0) memory data is assigned to the high resistance state and low resistance state of the memory element.

The readout circuit of the memory device as described above has a reference cell that serves as a reference for determining stored data. The reference cell is adjusted to exhibit an intermediate resistance value between the high resistance state and the low resistance state of the storage element of the memory cell.

Known methods for reading data include a precharge method (see, for example, Patent Document 1) and a pull-up method (see, for example, Patent Document 2). Data reading by the precharge method utilizes the parasitic capacitance of the bit line to which the memory cell is connected and the dummy bit line to which the reference cell is connected, and performs a precharge operation and a read operation in order. In the precharge operation, charges are supplied to the bit line and the dummy bit line through a bit line load including a switching element to charge (precharge) them to a specific potential. In the read operation, the bit line and the dummy bit line are discharged through the memory cell and the reference cell, and the discharging speed at this time, that is, the potential difference between the discharging bit line and the dummy bit line is detected.

On the other hand, in pull-up data reading, a pull-up current is supplied from the bit line load circuit to the memory cell via the bit line, and at the same time, a pull-up current is supplied to the reference cell via the dummy bit line. A read operation is performed to detect the potential difference between the line and the dummy bit line.

As a reference cell, for example, a MOS transistor whose drain is connected to a bit line is applied with a predetermined gate voltage to function as a reference cell resistor (hereinafter referred to as a MOS type). (See Patent Document 3, for example). Also known is a memory cell that uses the same memory element as the memory cell (hereinafter referred to as memory element type).

In the above memory element type reference cell, the memory element in the low resistance state and the memory element in the high resistance state are connected, and the resistance value RL of the memory element in the low resistance state and the resistance value RH of the memory element in the high resistance state are obtained as a whole. and an intermediate resistance value (=(RL+RH)/2). In general, in order to suppress the influence of variations in manufacturing processes and variations in temperature characteristics, one reference cell is configured by connecting a plurality of storage elements in a low resistance state and a plurality of storage elements in a high resistance state.

FIG. 22 shows the configuration of a conventional storage element type reference cell 90 . This reference cell 90 has four sub-circuits 91 connected in parallel. Each sub-circuit 91 initializes a series circuit in which two MTJ elements 93a and 93b in the high resistance state and two MTJ elements 93c and 93d in the low resistance state are connected in series, and the MTJ elements 93a to 93d. Transistors 94a-94d, 95a-95c and a switch element 96 are provided for switching. For initialization, the switches 94a to 94d and 95a to 95c are combined to be turned on while the switch element 96 is turned on, so that write currents are supplied to the MTJ elements 93a to 93d in order, thereby The MTJ elements 93a-93d are set to either a high resistance state or a low resistance state. For example, by turning on the transistors 94a and 95a, the MTJ element 93a is brought into a high resistance state. Also, by turning on the transistors 95c and 94d, the MTJ element 93d is brought into a low resistance state.

Japanese Patent Application Laid-Open No. 2009-230798 JP 2012-243364 A JP 2010-92521 A

By the way, the reference cell of the storage element type described above can be used for reading data by either the precharge method or the pull-up method, but each storage element requires one or more transistors for initialization. , and there is a problem of increasing the circuit area of the memory device. For example, in the configuration example of FIG. 22, seven transistors for initialization are required for four MTJ elements, and one reference cell requires 28 transistors. It is conceivable to apply the same current to a plurality of memory elements connected in series to change the resistance states of the memory elements all at once. , and the precision of the resistance value decreases, which is not preferable.

On the other hand, the MOS type reference cell can have a smaller circuit area than the memory element type, but detects the potential difference between the bit line and the dummy bit line while the potential of the dummy bit line is changing. It is unsuitable for precharge data reading because the operation margin is small. That is, since the resistance value of the reference transistor changes depending on the potential of the dummy bit line, the period during which the potential difference between the bit line and the dummy bit line corresponding to the data to be read from the memory cell is obtained is extremely short. It was difficult to read the data. Further, in the pull-up data reading, the potential difference between the bit line and the dummy bit line is detected while the pull-up current is constantly flowing through the memory cell and the reference cell. There is a problem that the power consumption is larger than that of the precharge method that charges the parasitic capacitance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a readout circuit for a resistive memory device and a method for reading the same, which is advantageous for power saving and can achieve a small area. .

The present invention provides a read circuit for a resistance change memory device including a memory cell including a resistance change storage element, wherein a first bit line connected to the memory cell is paired with the first bit line. and a reference cell for generating a reference potential on the second bit line, wherein the reference cell has a drain connected to the second bit line. a reference transistor connected, a select transistor connected between the source of the reference transistor and ground and having a gate connected to a word line; and a potential of the second bit line fed back to the gate of the reference transistor. and a feedback section for changing the potential of the gate of the reference transistor in the same direction as the potential of the second bit line changes.

Further, according to the present invention, the memory cell stores information based on the potential difference between a first bit line connected to a memory cell including a resistance change storage element and a second bit line connected to a reference cell. In the reading method of a resistance change type memory device for reading data from a memory device, a current from the second bit line is caused to flow through a reference transistor connected to the second bit line when reading data. a reference potential generation step of generating a reference potential on the second bit line; and a reference potential generation step performed during the generation of the reference potential, in accordance with a change in the potential of the second bit line, in the same direction as the change in the potential of the reference transistor. and a feedback step of feeding back the potential of the second bit line to the gate of the reference transistor so as to change the potential of the gate.

According to the present invention, the potential of the second bit line is fed back to the gate of the reference transistor, and the potential of the gate of the reference transistor is changed according to the change of the potential of the second bit line. is maintained substantially constant regardless of changes in the potential of the second bit line. Therefore, the area can be reduced by using the reference transistor, and data can be read by the precharge method while securing an operation margin. It is possible to detect the potential difference between the line and the second bit line, and power can be saved.

1 is a circuit diagram showing a main part of a resistive memory device according to a first embodiment; FIG. 4 is a circuit diagram showing a sense circuit section; FIG. 5 is a graph schematically showing changes in potentials of the gate and source of a reference transistor and dummy bit lines; 4 is a graph showing simulation results of changes in potentials of bit lines and dummy bit lines; 7 is a graph showing simulation results of changes in potentials of a bit line and a dummy bit line when a reference cell is not provided with a feedback section; FIG. 10 is a graph showing simulation results of sense amplifier outputs when a memory cell stores data “1”; FIG. FIG. 10 is a graph showing simulation results of sense amplifier outputs when a memory cell stores data “0”; FIG. FIG. 10 is a circuit diagram showing a sense circuit section of a resistance change type memory device according to a second embodiment; 10 is a graph showing simulation results of potential changes of a pair of signal lines that are inputs to a sense amplifier in the second embodiment; FIG. 10 is a circuit diagram showing a sense circuit unit used in the simulation of FIG. 9; FIG. 10 is a graph showing a simulation result of potential change of a pair of signal lines in a circuit configuration similar to that of the simulation of FIG. 9 when no feedback section is provided in the reference cell; FIG. FIG. 10 is a graph showing simulation results of outputs of bit lines, dummy bit lines, and sense amplifiers when memory cells store data “1” in the second embodiment; FIG. FIG. 10 is a graph showing simulation results of outputs of bit lines, dummy bit lines, and sense amplifiers when memory cells store data “0” in the second embodiment; FIG. FIG. 11 is a circuit diagram showing a pull-up type sense circuit section of a resistance change type memory device according to a third embodiment; FIG. 11 is a graph showing simulation results of changes in potential of each signal line in the third embodiment; FIG. FIG. 10 is a graph showing simulation results of changes in the potential of each signal line of the pull-up system when the reference cell is not provided with a feedback section; FIG. FIG. 4 is a circuit diagram showing a feedback section that feeds back a dummy bit line potential to the gate of a reference transistor using a transistor; 4 is a circuit diagram showing a feedback section that feeds back a dummy bit line potential to the gate of a reference transistor using a MOS diode; FIG. 4 is a circuit diagram showing a feedback section that feeds back a dummy bit line potential to the gate of a reference transistor by a source follower circuit; FIG. FIG. 3 is an explanatory diagram showing an example layout of a memory array in which memory cells and references are connected to common bit lines; FIG. 10 is an explanatory diagram showing another example of the layout of a memory array in which memory cells and references are connected to common bit lines; 1 is a circuit diagram showing a conventional reference cell; FIG.

[First embodiment]
As shown schematically in FIG. 1, a resistive memory device (hereinafter simply referred to as a memory device) 10 includes a memory array in which a plurality of memory cells 12 and reference cells 14 are arranged in a matrix. ing. A sense circuit section 15 is provided in each column of the memory array. In FIG. 1, only one memory cell 12, one reference cell 14 provided corresponding to the column, and the sense circuit section 15 are illustrated. Although not shown, the memory device 10 is provided with peripheral circuits including column decoders and row decoders for selecting the memory cells 12 and the reference cells 14 and supplying potentials through various signal lines.

In the memory device 10, bit lines BL as first bit lines are provided for each column, and word lines WL as first word lines are provided for each row. The bit lines BL extend in the column direction (vertical direction in the drawing), and the word lines WL extend in the row direction (horizontal direction in the drawing). The memory cells 12 are provided at intersections between bit lines BL and word lines WL. Memory cells 12 in the same column are connected to the same bit line BL, and memory cells 12 in the same row are connected to the same word line WL.

In the memory array, dummy bit lines DBL as second bit lines are provided corresponding to respective columns, and dummy word lines DBL as second word lines are provided in rows in which the reference cells 14 are arranged. A line DWL is provided. Dummy bit lines DBL extend in the column direction, and dummy word lines DWL extend in the row direction. A reference cell 14 is connected to each dummy bit line DBL. Each reference cell 14 is connected to the dummy word line DWL.

A first bit line is a bit line to which a memory cell 12 to be read is connected when data is read, and whose potential changes in a manner based on the data stored in the memory cell 12 . A bit line connected to the reference cell 14 used when reading data from the memory cell 12 is a second bit line. A word line that selects a row of memory cells 12 to be read is a first word line, and a word line that selects a row of reference cells 14 used when reading the memory cell 12 is a second word.

The memory cell 12 has an MTJ (Magnetic Tunnel Junction) element (magnetic tunnel junction element) 17 as a resistance change memory element and a selection transistor 18 of an NMOS transistor. As the MTJ element 17, a two-terminal type element having a configuration in which a magnetization fixed layer and a magnetization free layer are laminated with an insulating film interposed therebetween, and terminals are provided for each of the magnetization fixed layer and the magnetization free layer is used. ing. The memory cell 12 can store one bit in the magnetization state of the MTJ element 17, that is, the magnetization direction of the magnetization free layer with respect to the magnetization fixed layer whose magnetization direction is fixed. The MTJ element 17 is in a low resistance state with a small resistance value when the magnetization directions of the magnetization fixed layer and the magnetization free layer are parallel to each other, and the magnetization direction of the magnetization free layer is opposite to that of the magnetization fixed layer. In the anti-parallel state, a high resistance state is obtained in which the resistance value is large. For example, the MTJ element 17 is assigned a low resistance state for data "0" and a high resistance state for data "1". In the following description, RL is the resistance value of the MTJ element 17 in the low resistance state, RH is the resistance value in the high resistance state, and R _AVE (=(RL+RH)/2) is the intermediate resistance value between them. and

The MTJ element 17 and the selection transistor 18 are connected in series, and the series circuit is connected between the bit line BL and ground during reading. Specifically, one end of the MTJ element 17 is connected to the bit line BL, the other end is connected to the drain of the selection transistor 18, and the source of the selection transistor 18 is connected to the first source line SL1. A source line SL1 is grounded via a first source line switch section (not shown) connected thereto. The select transistor 18 has its gate connected to the word line WL, and is turned on when the connected word line WL is activated (H level) by the row decoder.

It should be noted that some or all of the transistors, including the select transistor 18, can be configured using vertical MOS transistors that are advantageous for high-density mounting, and such a configuration can further reduce the circuit area. becomes.

When writing data to or reading data from the memory cells 12, the word line WL of the row to be written or read is activated. When writing data, with the select transistor 18 turned on, the potential of the bit line BL connected to the memory cell 12 to which data is to be written is set higher than that of the source line according to the data (1 or 0) to be written. By making it higher or lower, the direction of the write current flowing through the MTJ element 17 is changed. When controlling the direction of the current, the bit line BL is switched between the state of being grounded and the state of being connected to the power supply voltage VDD, and the state of the first source line SL1 is switched between the state of being connected to the power supply voltage VDD and the state of being grounded. switch. The connection state of the first source line SL1 is switched by the above-described first source line switch section.

The reference cell 14 constitutes a readout circuit 20 . The read circuit 20 is for reading data stored in the memory cell 12, and includes the bit line BL, the dummy bit line DBL, the sense circuit section 15, etc. in addition to the reference cell 14. FIG. In this example, a precharge method is adopted as a data read method, and data read by the read circuit 20 includes a precharge operation of precharging the parasitic capacitances of the bit line BL and the dummy bit line DBL, and precharging the parasitic capacitance of the bit line BL and the dummy bit line DBL. There is a read operation which is performed in a read period after the precharge operation and detects a difference in discharge speed between the bit line BL and the dummy bit line DBL as a potential difference.

The reference cell 14 generates a dummy bit line potential _{V_DBL} on the dummy bit line _DBL during a read operation. This reference cell 14 has a reference transistor 27 , a selection transistor 28 and a feedback section 30 . Both the reference transistor 27 and the selection transistor 28 are NMOS transistors.

The reference transistor 27 and selection transistor 28 are connected in series, and the series circuit is connected between the dummy bit line DBL and the ground. Specifically, the reference transistor 27 has a drain connected to the dummy bit line DBL and a source connected to the drain of the select transistor 28 . The select transistor 28 is connected to a second source line SL2 whose source is grounded. The reference transistor 27 has its gate connected to the feedback section 30 and the gate potential _Vg thereof is controlled by the feedback section 30 . The select transistor 28 has its gate connected to the dummy word line DWL, and is turned on when the dummy word line DWL is activated (H level) by the row decoder.

As will be described later, in a configuration in which the bit lines to which the memory cells 12 are connected can serve as the first bit line and the second bit line, a second source line switch section similar to the first source line switch section ( (not shown) is connected to the second source line SL2, and the second source line SL2 is switched between a state of being connected to the power supply voltage VDD and a state of being grounded by the second source line switch section.

The feedback unit 30 feeds back the dummy bit line potential VDBL of the dummy bit line _DBL to the gate of the reference transistor 27, and according to the change of the dummy bit line potential _VDBL , the gate potential _Vg of the reference transistor 27 in the same direction as the change. change. In this example, the feedback section 30 is composed of capacitors 31 and 32 and a switch element 33 .

A capacitor 31 as a bit line side capacitance component has one end connected to the dummy bit line DBL and the other end connected to the gate of the reference transistor 27 . The dummy bit line _DBL and the gate of the reference transistor 27 are capacitively coupled by the capacitor 31 connected in this way. The gate potential _Vg of 27 is also lowered. The bit line side capacitance component does not necessarily need to be provided in the form of an element. It can also be implemented as a side capacitance component.

A capacitor 32 as a ground-side capacitance component has one end connected to the gate of the reference transistor 27 and the other end grounded. This capacitor 32 is provided to keep the gate potential _Vg of the reference transistor 27 stable against noise. Further, as will be described later, by appropriately setting the capacitance of the capacitor 31 and the capacitance of the capacitor 32, the amount of change in the gate potential _Vg of the reference transistor 27 in the read operation can be adjusted. Capacitors 31 and 32 are formed, for example, as MOS capacitors. It should be noted that the ground-side capacitance component does not necessarily have to be provided in the form of an element, like the bit-line-side capacitance component. For example, as the ground-side capacitance component, there is a predetermined equivalent capacitance between the gate of the reference transistor 27 and the ground due to the wiring capacitance, the parasitic capacitance of the switch element 33, etc., so that the amount of change in the gate potential _Vg can be appropriately adjusted. It just needs to be implemented. Note that the capacitor 31 is a bit line side capacitor, and the capacitor 32 is a ground side capacitor.

The switch element 33 has one end connected to the gate of the reference transistor 27 and the other end connected to a potential supply section (not shown) that outputs an initial gate potential _VR1 . The switch element 33 is composed of a transistor, for example, and is turned on during the precharge operation to set the gate potential _{Vg of the reference transistor 27 to the initial gate potential VR1 .} This switch element 33 is turned off during the read operation.

The initial gate potential V _R1 is the gate potential V _g that makes the equivalent resistance (drain-source on-resistance) Ron of the reference transistor 27 equal to the intermediate resistance value R _AVE at the start of the read period. The initial gate potential V _R1 can be determined based on the characteristics of the reference transistor 27 by using the initial bit line potential V _B0 , which is the potential at the start of the read period of the dummy bit line DBL, as the drain potential of the reference transistor 27 . At the start of the detection period, the bit line potential VBL of the bit line _BL and the dummy bit line potential _VDBL of the dummy bit line _DBL are set to the same initial bit line potential VB0.

The above-mentioned potential supply section has, for example, a circuit in which a plurality of MTJ elements that are the same as the memory cell 12 are connected, and the _circuit changes the initial gate potential VR1. As a result, variation compensation and temperature compensation for variations in the manufacturing process of the MTJ element are performed. By supplying the initial gate potential _VR1 from, for example, one potential supply unit to each reference cell 14 of the memory device 10, an increase in the circuit area of the memory device 10 can be suppressed.

The feedback section 30 configured as described above stably maintains the equivalent resistance Ron of the reference transistor 27 at the intermediate resistance value _RAVE during the readout period (all or most of the period). That is, when the source potential of the reference transistor 27 is V _s and the threshold voltage is V _t , “(V _g −V _s )≧{(V _DBL −V _s )+V _t }≧V _t ” in the read period. The initial bit line potential V _B0 , the initial gate potential V _R1 , the capacities of the capacitors 31 and 32, and the threshold voltage V _t of the reference transistor 27 are appropriately selected so as to satisfy the above conditions.

The sense circuit section 15 is connected to the bit lines BL and the dummy bit lines DBL. The sense circuit section 15 has a bit line BL to which the memory cell 12 to be read is connected and a dummy bit line DBL paired with the bit line BL and to which the reference cell 14 is connected. Detects potential difference.

As shown in FIG. 2, the sense circuit section 15 in this example comprises a precharge circuit 36, a potential limiting circuit 37, and a sense amplifier . The precharge circuit 36 is composed of transistors PR1 and PR2 as bit line loads, and the potential limiting circuit 37 is composed of transistors 37a and 37b. The transistors PR1 and PR2 are PMOS transistors, and the transistors 37a and 37b are NMOS transistors.

Sources of the transistors PR1 and PR2 are connected to the power supply voltage VDD. The transistors PR1 and PR2 are connected to the bit line BL and the dummy bit line DBL through the potential limiting circuit 37, respectively. That is, the transistor PR1 has its drain connected to the drain of the transistor 37a, and the source of the transistor 37a connected to the bit line BL. The drain of the transistor PR2 is connected to the drain of the transistor 37b, and the source of the transistor 37b is connected to the dummy bit line DBL.

The transistors PR1 and PR2 are turned on when the precharge signal /PRC is activated (L level). Precharge signal /PRC is activated during the precharge operation. As a result, the power supply voltage VDD is applied to the bit line BL and the dummy bit line DBL through the potential limiting circuit 37 to precharge the bit line BL and the dummy bit line DBL.

A gate voltage Vgn is applied to each gate of the transistors 37a and 37b during the precharge operation. As a result, the bit line potential _{VBL and the dummy bit line potential VDBL in} the precharge operation are limited to the initial bit line potential _VB0 smaller than the power supply voltage VDD for precharging, thereby preventing read disturb.

Sense amplifier 38 is connected to bit line BL and dummy bit line DBL. The sense amplifier 38 detects a potential difference between the bit line potential _VBL and the dummy bit line potential VDBL when the bit line _BL and the dummy bit line DBL are discharged during the read period.

As an example is shown in FIG. 2, the sense amplifier 38 is composed of inverters INV1 and INV2, PMOS transistors 41 to 43, and NMOS transistors 49a and 49b. The inverter INV1 consists of transistors 45 and 46, and the inverter INV2 consists of transistors 47 and 48. FIG. Transistors 45 and 47 are PMOS transistors and transistors 46 and 48 are NMOS transistors.

The transistor 41 has a source connected to the power supply voltage VDD and a drain connected to the sources of the transistors 42 and 43 . The transistor 41 is turned on by activating (L level) the sense signal /SE input to the gate, and starts the operation of the sense amplifier 38 . Sense signal /SE is activated simultaneously with the start of a senseable period set within the read period. The transistor 42 has a gate connected to the bit line BL and a drain connected to the source of the transistor 45 . Similarly, the transistor 43 has its gate connected to the dummy bit line DBL and its drain connected to the source of the transistor 47 .

Gates of the transistors 45 and 46 are connected to each other in the inverter INV1. Transistor 45 has its drain connected to the drain of transistor 46 . The connection point between the drains of these transistors 45 and 46 is the output node n1 of the inverter INV1. In the inverter INV2, the gates of the transistors 47 and 48 are connected to each other, to which the output node n1 is connected. Transistor 47 has its drain connected to the drain of transistor 48 . The connection point between the drains of these transistors 47 and 48 is the output node n2 of the inverter INV2. Also, the output node n2 is connected to the gates of the transistors 45 and 46. FIG.

Transistors 49a and 49b set output nodes n1 and n2 to L level to initialize sense amplifier . The transistor 49a has its drain connected to the output node n1 and its source grounded. Similarly, transistor 49b has its drain connected to output node n2 and its source grounded. Sense signal /SE is input to each gate of transistors 49a and 49b. As a result, the transistors 49a and 49b are turned on by the inactivated (H level) sense signal /SE during the precharge operation before the read operation, that is, before the read period, and the output nodes n1 and n2 are brought to the L level. . In the read period, the transistors 49a and 49b are turned off by activating the sense signal /SE, allowing the potentials of the output nodes n1 and n2 to change.

Sense amplifier 38 configured as described above outputs complementary output signals /D and D from output nodes n1 and n2 based on the potential difference between bit line potential _{VBL and dummy bit line potential VDBL .} When memory cell 12 stores data "1", it outputs L level output signal /D from output node n1 and H level output signal D from output node n2. When the memory cell 12 stores data "0", it outputs an H level output signal /D from the output node n1 and outputs an L level output signal D from the output node n2. Only one of the output signals D and /D may be output.

Next, the capacities of the capacitors 31 and 32 of the feedback section 30 will be explained. In the following description, the start of the operation of the sense amplifier 38 due to the activation of the sense signal /SE is referred to as read start, and the time at which the state of the sense amplifier 38 is stably determined is referred to as the read completion time. Further, for the capacitor ₃₁ , the capacitance is C31, the charge at the read start time is _Q31s , the charge at the read completion time is _Q31f , the capacitance of the capacitor ₃₂ is C32, and the charge at the read start time is _Q32s . , and the charge at the read completion time is Q _32f . The charge of the capacitor 31 is positive and negative with the electrode of the capacitor 31 connected to the dummy bit line DBL as the positive electrode, and the charge of the capacitor 32 is positive and negative with the electrode of the capacitor 32 connected to the gate of the reference transistor 27 being the positive electrode. Define Further, the dummy bit line potential _VDBL at the read completion time is set to _VBf , and the gate potential _{Vg of the reference transistor 27 is set to Vgf .} In order to simplify the explanation, are the capacitive component between the gate and the drain of the reference transistor 27 and the capacitive component parasitic between the gate of the reference transistor 27 and the ground sufficiently small with respect to the capacitance _C31 and the capacitance _C32 ? , or included in each of the capacitors C ₃₁ and C ₃₂ .

At the start of reading, the following formulas (1) and (2) hold. In this example, the capacitors 31 and 32 are charged prior to the start of reading, so the initial charges Q _31s and Q _32s are different for each of the capacitors 31 and 32 .

The following formulas (3) and (4) hold at the read completion time.

From the above equations (2) and (4), the change ΔQ ₃₁ in the charge amount of the capacitor 31 that occurs between the start of reading and the completion of reading is expressed by the following equation (5).

If the potential change of the dummy bit line potential _VDBL is _ΔVB and the potential change of the gate potential _Vg of the reference transistor 27 is _ΔVg , the above equation (5) is expressed as the following equation (6).

Since the dummy bit line potential V _DBL decreases in the read operation, "V _B0 >>V _Bf " and "ΔV _B <0". As for the potential change ΔV _g , "ΔV _g <0", but "|ΔV _B |>|ΔV _g |", and ΔQ ₃₁ becomes negative (ΔQ ₃₁ <0). That is, during the read period, the charge of “|ΔQ31|” is discharged from the positive terminal of the capacitor 31 through the reference transistor 27 . Since the switch element 33 is off during this read period, the charge equal to “|ΔQ31|” is transferred from the positive terminal of the capacitor 32 to the capacitor 31 . Therefore, the following formula (7) holds from formulas (1), (3), and (6).

Since the value (V _gf −V _R1 ) in the equation (7) is the potential change ΔV _g of the gate potential V _g of the reference transistor 27, it can be transformed into the following equation (8).

As shown in equation (8), in this example, the relationship between the potential change _ΔVB of the dummy bit line DBL and the potential change _ΔVg of the gate potential _Vg of the reference transistor 27 during the read period is expressed by the capacitance C ₃₁ and C ₃₂ can be adjusted accordingly. By making these adjustments and appropriately setting the gate width, gate length, and initial gate potential _VR1 of the reference transistor 27, the reference transistor 27 is kept in a linear state during most of the read operation (period). do. That is, adjustment is made so that "(V _g −V _s )≧{(V _DBL −V _s )+V _t }" holds. Such adjustment makes it possible to _stably maintain the equivalent resistance Ron of the reference transistor 27 at the intermediate resistance value RAVE during the read period.

Considering that the gate potential _Vg actually changes in response to changes in the dummy bit line potential _VDBL , the gate potential _Vg changes in parallel with the dummy bit line potential _VDBL in the read period. , and the ratio of the capacitances C ₃₁ and C ₃₂ of the capacitors 31 and 32 is adjusted based on the above equation (8) so that the rate of change of the gate potential _{Vg is less than or equal to the rate of change of the dummy bit line potential VDBL .} The fact that the gate potential _Vg changes in response to the change in the dummy bit line potential _VDBL means that the gate potential _{Vg starts to change after a short response time elapses from the change in the dummy bit line potential VDBL .} do. Further, the fact that the gate potential _Vg changes in the same direction as the dummy bit line potential _VDBL in this example means that the gate potential _Vg decreases substantially simultaneously with the decrease of the dummy bit line potential _VDBL . means. Further, maintaining "V _g - V _s ≥ V _t " (preferably "(V _g - V _s ) ≥ {(V _DBL - V _s )+V _t } ≥ V _t ") during the readout period, and In order to prevent the equivalent resistance Ron of the reference transistor 27 from greatly deviating from the intermediate resistance value R _AVE at the completion time, "(V _g −V _s )≧V _t " is set. For this purpose, the ratio of the capacitances C ₃₁ and C ₃₂ of the capacitors 31 and 32 is adjusted based on the above equation (8), and the gate width and length of the reference transistor 27 and the initial gate potential V _R1 are appropriately determined.

In order to satisfy the relationship “(V _g −V _s )≧V _t ” at the read completion time with a potential margin, the gate potential V _g is set slightly later than the timing at which the dummy bit line potential V _{DBL stops} changing. It is better to adjust it to the extent that it does not change. For this purpose, for example, the capacitor 31 of the feedback section 30 may be replaced with a circuit in which a capacitor and a resistor r are connected in series. As a result, a gate potential _Vg is obtained which changes with a delay of a predetermined time constant τ with respect to a change in the dummy bit line potential _VDBL . The magnitude of the time constant τ can be adjusted by "r".

Next, data reading with the above configuration will be described. In data reading, a precharge operation is first performed. In the precharge operation, the transistors 37a and 37b of the potential limiting circuit 37 are first applied with the gate voltage Vgn. After that, the precharge signal /PRC is activated to turn on the transistors PR1 and PR2, and the switch element 33 of the reference cell 14 is turned on.

When the transistors PR1 and PR2 are turned on, the power supply potential VDD is applied to the bit line BL and the dummy bit line DBL through the transistors 37a and 37b, respectively, to precharge the bit line BL and the dummy bit line DBL. As a result, the bit line potential _{V_BL} and the dummy bit line potential _{V_DBL} rise and become constant at the initial bit line potential _{V_B0} .

On the other hand, when the switch element 33 is turned on, the capacitors 31 and 32 are charged, and the gate potential _{Vg of the reference transistor 27 becomes the initial gate potential VR1 .} At this time, the capacitor 31 has one end at the initial bit line potential _VB0 and the other end at the initial gate potential _VR1 .

In the precharge operation, sense signal /SE is inactivated (H level). Therefore, the transistors 49a and 49b are turned on, the output nodes n1 and n2 are set to L level, and the sense amplifier 38 is initialized. Therefore, the output nodes n1 and n2 are at the same potential.

From the time when the precharge signal /PRC is activated, the bit line potential _VBL and the dummy bit line potential _VDBL become the initial bit line potential _VB0 , and the gate potential _Vg becomes the initial gate potential _VR1 as described above. After the elapse of the time required for this, the precharge signal /PRC is deactivated (H level) to turn off the transistors PR1 and PR2, and the switch element 33 is turned off. Also, the application of the gate voltage Vgn to the potential limiting circuit 37 is stopped. This completes the precharge operation.

After the precharge operation is finished, the word line WL and the dummy word line DWL are activated at the same time, and the read operation starts in the read period. By simultaneously activating the word line WL and the dummy word line DWL, the select transistor 18 of the memory cell 12 and the select transistor 28 of the reference cell 14 are turned on at the same time.

When the selection transistor 18 is turned on, the charge of the bit line _BL charged by the precharge operation is discharged through the MTJ element 17 and the selection transistor 18 (discharge current flows), and the bit line potential VBL becomes the initial bit line potential. Gradually decreases from V _B0 . Since the discharge speed of the bit line BL at this time is determined by the time constant that depends on the constant resistance value of the MTJ element 17, it corresponds to the data stored in the memory cell 12. FIG.

Also, when the selection transistor 28 of the reference cell 14 is turned on, the charge of the dummy bit line DBL charged by the precharge operation is discharged via the reference transistor 27 and the selection transistor 28 (discharge current flows). . The discharge speed of the dummy bit line DBL at this time is determined by the equivalent resistance Ron of the reference transistor 27 . As shown in FIG. 3, when the dummy word line DWL is activated, its dummy bit line potential _VDBL gradually decreases from the initial bit line potential _VB0 . As the dummy bit line potential _VDBL drops, the source potential _Vs of the reference transistor 27 drops. On the other hand, the decrease in the dummy bit line potential V _DBL is fed back to the gate of the reference transistor 27 through the capacitor 31 of the feedback section 30 . As a result, the gate potential _Vg of the reference transistor 27 drops from the initial gate potential _VR1 as the dummy bit line potential _VDBL drops. Therefore, the relationship between the gate-source voltage (=V _g −V _s ) and the drain-source voltage (=V _d −V _s ) of the reference transistor 27 does not change significantly. That is, since the gate-source voltage of the reference transistor 27 does not become too high or too low with respect to the drain-source voltage (=V _d −V _s ), the equivalent resistance of the reference transistor 27 during the read period is Ron is stably maintained at the intermediate resistance value _RAVE .

After the word line WL and the dummy word line DWL are activated, the sense signal /SE is activated when a predetermined delay time elapses and the sensing possible period is reached. This turns on the transistor 41 and turns off the transistors 49a and 49b. By turning off the transistors 49a and 49b, the potentials of the output nodes n1 and n2, which have been assumed to have the same potential, are allowed to change. Also, when the transistor 41 is turned on, the potential difference between the bit line potential _{VBL and the dummy bit line potential VDBL is} propagated through the transistors 42 and 43 as the potential difference between the output nodes n1 and n2. In this example, the level of the bit line potential _VBL with respect to the dummy bit line potential _VDBL is the level of the potential of the output node n2 with respect to the potential of the output node n1, resulting in a potential difference between the output nodes n1 and n2. When a minute potential difference occurs between the output node n1 and the output node n2, one of the potentials of the output nodes n1 and n2 becomes H level (VDD) due to the mutual positive feedback action of the inverter INV1 and the inverter INV2. , is amplified and latched until the other becomes L level (0V).

For example, when the memory cell 12 stores data “1”, the MTJ element 17 is in a high resistance state and has a resistance value higher than the equivalent resistance Ron of the reference transistor 27 of the reference cell 14 . Therefore, the discharge speed of the bit line potential _{V_BL} is slower than the discharge speed of the dummy bit line potential _{V_DBL} , and the bit line potential _{V_BL} is higher than the dummy bit line potential _{V_DBL} . As a result, the potential of the output node n2 becomes higher than that of the output node n1, the output node n1 becomes L level, and the output node n2 becomes H level. As a result, an L level output signal /D from the output node n1 and an H level output signal D from the output node n2 are output, and data "1" is obtained.

Also, when the memory cell 12 stores data “0”, the MTJ element 17 is in a low resistance state and has a resistance value lower than the equivalent resistance Ron of the reference transistor 27 of the reference cell 14 . Therefore, the discharge speed of the bit line potential _{V_BL} is faster than the discharge speed of the dummy bit line potential _{V_DBL} , and the bit line potential _{V_BL} is lower than the dummy bit line potential _{V_DBL} . As a result, the potential of the output node n1 becomes higher than that of the output node n2, the output node n1 becomes H level, and the output node n2 becomes L level. As a result, an H level output signal /D from the output node n1 and an L level output signal D from the output node n2 are output, and data "0" is obtained.

As described above, the precharge operation and the read operation are sequentially performed, data is read from the memory cell 12, and the output signals D and /D corresponding to the data stored in the memory cell 12 are output. be done.

By the way, in a configuration in which the feedback unit 30 is not provided in the reference cell 14 and a constant potential is applied to the gate of the reference transistor 27 during the read period (this configuration is hereinafter referred to as a comparative configuration), the dummy bit line DBL is discharged. advances, the relationship between the gate-source voltage (=V _g −V _s ) and the drain-source voltage (=V _d −V _s ) of the reference transistor 27 changes significantly. Therefore, the equivalent resistance Ron cannot be kept constant during the read period. In this comparative configuration, for example, when the equivalent resistance _Ron is adjusted to have an intermediate resistance value RAVE at a certain time during discharging of the dummy bit line _DBL , the equivalent resistance Ron is equal to At the end of discharge, the equivalent resistance _{Ron becomes too low with respect to the intermediate resistance value RAVE ,} and desired characteristics cannot be obtained. As a result, during discharging of the dummy bit line DBL, the dummy bit line potential _{V_DBL} is effective between each of the bit line potentials _{V_BL} showing changes corresponding to the MTJ element 17 in the low resistance state and the high resistance state. The senseable period with a large difference becomes extremely short, and an operating margin cannot be secured.

On the other hand, in the read circuit 20 of this example, the capacitor 31 of the feedback section 30 provided in the reference cell 14 as described above causes the gate potential V of the reference cell 14 to follow the decrease in the dummy bit line potential _VDBL . _{Since g} is lowered, the relationship between the gate-source voltage (=V _g −V _s ) and the drain-source voltage (=V _d −V _s ) does not change significantly, and the reference transistor in the read period 27 equivalent resistance Ron is stably maintained at the intermediate resistance value R _AVE . As a result, during discharging of the dummy bit line DBL, the dummy bit line potential _{V_DBL} is effective between each of the bit line potentials _{V_BL} showing changes corresponding to the MTJ element 17 in the low resistance state and the high resistance state. The senseable period with a large difference is longer, and there is a sufficient operating margin.

Further, the read circuit 20 in this example is of the precharge type as described above, and detects the potential difference between the precharged bit line BL and the dummy bit line DBL at the time of discharging. This eliminates the need to detect the magnitude of the steadily flowing current, which is advantageous for power saving. For example, the power consumption in data reading in this example can be reduced to about 1/10 of that in pull-up data reading. Moreover, since the reference cell 14 is of a MOS type in which the reference transistor 27 functions as a resistor, the circuit area is smaller than that of a reference cell using an MTJ element.

Further, the feedback unit 30 provides a stable and highly accurate dummy bit line potential _VDBL as a threshold for discriminating _whether the bit line potential _VBL is high or low. It is possible to reduce the difference from the bit line potential _VBL corresponding to "0". This means that the read current (discharge current) flowing through the MTJ element 17 corresponding to data "1" and data "0" can be reduced when the bit line BL is discharged. In the MTJ element 17, the write current that changes the magnetization state is made larger than the read current. If the read current is made smaller, the MTJ element 17 can be scaled so that the write current is also made smaller accordingly. Become. As a result, the power consumption including the write operation of the memory device 10 can be reduced.

FIG. 4 shows changes in the readout period of each bit line potential _{VBL and the dummy bit line potential VDBL when} the memory cell 12 stores data "1" and data "0" in the configuration of the read circuit 20. are shown along with changes in the potentials of the word line WL, the dummy word line DWL, and the precharge signal /PRC. FIG. 5 also shows the result of simulating the change in the readout period of each bit line potential _{VBL and the dummy bit line potential VDBL in} the comparative configuration.

As can be seen from FIG. 4, when the word line WL and the dummy word line DWL are activated and discharge is started, the dummy bit line potential _VDBL is changed to the bit line potential _VBL corresponding to data "1" during the discharge. , and the bit line potential _VBL storing data "0", and the equivalent resistance Ron of the reference cell 14 is maintained substantially at the aforementioned intermediate resistance value _RAVE by the feedback section 30. FIG. The _senseable period t _SE is a period in which the dummy bit line potential V _DBL exceeds 60 mV (=|V BL−V _DBL |) with respect to the bit line potential V _BL of either data “1” or data “0”. , the senseable period t _SE is 1.56 nsec. This senseable period _tSE is approximately 2.7 times as long as the senseable period _tSE of the comparative configuration, which will be described later.

On the other hand, in the comparative configuration, as can be seen from FIG. 5, the dummy bit line potential _{V_DBL} is higher than the bit line potential _{V_BL} corresponding to data “1” immediately after the start of discharge, and then data “1” and “0”. '' and each bit line potential _VBL . As the discharge progresses further, the difference from the bit line potential _VBL corresponding to data "1" increases, but the difference from the bit line potential _VBL corresponding to data "0" decreases, and the discharge approaches the end. becomes lower than the bit line potential _VBL corresponding to data "0". In the comparative configuration showing such a change in the dummy bit line potential _VDBL , the senseable period _tSE that can be set in the same manner as described above is 0.58 nsec, which is extremely short.

Further, as shown in FIGS. 6 and 7, simulation results of potential changes of the output nodes n1 and n2 in the configuration provided with the feedback section 30, the sense signal / _SE is activated during the sensing enable period tSE. As a result, the signal levels of the output nodes n1 and n2 change as described above, and the data can be read out from the memory cell 12 normally. 6 shows the case where data "1" is stored in the memory cell 12, and FIG. 7 shows the case where data "0" is stored.

[Second embodiment]
The configuration of the memory device of the second embodiment is the same as that of the first embodiment, except for the sense circuit section which will be described in detail below. Therefore, in the following description, the same members are denoted by the same reference numerals, detailed description thereof is omitted, and illustration of the circuit configuration other than the sense circuit portion is omitted.

In this example, the sense circuit section 15A comprises a precharge circuit 56, a potential limiting circuit 57, and a sense amplifier 58, as shown in FIG. The precharge circuit 56 is composed of transistors PR1 and PR2, and the potential limiting circuit 57 is composed of NMOS transistors 57a and 57b. The sense amplifier 58 is composed of inverters INV1A and INV2A. The inverter INV1A consists of transistors 61 and 62, and the inverter INV2A consists of transistors 63 and 64. FIG. Transistors 61 and 63 are PMOS transistors and transistors 62 and 64 are NMOS transistors.

In the inverter INV1A, the gates of the transistors 61 and 62 are connected together and this is the input of the inverter INV1A. The transistor 61 has its source connected to the power supply voltage VDD and its drain connected to the drain of the transistor 62 . The source of the transistor 62 is connected to the signal line SBL, and the signal line SBL is connected to the bit line BL through the transistor 57a of the potential limiting circuit 57. FIG. In the inverter INV2A, the gates of the transistors 63 and 64 are connected to each other, and this serves as the input of the inverter INV2A. The transistor 63 has its source connected to the power supply voltage VDD and its drain connected to the drain of the transistor 64 . The source of the transistor 64 is connected to the signal line SDBL, and the signal line SDBL is connected to the dummy bit line DBL through the transistor 57b of the potential limiting circuit 57. FIG. In this example, the signal line SBL and the signal line SDBL serve as inputs to the sense amplifier 58 .

The connection point between the drains of the transistors 61 and 62 is the output node n1, and the connection point between the drains of the transistors 63 and 64 is the output node n2. The output node n1 is connected to the gates of transistors 63 and 64, respectively, and the output node n2 is connected to the gates of transistors 61 and 62, respectively. Sense amplifier 58 outputs complementary output signals D and /D from output nodes n1 and n2. In this example, the signal level of output node n1 is output as output signal D, and the signal level of output node n2 is output as output signal /D.

The sources of the transistors PR1 and PR2 of the precharge circuit 56 are connected to the power supply voltage VDD. The drain of the transistor PR1 is connected to the output node n1, and the drain of the transistor PR2 is connected to the output node n2.

A gate voltage Vgn is applied to the transistors 57a and 57b of the potential limiting circuit 57 from the start of the precharge operation to the end of the read operation. During the precharge operation, these transistors 57a and 57b limit the bit line potential _VBL and the dummy bit line potential _VDBL to prevent read disturb, as in the first embodiment. Further, in the read operation, the transistors 57a and 57b operate as preamplifiers for amplifying the bit line potential _{VBL and the dummy bit line potential VDBL .}

The sense amplifier 58 has a signal line potential V _SBL of the signal line SBL connecting the sources of the transistors 62 and 64 and the drains of the transistors 57 a and 57 b of the potential limiting circuit 57 and a signal line potential V _SDBL of the signal line SDBL. detect the difference between That is, output signals D and /D are output based on the difference between the signal line potential _{V_SBL} obtained by amplifying the bit line potential _{V_BL} and the dummy bit line potential _{V_DBL} by the transistors 57a and 57b and the signal line potential _{V_SDBL} .

In data reading with the above configuration, the gate voltage Vgn is first applied to the transistors 57a and 57b of the potential limiting circuit 57 in the precharge operation. After that, the precharge signal /PRC is activated to turn on the transistors PR1 and PR2. At the same time, the switch element 33 (see FIG. 1) is turned on. When the transistors PR1 and PR2 are turned on, the output nodes n1 and n2 go to the potential VDD, that is, the H level through the transistors PR1 and PR2, and the sense amplifier 58 is initialized. At this time, transistors 61 and 63 are off and transistors 62 and 64 are on.

Also, when the transistors 62 and 64 are turned on, the power supply voltage VDD is applied to the bit line BL via the transistors PR1, 62 and 57a and to the dummy bit line DBL via the transistors PR2, 64 and 57b. As a result, the bit line _BL and the dummy bit line DBL are precharged, and the bit line potential VBL and the dummy bit line potential _{V_DBL} become the initial bit line potential _VB0 . At this time, the signal line potential V _SBL and the signal line potential V _SDBL are equal because they are obtained by amplifying the bit line potential V _BL and the dummy bit line potential V _DBL .

After precharging the bit line BL and the dummy bit line DBL to the initial bit line potential _VB0 , the precharge signal /PRC is deactivated. As a result, the transistors PR1 and PR2 are turned off, and the switch element 33 is turned off. This completes the precharge operation.

After the precharge operation is finished, the word lines WL and the dummy word lines DWL are activated to enter the read period, and the read operation is performed. By activating the word line WL and the dummy word line DWL, discharge of the bit line BL through the MTJ element 17 (see FIG. 1) and discharge of the dummy bit line DBL through the reference transistor 27 (see FIG. 1) are performed. are started respectively, and the bit line potential _{V_BL} and the dummy bit line potential _{V_DBL} are gradually lowered.

When the bit line potential VBL and the dummy bit line potential VDBL drop, the signal line potentials V _SBL and V _SDBL of the signal lines SBL and _SDBL also _drop proportionally due to the amplifying action of the transistors 57a and 57b. Further, when a potential difference occurs between the bit line potential _VBL and the dummy bit line potential _VDBL , an amplified potential difference occurs between the signal line potential V _SBL and the signal line potential V _SDBL . The difference between the signal line potential V _SBL and the signal line potential V _SDBL propagates through the transistors 62 and 64 as the potential difference between the output nodes n1 and n2.

The sense amplifier 58 stands by in an operable state by turning off the transistors PR1 and PR2 at the end of the precharge operation, and starts operating by activating the word line WL and the dummy word line DWL. Thus, when a slight potential difference occurs between the output node n1 and the output node n2 due to the potential difference between the signal line potential V _SBL and the signal line potential V _SDBL , the mutual positive feedback action of the inverters INV1A and INV2A causes: Output nodes n1 and n2 are amplified and latched until one of them becomes H level and the other becomes L level. As a result, output signals D and /D corresponding to the difference in discharge speed between the bit line BL and the dummy bit line DBL, that is, the level of the resistance value of the MTJ element 17 with respect to the equivalent resistance Ron of the reference transistor 27, are output. The data stored in cell 12 can be read.

FIG. 9 shows the signal line potential V SBL of the signal line _SBL and the signal line potential V of the signal line SDBL in the read period when the memory cell 12 (see FIG. 1) stores data “1” and data “0”. The results of simulating changes in _SDBL are shown along with changes in potentials of the word line WL, dummy word line DWL, and precharge signal /PRC. In this simulation, in order to eliminate changes in the signal line potential V _SBL and the signal line potential V _SDBL due to the latching operation of the sense amplifier 58, the sense circuit section 15A is configured with the sense amplifier 58 as shown in FIG. are omitted, and a circuit in which the transistors PR1 and PR2 of the precharge circuit 56 are directly connected to the transistors 57a and 57b of the potential limiting circuit 57 is used.

As can be seen from FIG. 9, the signal line potential V _SDBL is at an intermediate potential between the signal line potential V _SBL corresponding to data "1" and the signal line potential V _SBL storing data "0" during discharging. It can be seen that the equivalent resistance Ron of the reference cell 14 is substantially maintained at the aforementioned intermediate resistance value _RAVE by the feedback section 30 (see FIG. 1). In both cases of data "1" and data "0", the senseable period tSE is 1.7 nsec, which is about 3.0 nsec compared to the comparative configuration (described later) in which the feedback section 30 is not provided in the reference cell 14. was five times. In this example, since the signal line potential V _SBL and the signal line potential V _SDBL obtained by amplifying the bit line potential V _BL and the dummy bit line potential V _DBL are used for detection by the sense amplifier 58, the senseable period tSE is A period in which the difference between the signal line potential V _SBL and the signal line potential V _SDBL exceeds 80 mV.

FIG. 11 shows the result of simulating changes in the signal line potential V SBL of the signal line _SBL and the signal line potential V _SDBL of the signal line SDBL in a comparative configuration in which the reference cell is not provided with the feedback section. Also in this comparative configuration, the sense circuit section 15A is configured without the sense amplifier 58 shown in FIG. there is In the comparative configuration in which no feedback section is provided, the equivalent resistance Ron of the reference cell changes as the read operation progresses, so the sensing enabled period tSE is shortened. For example, if the equivalent resistance Ron of the reference cell at the start of readout is adjusted to the intermediate resistance value _RAVE , the equivalent resistance Ron becomes too low at an early point in the readout operation, resulting in a signal line on the reference side. The potential V _SDBL becomes lower than the signal line potential V _SBL that should be determined as "0", resulting in malfunction. Thus, the sensing enable period tSE in the comparative configuration is shortened to 0.48 nsec, which is significantly shorter than the reference cell 14 (FIG. 9) of this example provided with the feedback section 30. FIG.

Further, when the sense circuit section 15A is used, the precharge signal /PRC, the potentials of the word line WL and the dummy word line DWL, the bit line potential V _BL and the dummy bit line potential V _DBL , the output nodes n1 and n2. Changes in potential are shown in FIGS. FIG. 12 shows the case where data "1" is stored in the memory cell 12, and FIG. 13 shows the case where data "0" is stored. From these potential changes, it can also be seen that the signal levels of the output nodes n1 and n2 change according to the data stored in the memory cell 12, and the data is normally read out from the memory cell 12. FIG. As sense amplifier 58 amplifies the potential difference between output nodes n1 and n2, the difference between bit line potential _{VBL and dummy bit line potential VDBL decreases} . Since the operation is almost completed and it is in a stable state, there is no problem.

[Third embodiment]
The memory device of the third embodiment performs data reading by a pull-up method. The configuration other than the sense circuit section, which will be described in detail below, is the same as that of the first embodiment. Therefore, in the following description, the same members are denoted by the same reference numerals, detailed description thereof is omitted, and illustration of the circuit configuration other than the sense circuit portion is omitted.

In this example, as shown in FIG. 14, the sense circuit section 15B is composed of a pull-up circuit 71, a sense amplifier 72, and a potential limiting circuit 73. FIG. The pull-up circuit 71 is composed of transistors PL1 and PL2 as bit line loads, and the potential limiting circuit 73 is composed of transistors 73a and 73b. Transistors PL1 and PL2 are PMOS transistors, and transistors 73a and 73b are NMOS transistors.

The sources of the transistors PL1 and PL2 are connected to the power supply voltage VDD. Also, the transistors PL1 and PL2 are connected to the bit line BL and the dummy bit line DBL through the potential limiting circuit 73, respectively. That is, the transistor PL1 has its drain connected to the drain of the transistor 73a, and the source of the transistor 73a connected to the bit line BL. The drain of the transistor PL2 is connected to the drain of the transistor 73b, and the source of the transistor 73b is connected to the dummy bit line DBL. The potential limiting circuit 73 has the same function as the potential limiting circuit 57 (see FIG. 8) of the second embodiment.

The sense amplifier 72 is connected between a signal line SBL connecting the transistors PL1 and 73a and a signal line SDBL connecting the transistors PL2 and 73b. The sense amplifier 72 detects the difference between the signal line potential V SBL of the signal line _SBL and the signal line potential V _SDBL of the signal line SDBL. The circuit of the sense amplifier 72 has the same circuit configuration as that shown in FIG. 2, for example, but the polarities of the transistors (PMOS and NMOS) are opposite, and the sense signal SE is activated (H level). The difference is that the operation is started by

In the data read in this example, only read operations are performed. In this read operation, the switch element 33 (see FIG. 1) is first turned on, and the gate voltage Vgn is applied to the transistors 73a and 73b of the potential limiting circuit 73, respectively. In addition, pull-up signal /PLU is activated (L level). The switch element 33 is turned off after a sufficient period of time has elapsed to _{bring the gate potential Vg of the reference transistor 27 (see FIG. 1) to the initial gate potential VR1 .} On the other hand, the gate voltage Vgn and the pull-up signal /PLU are activated prior to the read operation and maintained until the read operation is completed.

Activation of pull-up signal /PLU turns on transistors PR1 and PR2. As a result, the same voltage (<VDD) is applied to the bit line BL and the dummy bit line DBL. After turning on the transistors PR1 and PR2 in this way, the word line WL and the dummy word line DWL are respectively activated. When the predetermined sense delay time _tDSE has elapsed after the activation of the word line WL and the dummy word line DWL, the sense signal SE is activated and the sense amplifier 72 starts operating.

When the select transistors 18 and 28 (see FIG. 1) are turned on by activating the word line WL and the dummy word line DWL, a current flows through the MTJ element 17 (see FIG. 1) and the select transistor 18 to the bit line BL. , and a current flows through the dummy bit line DBL through the reference transistor 27 (see FIG. 1) and the selection transistor 28 . As a result, the bit line _BL becomes the bit line potential VBL corresponding to the resistance value of the MTJ element 17, and the dummy bit line _DBL becomes the dummy bit line potential VDBL corresponding to the equivalent resistance Ron of the reference transistor 27. FIG. The bit line potential _{VBL and the dummy bit line potential VDBL are amplified by the transistors 73a and 73b and appear as the signal line potentials V SBL and V SDBL of the signal} lines SBL and _SDBL . When a potential difference occurs between _VDBL and VDBL, an amplified potential difference occurs between the signal line potential V _SBL and the signal line potential V _SDBL . Then, the signal line potential V _SBL and the signal line potential V _SDBL are detected by the sense amplifier 72 and the output signals D and /D corresponding to the level of the resistance value of the MTJ element 17 are output. Thus, data stored in the memory cell 12 (see FIG. 1) is read.

Note that the constant of the reference transistor 27, the initial gate potential V _R1 , and the like are such that the signal line potential V _SDBL of the signal line SDBL becomes It is adjusted to be an intermediate potential between the signal line potential VSBL of the signal line _SBL when data "1" is read and the signal line potential VSBL of the signal line _SBL when data "0" is read.

FIG. 15 shows the result of simulating changes in the signal line potential V _SBL and the signal line potential V _SDBL when the memory cell 12 stores data “1” and data “0” in the above configuration. It is shown along with changes in the respective potentials of the line WL and the dummy word line DWL. FIG. 16 also shows simulation results of changes in the signal line potential V _SBL and the signal line potential V _SDBL in the case of the configuration without the feedback section.

As can be seen from the graph of FIG. 15, in the configuration provided with the feedback section 30 (see FIG. 1), compared with the configuration without the feedback section 30, the activation of the word line WL and the dummy word line DWL occurs earlier than the signal line potential V _SBL . , and the signal line potential V _SDBL . When the dummy word line DWL rises (activates), the dummy bit line potential _VDBL also changes so as to follow the change in its potential _. This is because the feedback section 30 maintains the equivalent resistance Ron of the reference transistor 27 substantially at the intermediate resistance value _RAVE .

_Simulation results of the configuration provided with the feedback section 30 shown in FIG. The sense delay time t _DSE at was 0.34 ns. On the other hand, the sense delay time t _DSE in the simulation result of the configuration without the feedback unit 30 shown in FIG. The t _DSE is shortened by approximately 40%.

By reducing the sense delay time t _DSE as described above, it is possible to shorten the time during which the current flows through the bit line BL and the dummy bit line DBL for the read operation, thereby saving power. can.

The configuration of the feedback section described in each of the above embodiments is an example, and the present invention is not limited to that configuration. A feedback section 30A shown in FIG. 17 is composed of a capacitor 32, a switch element 33, and a feedback transistor 81 of a PMOS transistor. The feedback transistor 81 has its gate connected to the dummy bit line DBL, its drain grounded, and its source connected to the gate of the reference transistor 27 . The connection between the capacitor 32 and the switch element 33 is the same as in the first embodiment, and the switch element 33 is turned on before the read operation and turned off after setting the gate potential _{Vg of the reference transistor 27 to the initial gate potential VR1 .} be made. In the read period, the feedback transistor 81 lowers the gate potential _Vg of the reference transistor 27 following the lowering of the dummy bit line potential _VDBL , and the equivalent resistance Ron of the reference transistor 27 is kept constant.

The feedback section 30B of FIG. 18 is composed of a capacitor 32, a switch element 33, and MOS diodes 82 and 83 connecting the drain and gate of an NMOS transistor. MOS diodes 82 and 83 are connected in series and connected between dummy bit line DBL and the gate of reference transistor 27 . That is, the source of the MOS diode 82 is connected to the dummy bit line DBL, the gate (drain) of the MOS diode 82 and the source of the MOS diode 83 are connected, and the gate (drain) of the MOS diode 83 is connected to the gate of the reference transistor 27. It is In this example, the connection between the capacitor 32 and the switch element 33 is the same as in the first embodiment, and the switch element 33 is turned on before the read operation to set the gate potential _{Vg of the reference transistor 27 to the initial gate potential VR1 .} turned off after

During the read period, the MOS diodes 82 and 83 of the feedback section 30B lower the gate potential _Vg of the reference transistor 27 following the lowering of the dummy bit line potential _VDBL , and the equivalent resistance Ron of the reference transistor 27 is kept constant. drip. In this configuration, since the N-type MOS diodes 82 and 83 are used to feed back the dummy bit line potential _VDBL to the gate of the reference transistor 27, which is an NMOS of the same polarity, it is less susceptible to process variations.

The feedback section 30C of FIG. 19 comprises a current source 85 and a PMOS transistor 86, which constitute a source follower circuit. The gate of the transistor 86 serving as the input terminal of the source follower circuit is connected to the dummy bit line _DBL to receive the dummy bit line potential V_DBL. The source of the transistor 86 is connected to the current source 85, and the connection point thereof is connected to the gate of the reference transistor 27 as the output terminal of the source follower circuit. The drain of transistor 86 is grounded. The gate potential _Vg of the reference transistor 27 connected to the output terminal changes according to the dummy bit line potential _VDBL , which is the potential of the input terminal of the source follower circuit, and the equivalent resistance Ron of the reference transistor 27 is kept constant. be Since the equivalent resistance Ron can be finely adjusted by adjusting the current source 85, the operation margin of the read operation can be improved by making adjustments corresponding to temperature and voltage changes, for example.

In the examples shown in FIGS. 17, 18 and 19, the capacitor connected between the dummy bit line DBL and the reference transistor 27 is not required, so the number of types of elements can be reduced and the manufacturing can be facilitated.

The arrangement of the memory cells, reference cells, bit lines, dummy bit lines, etc. of the memory device in each of the above-described embodiments is an example, and is not limited thereto. For example, as shown in FIGS. 20 and 21 to be described later, in each column of memory cells, memory cells and reference cells may be connected to a common bit line. In this configuration, each bit line can be a first bit line, a second bit line. That is, when reading data from a memory cell connected to a bit line in an arbitrary column, if a reference cell connected to another bit line is used, the bit line to which the memory cell is connected is the first bit line. A bit line connected to the reference cell is a second bit line. As for the dummy word line, for example, in each row, a plurality of memory cells and one reference cell are connected to a common word line, and bit lines to which the memory cells are connected are sequentially selected and selected. A configuration in which bit lines and dummy bit lines to which reference cells are connected may be combined.

In the memory device 10 shown in FIG. 20, a first memory array 87a and a second memory array 87b are arranged in the vertical direction, and a plurality of sense circuit portions 15 are arranged in the row direction (horizontal direction in the figure) between them. It is The memory cells 12 are arranged in rows and columns in each of the first memory array 87a and the second memory array 87b. In the first memory array 87a, bit lines BLa1, BLa2, . . . are provided for each column, and word lines WLa1, WLa2, . Bit lines BLa1, BLa2, . In the first memory array 87a, the memory cells 12 in the same column are connected to one of the same bit lines BLa1, BLa2, . , WLa2 . . . A plurality of reference cells 14 are arranged side by side in the row direction in the first memory array 87a. In the first memory array 87a, one reference cell 14 is connected to each bit line BLa1, BLa2, . . . , and each reference cell 14 is connected to the same dummy word line DWLa.

Similarly, the second memory array 87b is provided with bit lines BLb1, BLb2, . . . extending in the column direction for each column, and word lines WLb1, WLb2, . is provided. In the second memory array 87b, the memory cells 12 in the same column are connected to one of the same bit lines BLb1, BLb2, . , WLb2 . . . A plurality of reference cells 14 are arranged in the row direction in the second memory array 87b. In the second memory array 87b, one reference cell 14 is connected to each bit line BLb1, BLb2, . The arrangement of the memory cells 12 and the like in the second memory array 87b is line-symmetrical with that in the first memory array 87a with the rows of the sense circuit section 15 as the axis of symmetry.

The sense circuit section 15 is provided for each column, and each sense circuit section 15 is connected to the bit line of the first memory array 87a and the bit line of the second memory array 87b in the same column. For example, the sense circuit section 15 of the first column C1 is connected to the bit line BLa1 of the first memory array 87a and the bit line BLb1 of the second memory array 87b.

In the memory device 10 having such a configuration, when data is read from each memory cell 12 in one row of one of the first memory array 87a and the second memory array 87b, the read target is The word line of the row of memory cells 12 is activated, and the dummy word line connected to the reference cell 14 of the other memory array is activated. For example, when data is read from each memory cell 12 in the second row of the first memory array 87a, the corresponding word line WLa2 is activated and a dummy line connected to the reference cell 14 of the second memory array 87b is activated. Word line DWLb is activated. Each sense circuit section 15 detects the level of the potential of each bit line BLa1, BLa2, . . . based on the potential of each corresponding bit line BLb1, BLb2, .

For example, when data is read from each memory cell 12 in the first row of the second memory array 87b, the corresponding word line WLb1 is activated and the reference cell 14 of the first memory array 87a is connected. Dummy word line DWLa is activated. In this case, each sense circuit section 15 detects the level of the potential of each bit line BLb1, BLb2, . . . based on the potential of each corresponding bit line BLa1, BLa2, .

Therefore, in the memory device 10 shown in FIG. 20, when data is read from the memory cells 12 of the first memory array 87a, the bit lines BLa1, BLa2, . of the second memory array 87b are the second bit lines, and the dummy word line DWLb is the second word line. becomes. Conversely, when reading data from the memory cells 12 of the second memory array 87b, the bit lines BLb1, BLb2, . The bit lines BLa1, BLa2, .

In a memory array 88 of the memory device 10 shown in FIG. 21, memory cells 12 are arranged in rows and columns, and bit lines BL1, BL2, . . . extending in the column direction are provided for each column. Two word lines are provided for each row. One word line in the same row is connected to the memory cells 12 in the odd columns, and the other word line is connected to the memory cells 12 in the even columns. It is For example, in the first row, word line WLa1 is connected to memory cells 12 in odd columns, and word line WLb1 is connected to memory cells 12 in even columns. Similarly, in the second row, word line WLa2 is connected to memory cells 12 in odd columns, and word line WLb2 is connected to memory cells 12 in even columns.

A plurality of reference cells 14 are arranged in the row direction in the memory array 88, and one reference cell 14 is connected to each bit line BL1, BL2, . A row of reference cells 14 is provided with dummy word lines DWLa and DWLb. The odd-numbered reference cells 14 are connected to the dummy word line DWLa, and the even-numbered reference cells 14 are connected to the dummy word line DWLb.

One sense circuit section 15 is provided for one set of bit lines of odd and even columns. That is, when m is an integer of 1 or more, one sense circuit section 15 is provided for a pair of bit lines in the (2m-1)th column and the 2mth column. For example, one sense circuit unit 15 is provided for the bit line BL1 of the first column and the bit line BL2 of the second column, and one sense circuit unit 15 is provided for the bit line BL3 of the third column and the bit line BL4 of the fourth column. Sense circuits 15 are provided.

In this configuration, for example, when reading data from each memory cell 12 in the second row and odd columns (first column, third column, . . . ), the word line WLa2 and the dummy word line DWLb are activated. do. Each sense circuit section 15 detects the level of the potential of each bit line BL1, BL3, . . . based on the potential of each corresponding bit line BL2, BL4, . When data is read from each memory cell 12 in even columns (second column, fourth column, . . . ) of the second row, the word line WLb2 and the dummy word line DWLa are activated and The level of the potential of each bit line BL2, BL4, . . . is detected with reference to the potential of each bit line BL1, BL3, .

In the memory device 10 of FIG. 21, when data is read from the memory cells 12 of the odd columns, the bit lines BL1, BL3, . Any one of the word lines WLa1, WLa2, . . . of the row becomes the first word line. Also, the bit lines BL2, BL4, . On the other hand, when data is read from the memory cells 12 of the even columns, the bit lines BL2, BL4, . . . become the first word line, the bit lines BL1, BL3, . .

Although an example using a two-terminal type MTJ element as a variable resistance memory element has been described above, the variable resistance memory element is not limited to this. For example, a three-terminal type MTJ element, a memory element whose electrical resistance changes due to an electric field-induced colossal resistance change, a ferroelectric random access memory using a ferroelectric capacitor as a memory element, a phase change memory (Phase Change Memory). Random Access Memory) or the like may be used.

10 memory device 12 memory cell 14 reference cell 17 MTJ element 20 readout circuit 27 reference transistors 30, 30A, 30B, 30C feedback sections 31, 32 capacitor 33 switch elements 36, 56 precharge circuit 71 pull-up circuit 81 feedback transistor 82, 83 MOS diodes BL, BLa1, BLa2, BLb1, BLb2, BL1 to BL4 Bit line DBL Dummy bit line V _BL bit line potential V _DBL dummy bit line potential V _R1 Initial gate potential V _SBL , V _SDBL Signal line potential

Claims (18)

In a read circuit of a resistance change memory device including memory cells including resistance change storage elements,
a sense circuit unit for detecting a potential difference between a first bit line connected to the memory cell and a second bit line paired with the first bit line;
a reference cell for generating a reference potential on the second bit line;
The reference cell is
a reference transistor having a drain connected to the second bit line;
a selection transistor connected between the source of the reference transistor and the ground and having a gate connected to a word line;
a feedback unit that feeds back the potential of the second bit line to the gate of the reference transistor, and changes the potential of the gate of the reference transistor in the same direction as the potential of the second bit line changes. A readout circuit for a resistance change memory device, characterized by: The feedback section is turned on prior to a read operation in which the sense circuit section detects a potential difference between the first bit line and the second bit line, and the second bit line and the reference transistor are turned on. and the ground side capacitance component between the gate of the reference transistor and the ground are charged, and the potential of the gate of the reference transistor is set to the initial gate potential. 2. The readout circuit of a resistance change type memory device according to claim 1, further comprising a switching element that turns off. 3. The bit line side capacitor according to claim 2, wherein the bit line side capacitance component includes a bit line side capacitor having one end connected to the second bit line and the other end connected to the gate of the reference transistor. A readout circuit of a resistive memory device. 4. The readout circuit of the resistance change type memory device according to claim 3, wherein the bit line side capacitor is a MOS capacitor. The feedback unit
a feedback transistor having a gate connected to the second bit line, a drain grounded, and a source connected to the gate of the reference transistor;
Prior to the read operation in which the sense circuit unit detects the potential difference between the first bit line and the second bit line, the ground side static electricity between the gate of the reference transistor and the ground is turned on. 2. The readout circuit of the resistance change type memory device according to claim 1, further comprising a switch element that charges a capacitive component and turns off after setting the potential of the gate of the reference transistor to the initial gate potential. The feedback unit
a MOS diode connected between the second bit line and the gate of the reference transistor;
Prior to the read operation in which the sense circuit unit detects the potential difference between the first bit line and the second bit line, the ground side static electricity between the gate of the reference transistor and the ground is turned on. 2. The readout circuit of the resistance change type memory device according to claim 1, further comprising a switch element that charges a capacitive component and turns off after setting the potential of the gate of the reference transistor to the initial gate potential. 7. The resistance change according to any one of claims 2 to 6, wherein the ground-side capacitance component includes a ground-side capacitor having one end connected to the gate of the reference transistor and the other end grounded. memory device readout circuit. 8. The readout circuit of the resistance change type memory device according to claim 7, wherein the ground side capacitor is a MOS capacitor. 2. The resistance change type memory according to claim 1, wherein the feedback section is a source follower circuit having an input end connected to the second bit line and an output end connected to the gate of the reference transistor. Device readout circuitry. The sense circuit unit sets the first bit line and the second bit line to a predetermined potential prior to a read operation for detecting a potential difference between the first bit line and the second bit line. 10. The readout circuit of a resistive memory device according to claim 1, further comprising a precharge circuit for precharging. The sense circuit unit detects the potential difference between the first bit line and the second bit line during a read operation in which the sense circuit unit senses the potential difference between the first bit line and the second bit line. 10. The reading circuit of the resistance change type memory device according to claim 1, further comprising a pull-up circuit that pulls up the . Data stored in the memory cell is read based on a potential difference between a first bit line to which a memory cell including a resistance change storage element is connected and a second bit line to which a reference cell is connected. In the reading method of the resistance change type memory device,
Reference potential generation for generating a reference potential in the second bit line by causing a current from the second bit line to flow through a reference transistor connected to the second bit line when data is read. a step;
During the generation of the reference potential, the potential of the second bit line is changed according to the change of the potential of the second bit line so as to change the potential of the gate of the reference transistor in the same direction as the change. and a feedback step of feeding back to the gate of the reference transistor. Before the feedback step, a predetermined potential is applied to the gate of the reference transistor, and the bit line side capacitance component between the second bit line and the gate of the reference transistor and the voltage of the reference transistor a charging step of charging a ground-side capacitance component between the gate and ground;
The feedback step changes the amount of charge charged in the bit line side capacitance component and the ground side capacitance component due to a change in the potential of the second bit line, thereby changing the reference transistor. 13. The reading method of the resistance change type memory device according to claim 12, wherein the potential of the gate of is changed. a charging step performed before the feedback step of applying a predetermined potential to the gate of the reference transistor to charge a ground-side capacitance component between the gate of the reference transistor and ground;
In the feedback step, the potential of the gate of the reference transistor is changed by changing the amount of charge charged in the ground-side capacitance component by a feedback transistor having a gate to which the potential of the second bit line is input. 13. The readout method of the resistance change type memory device according to claim 12, wherein . a charging step performed before the feedback step of applying a predetermined potential to the gate of the reference transistor to charge a ground-side capacitance component between the gate of the reference transistor and ground;
In the feedback step, a MOS diode connected between the second bit line and the gate of the reference transistor changes the amount of charge charged in the ground-side electrostatic capacitance component, thereby changing the reference transistor. 13. The reading method of the resistance change type memory device according to claim 12, wherein the potential of the gate is changed. 13. The reading method of the resistance change type memory device according to claim 12, wherein said feedback step feeds back the potential of said second bit line to the gate of said reference transistor by a source follower circuit. 17. The method according to claim 12, further comprising a precharge step of precharging the first bit line and the second bit line before the reference potential generating step. read method of the resistance change memory device of. 17. The resistance change according to claim 12, wherein the first bit line and the second bit line are pulled up to a predetermined potential during the reference potential generating step. method of reading a memory device.

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