JP2003109374A - Write-in circuit for magnetic memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress overshoot caused in the current flowing in a write-in line and a bit line at the time of writing-in of data. SOLUTION: A current is supplied by improving current supply capability in a plurality of stages at the time of rise of a pulse type current by a current generating means generating a pulse type current instead of generating a rectangular current pulse as a write-in current and an assist current, and a pulse being an originally prescribed current value (prescribed value) I is generated finally. When a current is supplied in two stages, switch elements 53, 54 provided respectively in constant current sources 51, 52 and at the output side of the constant current sources 51, 52 are used, and the switch element 53 is made conductive before the switch element 54 is done so.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write circuit for a non-volatile memory device, and more particularly to a write circuit suitable for a magnetic memory device having a memory cell using a magnetoresistive element.

[0002]

2. Description of the Related Art In a magnetic material such as a ferromagnetic material, a magnetoresistive effect is known in which the electric resistance changes depending on the direction of magnetization and the presence or absence of magnetization. Resistance ratio (MR ratio; Magneto-Resistance)
Ratio). Giant Magneto-Resistance (GMR) materials and Colossal Magneto-Resista (CMR) materials are used as materials having a large magnetic resistance ratio.
nce) materials, which are generally metals, alloys, complex oxides, and the like. For example, Fe, Ni, Co, Gd,
Tb and their alloys, La _X Sr _1-X MnO ₉ , L
There are materials such as composite oxide such as _{a X Ca 1-X MnO 9} . In general, a ferromagnetic substance has a characteristic that the magnetization generated in the ferromagnetic substance by an externally applied magnetic field remains even after the external magnetic field is removed (this is called remanent magnetization).

Therefore, if a ferromagnetic material is used as the magnetoresistive material and the residual magnetization of the ferromagnetic material is utilized, a non-volatile memory for storing information by selecting an electric resistance value depending on the magnetization direction and the presence / absence of magnetization is constructed. can do. Such a nonvolatile memory is a magnetic memory (MRAM: Magnetic Random Access Memory).
is called.

Most of the MRAMs that have been developed in recent years store information by the residual magnetization of a ferromagnetic material of a giant magnetoresistive material, and can detect a change in electric resistance value caused by a difference in magnetization direction. Therefore, a method of reading the stored information is adopted. In addition, by writing a current in the memory cell by changing the magnetization direction of the ferromagnetic memory cell by a magnetic field induced by applying a current to the write wiring,
Also, the information can be rewritten.

As a memory cell of an MRAM, a tunnel magnetoresistive element (TMR; Tunnel Magneto-) having a structure in which a tunnel insulating film (an electric insulating film having a thickness such that a tunnel current flows) is sandwiched between two ferromagnetic layers. Resistance, or MTJ (Magnetic Tunnel Junction), has a high rate of change in magnetoresistance (MR ratio), and is expected as a device that is most practical. As such a memory cell, one having a structure in which a tunnel insulating film is sandwiched between two in-plane magnetized films has been conventionally studied. However, in the case of a memory cell using an in-plane magnetized film, the MR ratio is reduced and the required write current is increased with the miniaturization of the memory cell, and the operating point (hysteresis indicating the magnetic characteristics of the memory cell is It is known that there are issues that need to be solved, such as movement of loops). On the other hand, in Japanese Unexamined Patent Application Publication No. 11-213650, 2
A structure has been proposed in which a non-magnetic layer that is a tunnel insulating film is sandwiched between a plurality of perpendicularly magnetized films. By using the perpendicular magnetization film, even if the memory cell is miniaturized, a decrease in MR ratio and an increase in write current can be suppressed, and a shift in a hysteresis loop can also be suppressed. You can get cells. One of the two perpendicularly magnetized films is a detection layer whose magnetization direction is always the same, and the other is a memory layer whose magnetization direction is reversed based on the recorded information. The detection layer and the memory layer are formed by using different compositions of magnetic materials to be used. The electric resistance between the detection layer and the memory layer changes depending on whether the magnetization directions of the detection layer and the memory layer are parallel or anti-parallel, and by detecting this, the recorded information can be read. You can In the following description, the magnetization direction of the magnetoresistive element or the reversal of the magnetization direction means
It refers to the magnetization direction of the memory layer or the reversal of the magnetization direction.

FIG. 6 is a circuit diagram showing an example of the configuration of the memory cell array of the MRAM.

One memory cell includes a magnetoresistive element (memory element) 11 represented as a variable resistance, and a transistor 12 having one end connected to the magnetoresistive element 11. The transistor 12 is typically a MOS (Metal-Oxi).
de-Semiconductor) field effect transistor, and the other end is grounded. A plurality of such memory cells are two-dimensionally arranged in a matrix to form a memory cell array. Here, when the arrangement in the horizontal direction in the drawing is called a row and the arrangement in the vertical direction is called a column, in the illustrated arrangement, 3 in the memory cell array are used.
A region of rows × 3 columns is shown. Bit lines BL1 to BL3 extending in the row direction are provided for each row, and word lines WL1 to WL3 extending in the column direction are provided for each column. In each memory cell, one end of the magnetoresistive element 11 is connected to the bit line of the corresponding row, and the gate of the transistor 12 is connected to the word line of the corresponding column.

The broken lines shown in the figure indicate write lines WWL1 to WW for writing data to each memory cell.
L3, and the write line is provided for each column. As will be described later, the magnetoresistive element 11 in the memory cell
At the time of recording data on the write line, a write current is made to flow in a pulsed manner on the write line. Depending on the direction of the pulsed write current on the write line, either binary recording “0” or “1” is magnetic. It is written in the resistance element 11. Therefore, for each of the write lines WWL1 to WWL3, a signal source 21 that generates a pulsed write current,
A write switch 13 that determines the direction in which a write current from the signal source 21 flows on the write line is provided. Power is supplied from the power supply circuit 14 to each signal source 21.

The write switch 13 includes transistors T1 to T4 as switching elements. The transistors T1 and T2 are connected in series with each other, and
It is inserted between the output of the signal source 21 and the ground point so that 2 is on the ground side. Similarly, the transistors T3 and T
4 are connected in series with each other and are inserted between the output of the signal source 21 and the ground point so that the transistor T4 is on the ground side. Each of the write lines WWL1 to WWL3 is configured to be folded back at the other end of the column, and is connected between the interconnection point of the corresponding transistors T1 and T2 and the interconnection point of the transistors T3 and T4. Transistor T1,
When T4 is conductive and the transistors T2 and T3 are off, the write current from the signal source 21 flows counterclockwise in the drawing on the write line, and the transistors T1 and T3 are turned on.
If the transistor 4 is cut off and the transistors T2 and T3 are conductive, the write current flows clockwise in the figure. For this reason,
The write switch 13 allows a write current to flow from the signal source 21 in both directions.

FIG. 7 is a sectional view showing an example of the structure of a memory cell. In the figure, two memory cells arranged in the column direction are shown.

The element isolation region 31 is formed on the semiconductor substrate 30, and the drain region 3 of the transistor 12 is formed.
2 and the source region 33 are provided, and the drain region 32
In the region sandwiched between the source region 33 and the source region 33, the word line 35 (the word lines WL1 to W in FIG. 6) that also serves as the gate electrode of the transistor 12 is provided via the gate insulating film 34.
(Corresponding to L3) is formed. In the illustrated example, the two transistors 12 also serve as the source region 33, and the interlayer insulating films 36, 37 and 38 are provided in this order so as to cover the transistor 12. The interlayer insulating film 38 is formed particularly thin. The source region 33 is connected to the ground line 40 formed on the interlayer insulating film 36 via the plug 39, and the drain region 32 is formed on the interlayer insulating film 38 via the plug 41. 11 is connected to the lower surface. In the illustrated example, the magnetoresistive element 11 is disclosed in JP-A-11-213.
As described in Japanese Patent Laid-Open No. 650, a tunnel insulating film which is a non-magnetic layer is sandwiched between two layers of perpendicularly magnetized films, one of which is a detection layer and the other of which is a memory layer. A write line 42 (corresponding to the write lines WWL1 to WWL3 in FIG. 6) is formed below the interlayer insulating film 38 so as to be engraved in the interlayer insulating film 37. The interlayer insulating film 43 is formed so as to fill the region between the adjacent magnetoresistive elements 11, and the upper surface of the magnetoresistive element 11 is
The bit lines 44 (corresponding to the bit lines BL1 to BL3 in FIG. 6) formed on the interlayer insulating film 43 and extending in the left-right direction in the drawing are connected. Further, an interlayer insulating film 45 which also serves as a protective film is formed so as to cover the interlayer insulating film 43 and the bit line 44.

When writing data to a memory cell in the memory cell array shown in FIG. 6, the write value ("0" or "0" is written to the write line of the column to which the memory cell (selected memory cell) to which the data is to be written belongs. 1 "), a write current of a polarity (direction) corresponding to 1") is applied in a pulsed manner to generate a write magnetic field perpendicular to the film surface of the magnetoresistive element, and an assist current is applied to the bit line of the row to which the memory cell belongs. It is carried out in a pulsed manner to generate an assist magnetic field horizontal to the film surface of the magnetoresistive element, and the sum magnetic field of the write magnetic field and the assist magnetic field is used to write data only to the selected memory cell. The write magnetic field serves as a magnetic field that determines the magnetization direction of the memory layer, and the assist magnetic field serves as a magnetic field that acts to reduce the magnitude of the write magnetic field necessary for reversing the magnetization direction of the memory layer.
The magnitudes of the write current and the assist current are determined so that the magnetization direction reversal does not occur in the magnetoresistive element only with the write magnetic field or the assist magnetic field. As described above, the pulsed write current is generated by the signal source 21, and the polarity of the write current on the write line is determined by the write switch 13.

A signal source 22 for generating a pulsed current as an assist current is provided. In order to pass a pulsed assist current to the bit line in the selected row, one end of each bit line is provided with a transistor 15 as a switch element for connecting the signal source 22 and the bit line, and the other end. Is provided with a transistor 16 as a switch element for grounding the bit line at the other end. The transistors 15 and 16 are typically MOS
It is composed of a field effect transistor. Signal source 22
Is supplied with power from the power supply circuit 14.

In the case of a magnetic memory device having a memory cell array in which memory cells including magnetoresistive elements are arranged in a matrix, two types of currents are required to write information only in the selected memory cell. One of them is for inducing a magnetic field component parallel / anti-parallel to the magnetization direction of the magnetoresistive element, and the polarity of which is inverted according to binary information (“0” or “1”) to be written. Therefore, in this specification, such a current is referred to as a write current. The other current is a current that induces a magnetic field that assists the recording of information by the write current, and is called an assist current. The polarity of the assist current does not need to be inverted depending on the information to be written, or the polarity is inverted, but the direction of the magnetic field induced compared to the write current described above is orthogonal to the magnetization direction of the magnetoresistive element. Is the current. Although not shown here, in some cases, 2
Both types of currents may have opposite polarities depending on the current to be written and also induce magnetic fields in similar directions. In that case, both are write currents. In the illustrated example, the write current flows in the column direction and the assist current flows in the row direction, but the relationship between the row and the column may of course be reversed.

In such a memory cell array, the read circuit 20 is provided at one end of each of the bit lines BL1 to BL3.
Is provided. The read circuit 20 uses the word line WL
The data written in the memory cell of the column selected by 1 to WL3 is read out. Specifically, all the transistors 15 and 16 are turned off, and the transistor 1 of a specific column is set by the word line.
2 is turned on, the resistance value of the magnetoresistive element 11 of the target memory cell is read from the read circuit 20 side, and whether "0" or "1" is recorded is determined based on the result. In this case, instead of measuring the absolute value of the resistance value of the magnetoresistive element 11, for example, a reference cell is provided in the read circuit 20, and the reference cell and the resistance of the magnetoresistive element 11 are compared to determine “0”. "" Or "1" is determined. In the reference cell, a resistance value that is intermediate between the resistance value when the recorded value is “0” and the resistance value when the recorded value is “1” in the magnetoresistive element 11 is set. Then, a predetermined current is caused to flow through both the reference cell and the magnetoresistive element 11, the voltages generated at both ends of the reference cell and the magnetoresistive element 11 at that time are detected, and the voltages of both are compared to obtain the reference cell. It is determined whether the resistance value of 1 is larger or the resistance value of the magnetoresistive element 11 is larger, and the data recorded in the magnetoresistive element 11 is determined.

The signal sources 21 and 22 will now be described.

Recording is surely performed on a selected magnetoresistive element among a plurality of magnetoresistive elements arranged in the row direction and the column direction, and erroneous magnetization reversal is performed on the non-selected magnetoresistive elements. To prevent it from happening
The write current and the assist current must each have a predetermined magnitude (current value) and a predetermined duration. In particular, if the current value is excessively smaller than the specified value, reliable recording is not guaranteed, and conversely, if the current value is excessively large, reversal of magnetization in the unselected magnetoresistive element is caused.

Conventionally, as the signal sources 21 and 22, for example, as shown in FIG. 8A, a constant current source 81 for generating a predetermined current, and a switch element 82 provided at the output of the constant current source 81. Was used. By turning on / off the switch element 82, a rectangular pulse write current or an assist current having a predetermined magnitude and a predetermined duration is generated. In the case of the signal source 21 that generates a write current, the write switch 13
The transistors T1 to T4 therein may also serve as the switch element 82.

However, the above-mentioned conventional signal source 2 is used.
When 1 and 22 are used, the pulse current waveforms of the actual write current and assist current in the memory cell array are affected by the parasitic capacitance in the memory cell array, the resistance component of the write line and the bit line, and the influence of the inductance component. ,
Overshoot occurs as shown in FIG.
According to the study by the present inventors, the current peak value of this overshoot is about 1.5 times the originally specified current value I. In order to reliably perform recording on the selected magnetoresistive element and to prevent erroneous recording on the non-selected magnetoresistive element, an allowable value is set for the peak value of overshoot, and the allowable value is It is about 1.2 times the specified current value (specified value) I. Then, the prescribed value I of 1.
An overshoot having a peak value of 5 times may cause erroneous recording or writing failure in the magnetoresistive element.

[0020]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a write circuit for a magnetic memory device, which can suppress overshoot occurring in a write current and / or an assist current when writing data. .

[0021]

A write circuit of a magnetic memory device according to the present invention is a write circuit in a magnetic memory device having a magnetoresistive element for writing information according to a magnetic field induced by a pulsed current for each memory cell. In the circuit, the current generating means for generating the pulsed current is characterized in that the current supply capability is increased in a plurality of stages when the pulsed current rises.

As described above, in the magnetic memory device, in general, a pulsed current in which a magnetic field component parallel / antiparallel to the magnetization direction of the magnetoresistive element is induced and the polarity is inverted according to binary information to be written. A first signal source for generating a write current and a second signal source for generating an assist current which is a pulsed current for inducing a magnetic field for assisting recording of information in the magnetoresistive element by the write current. Although provided, it is preferable that at least one of the first signal source and the second signal source is configured by current generation means characterized in that the current supply capability is increased in a plurality of steps at the rise of the pulsed current. It is further preferable that both the first signal source and the second signal source are constituted by such current generating means.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Next, preferred embodiments of the present invention will be described with reference to the drawings. First, the basic operating principle of the write circuit of the present invention will be described.

In the present invention, instead of generating a rectangular current pulse as a write current or an assist current, a current generating means for generating a pulsed current is used to increase the current supply capability in multiple stages at the rise of the pulsed current. I will raise it. For example, when the pulsed current rises, the current is supplied in a plurality of stages, and finally a pulse having the originally specified current value (specified value) I is generated. With this configuration, the current value at the initial stage can be made smaller than the specified value I, so that the overshoot can be made smaller than in the case of using the rectangular wave current pulse. Then, when the overshoot is suppressed to some extent, the current value in the second stage is set. Since the current increment in the second stage is naturally smaller than the specified value I, the overshoot in the second stage is smaller than that in the case of using the rectangular wave current pulse. By dividing into a plurality of stages in this way, the current peak value of the overshoot can be made smaller as compared with the case of using the conventional rectangular wave current pulse, and the selected magnetoresistive element can be used as the write circuit of the magnetic memory device. Thus, it is possible to provide a writing circuit capable of surely recording and surely preventing erroneous recording on a non-selected magnetoresistive element.

It depends on how many stages the current value is supplied, but if the number of stages is increased too much, the circuit becomes complicated,
Moreover, the allowable value of overshoot is approximately 1.
Since it is about double, it is preferable to have two stages. Of course, there may be three or more stages.

In the present invention, the pulse current of the write current and / or the assist current is thus supplied in a plurality of stages at the rising time. In order to obtain such a write current and / or an assist current, a circuit that generates such a pulse current may be used as the signal source 21 and / or the signal source 22 in the magnetic memory device shown in FIG. Therefore, in FIG.
(A) is an example of a write circuit based on the present invention, and it is assumed that the signal sources 21 and 22 are supposed to supply current in two stages.
Shows an example of the basic configuration of the circuit that can be used for,
FIG. 1B shows an example of actual pulse current waveforms of a write current and an assist current in the memory cell array when the circuit shown in FIG. 1A is used as a signal source.

The circuit shown in FIG. 1A has a constant current source 51 for supplying a current I1 and a constant current source 52 for supplying a current I2.
A switch element 53 provided at the output of the constant current source 51,
The switch element 54 is provided at the output of the constant current source 52, and the output sides of the switch elements 53 and 54 are commonly connected to the terminal 55. If this circuit is used as the signal source 21 described above, the terminal 55 is connected to the write switch 13
If used as the signal source 22, the terminal 5
5 is connected to the transistor 15 of each bit line. Here, the sum of the current I1 and the current I2 is set to a current value (specified value) I specified as a write current or an assist current. I1 and I2 may or may not be equal to each other. As the switch elements 53 and 55, for example, transistors or the like can be used.

When a current pulse for the write current or the assist current is generated by the circuit shown in FIG. 1A, it is assumed that both switch elements 53 and 54 are in the cutoff state, and the switch element 53 is first brought into the conductive state. After that, the switch element 54 is turned on after a predetermined delay time. In order to terminate the current pulse, the switch elements 53 and 54 are simultaneously turned off. When the switch elements 53 and 54 are operated in this way, as shown in FIG. 1B, first, the current I1 tends to flow from the terminal 55, and an overshoot accompanying it is generated. Assuming that the current peak value of overshoot is 1.5 times the current value when the current starts to flow steadily, I1 ≦ 0.
By setting 8 · I, the current peak value of the overshoot when the current I1 flows is 1.2 · I or less, which falls within the allowable overshoot value. Then, after a lapse of a predetermined delay time for the overshoot to settle to some extent, the switch element 54 becomes conductive,
The current I (= I1 + I2) tries to flow from the terminal 55. The overshoot newly generated at this time corresponds to the current increment I2, and I2 is, for example, 0.4.
・ If it is smaller than about I, the current peak value in overshoot does not exceed 1.2 · I and falls within the allowable overshoot value.

Next, as described above, the rising portion is set to 2
A specific example of a circuit for generating a pulsed write current and / or assist current in stages will be described.

(Circuit example 1) The circuit shown in FIG. 2 is equivalently provided with two constant current sources corresponding to the currents I1 and I2, respectively, and these constant current sources can be independently controlled. It is a thing. That is, the reference current I
One end of a constant current source 61 that supplies _REF is grounded, the other end of the constant current source 61 is connected to the drain and gate of a p-channel MOS field effect transistor 62, and the source of the transistor 62 is connected to a power supply V _cc . . Further, two p-channel MOS field effect transistors 63 and 65 are provided, and the sources of these transistors are both connected to the power supply _Vcc . The gate of the transistor 63 is connected to the source of the transistor 62 by the switching element 64.
It is designed to be connected to the gate. Similarly, the gate of the transistor 65 is connected to its source or the gate of the transistor 62 by the switch element 66. As the switch elements 64 and 66, for example, those composed of transistors can be used.

Next, the operation of the circuit shown in FIG. 2 will be described.
It The constant current source 61 is always the reference current I_{RE F}Keep flowing
Power supply voltage V_ccRegardless of the gate of transistor 62
・ The source-to-source voltage is the drain current of the transistor 62.
Flow I_REFThe voltage is such that Switch element 64
If connected to the gate of transistor 62,
Transistor voltage between gate and source of transistor 62
It is applied to the gate of the star 63. Also here
Transistor 63 has the same characteristics as transistor 62
If so, a current mirror circuit is
The drain current of the transistor 63 is also I_REFBecomes actually
Is the desired current I1 from the drain of transistor 63
The transistor 63 is designed to be obtained. Trang
In the same semiconductor manufacturing process
When they are formed at the same time and the channel lengths of both are the same
If so, the ratio of the channel widths of the transistors 62 and 63 is
Current I _REFAnd I1.
On the other hand, the switch element 64 is the saw of the transistor 63.
This transistor 63 is cut off when connected to
It becomes a state. Similarly, the switch element 66 is a transistor
When connected to the gate of 62, the
The gate-source voltage is the gate-source voltage of the transistor 62.
It becomes equal to the inter-source voltage. Therefore, the drain current is desired
Design the transistor 65 so that the current I2 becomes
As a result, the switch element 66 becomes
When connected to the gate, the drain of the transistor 65
The current I2 is obtained from the in. Where I1 = I2
Alternatively, I1 ≠ I2 may be satisfied. Switch element 66
If connected to the source of transistor 65
The transistor 65 is turned off.

Therefore, when the write current or the assist current is generated by the circuit shown in FIG.
First, the switch element 6 is set to the source side of 3,65.
4 is switched to the gate side of the transistor 62. As a result, the current I1 starts to flow from the drain of the transistor 63. After the elapse of a predetermined delay time, the switch element 6
6 is also switched to the gate side of the transistor 62. As a result, the current I2 starts to flow from the drain of the transistor 65. After a further predetermined time, the switch element 6
4 and 66 are simultaneously switched to the source side of the transistors 63 and 65 to stop the output of the currents I1 and I2. By connecting the drains of the transistors 63 and 65 to each other to provide the output of this circuit, a pulse current to which a current is supplied in two steps at the time of rising can be obtained, and this may be used as a write current or an assist current.

(Circuit example 2) In the circuit shown in FIG. 3, two constant current sources equivalently corresponding to the currents I1 and I2 are provided, and a switch element is provided on the output side of the constant current source. It is a thing. That is, the reference current I
One end of a constant current source 61 that gives _REF is grounded, and the drain and gate of a p-channel MOS field effect transistor 62 are connected to the other end of the constant current source 61, and the p-transistor 62 is connected.
Source is connected to the power supply _Vcc . Further, two p-channel MOS field effect transistors 67 and 69 are provided, the sources of these transistors are both connected to the power supply V _cc , and the gates thereof are connected to the gate of the transistor 62. The drains of the transistors 67 and 69 are
A current is output via the switch elements 68 and 70. As the switch elements 67 and 69, for example, those composed of transistors can be used.

Next, the operation of the circuit shown in FIG. 3 will be described.
It The constant current source 61 is always the reference current I_{RE F}Keep flowing
Therefore, the gate-source voltage of the transistor 62 is
The drain current of the transistor 62 is the current I_REFAs is
Voltage, the gate and source of transistors 67 and 69
The voltage between the gate and source of this transistor 62
It becomes pressure. Therefore, such a gate-source voltage
When applied, the drain currents are I1 and I2, respectively.
Design the transistors 67 and 69 so that
Therefore, the transistors 67 and 69 have currents I1 and I1, respectively.
It will operate as a constant current source of I2. According to
And connect the output sides of the switch elements 68 and 70 to each other.
As the output of this circuit, and as described in connection with FIG.
By operating the switch elements 68 and 70 in the same manner as
Pulse current that is supplied in two steps when rising.
The flow is obtained. This is the write current or assist voltage.
It can be used as a flow. Note that the current pulse is terminated
Occasionally, the switch elements 68 and 70 are turned off at the same time.
do it.

(Circuit example 3) In the circuit shown in FIG. 4, the effective resistance value of the transistor is changed to obtain a pulse current to which the current is supplied in two stages at the time of rising. is there. That is, one end of the constant current source 61 that _{supplies the} reference current I _REF is grounded, and the drain and gate of the p-channel MOS field effect transistor 62 are connected to the other end of the constant current source 61, so that the transistor 62
Source is connected to the power supply _Vcc . Another p-channel MOS field effect transistor 71 is provided, the source of the transistor 71 is connected to the power supply V _cc , and the gate is connected to the gate of the transistor 62. The drain of the transistor 71 is connected to the drain of the n-channel MOS field effect transistor 72, and the source of the transistor 72 serves as the output terminal of this circuit. The switch signal V _SW is input to the gate of the transistor 72.

Next, the operation of the circuit shown in FIG. 4 will be described.
It The constant current source 61 is always the reference current I_{RE F}Keep flowing
Therefore, the gate-source voltage of the transistor 62 is
The drain current of the transistor 62 is the current I_REFAs is
Voltage, which is the gate-source voltage of the transistor 71
Is the gate-source voltage of this transistor 62.
It Therefore, the transistor 71 is
When a source-to-source voltage is applied, its drain current is written.
So that the specified value I of the sink current or assist current
Designed to operate as a constant current source of current I
deep. In this state, the gate of the transistor 72
On the other hand, under normal conditions (when pulse current is not generated)
Write the transistor 72 so that it is in the cutoff state.
Generates pulse current of inrush current or assist current
When applying voltage signals of different levels to the gate,
This causes the drain current of the transistor 72 to rise.
It is supplied in two stages when rising. Such different levels
As the voltage signal of the switch, for example, the switch signal V_SWBut
It Switch signal V_SWAs shown in FIG. 4,
Is 0 potential, the first stage at the rise of pulse current
And the drain current of the transistor 72 is the current I1
And a transistor 7 as a second stage.
2 becomes a substantially perfect conduction state (0Ω state)
Signals with different levels of potential are used. like that
Switch signal V_SWBy using a transistor
From the source of 72, write current or assist current
It can be used as a current, and the current is supplied in two stages at the time of rising.
The pulsed current delivered is obtained.

(Circuit example 4) The circuit shown in FIG. 5 is controlled by voltage signals of different levels as in the circuit shown in FIG. 4 in order to obtain a pulse current in which current is supplied in two steps at the time of rising. Instead of using transistors, two transistors are arranged in parallel. That is, one end of the constant current source 61 that _{supplies the} reference current I _REF is grounded, and the other end of the constant current source 61 is connected to the p-channel MOS.
The drain and gate of the field effect transistor 62 are connected, and the source of the transistor 62 is connected to the power supply _Vcc . Another p-channel MOS field effect transistor 73 is provided, the source of the transistor 73 is connected to the power supply V _cc , and the gate is connected to the gate of the transistor 62. Two n-channel MOS field effect transistors 74 and 75 are provided, and the drains of these transistors 74 and 75 are commonly connected to the drain of the transistor 73. Also, the transistors 74 and 7
The sources of 5 are also commonly connected to serve as the current output of this circuit. The control signal φ1 is input to the gate of the transistor 74, and the control signal φ2 is input to the gate of the transistor 75. The control signals .phi.1 and .phi.2 generate the pulses with different rising timings shown by the controller CNT. Both of the control signals φ1 and φ2 are normally at 0 potential so that the corresponding transistors 74 and 75 are normally cut off.

Next, the operation of the circuit shown in FIG. 5 will be described.
It The constant current source 61 is always the reference current I_{RE F}Keep flowing
Therefore, the gate-source voltage of the transistor 62 is
The drain current of the transistor 62 is the current I_REFAs is
Voltage, which is the gate-source voltage of the transistor 73
Is the gate-source voltage of this transistor 62.
It Therefore, the transistor 73 is
When a source-to-source voltage is applied, its drain current is written.
So that the specified value I of the sink current or assist current
Designed to operate as a constant current source of current I
deep. The write current or assist current pulse
To generate the output current, first set the control signal φ1 to zero.
The drain current of the transistor 74 becomes the current I1.
To change the potential. As a result, transistor 7
Current I1 flows out from the source of 4 and this is
Current output. Next, after the elapse of a predetermined delay time, control
Signal φ2 from 0 potential to drain current of transistor 75
Is changed to a potential that results in a current I2,
The current I2 starts to flow from the source of 75. this
Therefore, the output current of this circuit becomes I (= I1 + I2).
It At the timing of falling pulse current, control signal
Transistor 7 with both φ1 and φ2 set to 0 potential at the same time
4, 75 are transited to the cutoff state. In this way, the calligraphy
Standing that can be used as a sinking current or assist current
A pulse current that can be supplied in two steps when rising is obtained.
To be

(Circuit example 5) In the circuit shown in FIG. 9, a single current mirror circuit is used to generate two kinds of current values so that a pulse current is supplied in two steps. It is the one. That is, one end of a constant current source 61 that supplies a reference current I _REF is grounded, and the other end of the constant current source 61 is connected to the drain and gate of a p-channel MOS field effect transistor 62, and the source of the transistor 62 is a power source. Connected to V _cc . Another p-channel MOS field effect transistor 76 is provided, and the source of the transistor 76 is a resistor 77.
Connected to the power supply V _cc via the gate of the transistor 62
Is connected to the gate. Further, a switch element 78 that short-circuits the resistor 77 and a switch element 79 that connects the gate of the transistor 76 to the power supply _Vcc are provided.

Next, the operation of the circuit shown in FIG. 9 will be described. Under normal conditions, the switch element 78 is in a cutoff state and the switch element 79 is in a conductive state. Therefore, the gate-source voltage of each of the transistors 62 and 76 is 0, and no current flows.
The constant current source 61 always keeps flowing the reference current I _REF , but this reference current flows from the power source V _cc to the constant current source 61 via the switch element 79.

When the write current or the assist current pulse current is generated, the switch element 78 is kept in the cut-off state while the switch element 79 is kept in the cut-off state. Then, the reference current I _REF starts flowing through the transistor 62, and the gate-source voltage of the transistor 62 is such that the drain current of the transistor 62 is the current I _REF . The gate potential of the transistor 76 also becomes the gate-source voltage of the transistor 62, and the drain current starts to flow from the transistor 76.
At this stage, since the resistor 77 is inserted in the source of the transistor 76, the gate-source voltage of the transistor 76 is smaller than the gate-source voltage of the transistor 62 by the voltage drop due to the resistor 77. Get smaller. Next, after a lapse of a predetermined delay time, the switch element 78 is brought into a conducting state so that the resistor 77 is short-circuited. Then, the gate-source voltage of the transistor 76 becomes equal to the gate-source voltage of the transistor 62, and a drain current larger than that when the resistor 77 is inserted flows out from the transistor 76. If the switch element 79 is in the cutoff state, the transistor 62 and the transistor 76 form a current mirror circuit. Therefore, when the resistor 77 is inserted, the drain current of the transistor 76 is I1 and the resistor 77.
By defining the characteristics of the transistor 76 and the resistance value of the resistor 77 so that the drain current when the pulse current is short-circuited becomes the specified value I, the current I1 is generated when the pulse current rises, and the current is calculated when the delay time elapses. Such as I,
A pulsed current is obtained in which the current is supplied in two stages. In order to stop this pulse current, the switch element 79 may be made conductive.

The preferred embodiment of the present invention has been described above. The write circuit of the present invention is equally applicable to a magnetic memory device using a magnetoresistive element using an in-plane magnetized film as a memory element and a magnetic memory device using a magnetoresistive element using a perpendicular magnetized film as a memory element. It is possible.

Further, as a configuration of the memory cell array of the magnetic memory device, in addition to the configuration in which an assist current is passed through the bit line itself as shown in FIG. 6, a configuration in which a line for passing an assist current is provided in parallel with the bit line is also provided. However, the present invention is also effective for the magnetic memory cell having such a configuration.
Further, there is a configuration in which a write current is passed through the bit line or a write line is provided in parallel to the bit line, and an assist current is passed through the word line or a line for passing an assist current is provided parallel to the word line. The present invention is effective for magnetic memory devices having various configurations. It is generally practiced that the write line for passing the write current is a folded wiring as shown in FIG. 6, and in such a structure, n is an integer of 1 or more and 2n-1. There is a configuration in which the latter half of the write line in the second column and the first half of the write line in the 2nth column are common, but the present invention is also effective for a magnetic memory device having such a configuration. In short, the write circuit of the magnetic memory device of the present invention is a magnetic memory device having a memory cell including a magnetoresistive element, and a pulse for inducing a magnetic field applied to the magnetoresistive element to record information in the magnetoresistive element. It is applied to all circuits that generate electric current.

[0044]

As described above, according to the present invention, instead of generating the rectangular current pulse as the write current or the assist current, the current generating means for generating the pulse current is used at the rising time of the pulse current. By increasing the current supply capacity in multiple stages to supply a pulsed current and finally generating a pulse with the originally specified current value, the overcurrent that occurs in the write current or assist current during data writing There is an effect that it is possible to suppress the chute and prevent erroneous recording and defective writing in the magnetoresistive element.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing a principle configuration of a write circuit according to an embodiment of the present invention, and FIG. 1B is a memory cell array when the circuit shown in FIG. 1A is used as a signal source. 6 is a waveform diagram showing an example of an actual pulse current waveform in FIG.

FIG. 2 is a circuit diagram showing a circuit configuration of circuit example 1;

FIG. 3 is a circuit diagram showing a circuit configuration of circuit example 2;

FIG. 4 is a circuit diagram showing a circuit configuration of circuit example 3;

FIG. 5 is a circuit diagram showing a circuit configuration of circuit example 4;

FIG. 6 is a circuit diagram showing an example of a configuration of a memory cell array of MRAM.

FIG. 7 is a cross-sectional view showing an example of the configuration of a memory cell.

FIG. 8A is a circuit diagram conceptually showing the configuration of a signal source in a write circuit of a conventional magnetic memory device,
(B) is a waveform diagram showing an example of a pulse current waveform which actually flows in the memory cell array at the time of writing when the signal source as shown in (a) is used.

FIG. 9 is a circuit diagram showing a circuit configuration of Circuit Example 5;

[Explanation of symbols]

11 Magnetoresistive Element 12, 15, 16 Switch Element 13 Write Switch 14 Power Supply Circuit 20 Read Circuit 21, 22 Signal Source 30 Semiconductor Substrate 31 Element Isolation Region 32 Drain Region 33 Source Region 34 Gate Insulating Film 35, WL1 to WL3 Word Line 36 ˜38,43,45 Interlayer insulating film 39,41 Plug 40 Ground line 42, WWL1 to WWL3 Write line 44, BL1 to BL3 bit line 50 Reference cells 51, 52, 61, 81 Constant current sources 53, 54, 64, 66 , 68, 70, 78, 79, 8
2 switch element 55 terminals 62, 63, 65, 67, 69, 71 to 75, 76
Transistor 77 Resistance T1 to T4 Transistor

Claims (13)

[Claims] 1. In a write circuit in a magnetic memory device having, for each memory cell, a magnetoresistive element in which information is written in accordance with a magnetic field induced by a pulsed current, the current generation means for generating the pulsed current A write circuit for a magnetic memory device, wherein the current supply capability is increased in a plurality of steps at the rise of the pulsed current. 2. A write circuit in a magnetic memory device having, for each memory cell, a magnetoresistive element in which information is written in accordance with a magnetic field induced by a pulsed current, in a direction parallel / antiparallel to a magnetization direction of the magnetoresistive element. A first signal source for inducing a strong magnetic field component and generating a write current which is a pulsed current whose polarity is inverted according to binary information to be written, and recording of information in the magnetoresistive element by the write current. A second signal source that generates an assist current that is a pulsed current that induces a magnetic field that assists the pulsed current from at least one of the first signal source and the second signal source. The current generating means for generating a current is
A write circuit for a magnetic memory device, characterized in that the current supply capability is increased in a plurality of steps when the pulsed current rises. 3. The write circuit of the magnetic memory device according to claim 2, wherein both the first signal source and the second signal source have the current generating means. 4. The magnetic memory device has a memory cell array in which a plurality of the memory cells are arranged in a matrix, and the write current is applied to the memory cell in one of a row direction and a column direction of the memory cell array. 4. The write circuit of the magnetic memory device according to claim 2, wherein the assist current is made to flow in the cell array, and the assist current is made to flow in the memory cell array in the other direction of the row direction and the column direction of the memory cell array. 5. The write circuit of the magnetic memory device according to claim 1, wherein the pulsed current is supplied in two stages according to the current supply capacity. 6. The current generating means comprises a first constant current source, a second constant current source, a first switch element for controlling the operation of the first constant current source, and the second constant current source. A second switch element for controlling the operation of the constant current source.
A writing circuit of the magnetic memory device according to 1. 7. The current generating means includes a first constant current source, a second constant current source, a first switch element provided on the output side of the first constant current source, and the first constant current source. The write circuit of the magnetic memory device according to claim 5, further comprising a second switch element provided on the output side of the second constant current source. 8. The current generating means has a current source and a field effect transistor provided on the output side of the current source, and voltage signals of different levels are applied to the gate of the field effect transistor. The write circuit of the magnetic memory device according to claim 5. 9. The current generating means includes a current source and first and second field effect transistors provided in parallel with each other on the output side of the current source, and voltage signals having different rising timings. Is applied to the gates of the first and second field effect transistors, respectively.
A writing circuit of the magnetic memory device according to 1. 10. The current generation means includes a current mirror circuit including a first transistor whose source is connected to a power source, a resistor, and a second transistor whose source is connected to the power source through the resistor, and The write circuit of the magnetic memory device according to claim 5, further comprising: a first switch element that short-circuits both ends of the resistor; and a second switch element that controls operation / non-operation of the current mirror circuit. 11. The magnetoresistive element comprises a non-magnetic layer sandwiched between a detection layer made of a ferromagnetic material and a memory layer made of a ferromagnetic material, and the magnetoresistive element is formed depending on a direction of magnetization in the memory layer. The binary information is recorded, and the electric resistance value is changed according to the recorded information.
The write circuit of the magnetic memory device according to claim 1. 12. The write circuit of the magnetic memory device according to claim 11, wherein the non-magnetic layer is a tunnel insulating film. 13. The write circuit of the magnetic memory device according to claim 11, wherein the detection layer and the memory layer are perpendicular magnetization films.