JP2017112351A - Magnetic memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic memory capable of achieving reduction in energy consumption.SOLUTION: A magnetic memory according to an embodiment comprises: a conductive layer having a first terminal and a second terminal; a plurality of magnetoresistive elements arranged on the conductive layer between the first terminal and the second terminal so as to be separated from each other, each magnetoresistive element having a reference layer, a storing layer arranged between the reference layer and the conductive layer, and a non-magnetic layer arranged between the storing layer and the reference layer; and a circuit that applies a first potential to the reference layers of the plurality of magnetoresistive elements and applies a first writing current between the first terminal and the second terminal, and that applies a second potential to a reference layer of a magnetoresistive element to which data is to be written, of the plurality of magnetoresistive elements and applies a second writing current reverse to the first writing current between the first terminal and the second terminal.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a magnetic memory.

  Existing memory is classified into volatile (SRAM (Dynamic Random Access Memory), DRAM (Dynamic Random Access Memory)) working memory and non-volatile (NAND flash memory, HDD (Hard Disk Drive)) storage. The However, these volatile memories consume large energy due to leakage current in SRAM and refresh current in DRAM.

  In order to solve this problem, various nonvolatile memories have been studied as working memory memories replacing SRAM and DRAM.

  However, the working memory has a higher frequency during operation (Active) than the frequency during standby (Standby). For this reason, a large write charge (Qw) is required during operation, and the write energy increases. As a result, the energy saved by the non-volatility during standby is used up during operation, and it is difficult to reduce the energy consumption in total. This is called a historical dilemma of nonvolatile memory, and has been an unsolved problem as a product up to now.

  Slowly, the lowest level cache memory (LLC (Last Level Cache)) with relatively low frequency of operation using STT (Spin Transfer Torque) -MRAM (Magnetic Random Access Memory) in simulations using laboratory-level best data. ), When STT-MRAM is used, energy consumption can be reduced.

  When the STT-MRAM is used as a cache memory above the LLC, the operation frequency is remarkably increased. Therefore, it is a fact that a large amount of energy is consumed, and the reduction of the energy consumption described above cannot be solved.

JP 2014-45196 A

Digest of 2015 Symposium on VLSI Technology H. Yoda, et al., IEDM Tech. Dig., 2012 pp. 259.

  The present embodiment provides a magnetic memory capable of realizing a reduction in energy consumption.

  The magnetic memory according to the present embodiment includes a conductive layer having a first terminal and a second terminal, and a plurality of magnetoresistive elements disposed apart from each other in the conductive layer between the first terminal and the second terminal. Each magnetoresistive element includes a reference layer, a storage layer disposed between the reference layer and the conductive layer, and a nonmagnetic layer disposed between the storage layer and the reference layer. , And applying a first potential to the reference layer of the plurality of magnetoresistive elements and passing a first write current between the first terminal and the second terminal, A circuit that applies a second potential to the reference layer of a magnetoresistive element to which data is to be written and flows a second write current in a direction opposite to the first write current between the first terminal and the second terminal. And.

1 is a perspective view showing a memory cell of a magnetic memory according to a first embodiment. FIG. 3 is a view for explaining a writing method in the memory cell of the magnetic memory according to the first embodiment. FIG. 3 is a view for explaining a writing method in the memory cell of the magnetic memory according to the first embodiment. 1 is a circuit diagram showing a magnetic memory according to a first embodiment. The figure which shows an example of the equivalent circuit of the magnetic memory by 1st Embodiment. A circuit diagram showing a magnetic memory by a 2nd embodiment. A circuit diagram showing a magnetic memory by a 3rd embodiment. A circuit diagram showing a magnetic memory by a 4th embodiment. A circuit diagram showing a magnetic memory by a 5th embodiment. The figure which shows the writing method of the magnetic memory by 6th Embodiment. The figure which shows the result calculated | required by the simulation which shows the relationship between the voltage applied to the reference layer of an MTJ element, and the threshold current of an MTJ element. The figure which shows the hysteresis characteristic with respect to the electric current of resistance at the time of applying a positive voltage to the reference layer of an MTJ element. The figure which shows the hysteresis characteristic with respect to the electric current of resistance when not applying a voltage to the reference layer of an MTJ element. The figure which shows the hysteresis characteristic with respect to the electric current of resistance at the time of applying a negative voltage to the reference layer of an MTJ element. The figure which shows the result of having calculated | required the relationship between the voltage applied to the MTJ element, and the electric current value which was sent through the conductive layer and the magnetization reversal was observed. Sectional drawing which shows the magnetic memory by the 1st modification of 1st Embodiment. The top view which shows the magnetic memory by the 1st modification of 1st Embodiment. Sectional drawing which shows the magnetic memory by the 1st modification of 1st Embodiment. Sectional drawing which shows the magnetic memory by the 2nd modification of 1st Embodiment. Sectional drawing which shows the magnetic memory by the 2nd modification of 1st Embodiment. The figure which shows the relationship between the interface magnetic anisotropy (Ks) generate | occur | produced in the interface of a memory | storage layer and a tunnel barrier, and reversal current value _Ic0 . Sectional drawing which shows the magnetic memory by 1st Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 1st Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 1st Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 1st Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 1st Example. Sectional drawing which shows the magnetic memory of 1st Example. Sectional drawing which shows the magnetic memory of 2nd Example. Sectional drawing which shows the magnetic memory of 3rd Example. Sectional drawing which shows the magnetic memory of 4th Example. The top view which shows the memory element of the magnetic memory of 4th Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 4th Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 4th Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 4th Example. Sectional drawing which shows the manufacturing method of the magnetic memory of 4th Example. The top view which shows the magnetic memory of 5th Example. The top view which shows the memory element of the magnetic memory of 5th Example. Sectional drawing which shows the magnetic memory of 6th Example. Sectional drawing which shows the magnetic memory of 6th Example. Sectional drawing which shows the magnetic memory of 6th Example. Sectional drawing which shows the magnetic memory of 7th Example. The top view which shows the magnetic memory of 7th Example. Sectional drawing which shows the magnetic memory of 8th Example. A circuit diagram showing a magnetic memory of a 7th embodiment.

  Embodiments will be described below with reference to the drawings.

(First embodiment)
A magnetic memory according to the first embodiment will be described with reference to FIGS. The magnetic memory of this embodiment has at least one memory cell, and the configuration of this memory cell is shown in FIG. The memory cell 10 includes a conductive layer 12, a plurality of (for example, eight) magnetoresistive elements 20 _{1 to} 20 ₈ provided on one surface of the conductive layer 12, and the magnetoresistive elements 20 _i. The transistor 25 _i provided corresponding to (i = 1,..., 8), the transistors 31 and 32 that cause current to flow through the conductive layer 10, and the control circuits 110 and 120 are provided.

For example, a metal such as Ta, W, or Pt is used for the conductive layer 12. A write current _Iw flows in the conductive layer 12. The direction of the current flowing through the conductive layer 12 is controlled by the control circuit 110. At this time, for example, electrons 13 a having an up spin and electrons 13 b having a down spin flow in the conductive layer 12. The direction of spin of the electrons 13a and 13b is indicated by arrows.

Each magnetoresistive element 20 _i (i = 1,..., 8) includes a storage layer 21 provided on the conductive layer 12, a nonmagnetic layer 22 provided on the storage layer 12, and a nonmagnetic layer 22. And a reference layer 23 provided thereon. Each magnetoresistive element 20 _i (i = 1,..., 8) may be an MTJ (Magnetic Tunnel Junction) element in which the nonmagnetic layer 22 is an insulating layer, or the nonmagnetic layer 22 is a nonmagnetic metal. The layer may be a GMR (Giant Magneto-Resistive) element. The magnetoresistive element is an MTJ element, and the magnetization directions of the storage layer 21 and the reference layer 23 are parallel to the film surface, that is, the magnetization direction is a direction perpendicular to the stacking direction of the stacked structure. In the case of an element, a CoFeB layer, for example, is used as the storage layer 21, and an MgO layer, for example, is used as the nonmagnetic layer 22. For example, the reference layer includes a CoFeB layer, a Ru layer provided on the CoFeB layer, and a CoFe layer provided on the Ru layer. The CoFeB layer and the CoFe layer are antiferromagnetic via the Ru layer. A synthetic antiferromagnetic laminate structure is used. Note that, in the case of an in-plane magnetization type MTJ element, an antiferromagnetic layer made of, for example, IrMn is provided on the reference layer 23 in order to fix the magnetization of the reference layer 23. In FIG. 1, the magneto-resistive element 20 ₁ to 20 ₈ are disposed above the conductive layer 12 may be disposed below. The magnetoresistive elements 20 _{1 to} 20 ₈ are memory elements.

The MTJ element is patterned in a rectangular shape, and the major axis direction of the magnetization of the storage layer and the reference layer is a stable direction due to the shape magnetic anisotropy. For example, a stable magnetization direction is indicated by an arrow in FIG. This stability is called uniaxial magnetic anisotropy (in the long axis direction). Uniaxial magnetic anisotropy depends on the rectangular aspect ratio, the thickness of the storage layer, and the magnetization of the magnetic layer, and a write current threshold I _co described later is proportional to the uniaxial magnetic anisotropy. Each magnetoresistive element 20 _i (i = 1,..., 8) is a 1-bit storage element, and the memory cell 10 is, for example, a 1-byte cell in which 1 byte is 8 bits. A dummy magnetoresistive element that is not used as a memory element may be disposed in the memory cell 10.

Each transistor 25 _i (i = 1,..., 8) is electrically connected to the reference layer 23 of the magnetoresistive element 20 _i corresponding to one of the source and the drain (hereinafter also referred to as a first terminal), The other of the source and the drain (hereinafter also referred to as a second terminal) is connected to a selection line (not shown) for selecting a memory cell, and the gate (hereinafter also referred to as a control terminal) selects the corresponding magnetoresistive element 20 _i . Connected to a selection line (not shown). That is, each transistor 25 _i (i = 1,..., 8) is also referred to as a bit selection transistor that selects the corresponding magnetoresistive element 20 _i . Each magnetoresistive element 20 _i (i = 1,..., 8) has a first terminal and a second terminal, the first terminal is connected to the conductive layer 12, and the second terminal corresponds to the bit selection transistor. 25 _i connected to the first terminal. Each of the bit selection transistors 25 _{1 to} 25 ₈ has a gate (hereinafter also referred to as a control terminal) and a second terminal connected to the control circuit 120 and is controlled to be turned on and off by the control circuit 120, and the corresponding magnetoresistive element The potential applied to the reference layers 20 _{1 to} 20 ₈ is controlled.

The transistor 31 has one of a source and a drain (hereinafter also referred to as a first terminal) connected to one terminal 12a of the two terminals 12a and 12b of the conductive layer 12, and the other of the source and the drain (hereinafter referred to as a second terminal). A terminal (also referred to as a terminal) is connected to a power source or a current source, and a gate (hereinafter also referred to as a control terminal) receives a signal for selecting the memory cell 10. The transistor 32 has one of a source and a drain (hereinafter also referred to as a first terminal) connected to the other terminal 12b of the two terminals 12a and 12b of the conductive layer 12, and the other of the source and the drain (hereinafter referred to as a second terminal). A terminal (also referred to as a terminal) is connected to a power source or a current source, and a gate (hereinafter also referred to as a control terminal) receives a signal for selecting the memory cell 10. By passing a write current between these transistors 31 and 32 through the conductive layer 12, writing is performed in the memory layer 21 of each magnetoresistive element 20 _i (i = 1,..., 8) as will be described later. It can be performed. These transistors 31 and 32 are also called byte select transistors. Each of these byte selection transistors 31 and 32 has a gate connected to the control circuit 110 and is controlled to be turned on and off. The direction of the current flowing through the conductive layer 12 is also controlled by the control circuit 110. Note that the transistor 32 may be omitted, and the second terminal 12b of the conductive layer 12 may be grounded.

In the following description, it is assumed that each magnetoresistive element 20 _i (i = 1,..., 8) is an MTJ element. The nonmagnetic layer 22 of each MTJ element, for example, the MgO layer, is set to be sufficiently thick (for example, about 2 nm), and the tunnel current flowing through the nonmagnetic layer 22 is set to be 1 μA or less. . Therefore, when the bit selection transistor 25 _i (i = 1,..., 8) is turned on by the control circuit 120, a voltage of about 0.5 V can be applied to the memory layer 21.

Perpendicular magnetic anisotropy is induced in the storage layer of the MTJ element to which a voltage is applied, and the magnetization has a perpendicular component. As a result, the magnetization stability (uniaxial magnetic anisotropy) is weakened. That is, when the bit selection transistor 25 _i (i = 1,..., 8) is in the ON state, the write current threshold value I _co of this bit can be lowered. This state is called a bit half-selected state, and the write current threshold in this state is _Ich . In the present embodiment, the current threshold I _ch is, for example,
_{I ch ~I co / 2 (1} )
The parameters of the storage layer 21 and the like are set so as to be approximately.

  The conductive layer 12 is made of a material having a spin orbit interaction or a Rashba effect, is disposed under the MTJ element, and electrically connects adjacent MTJ elements in series. Typically, one byte (eight) is connected in series. Since the thickness of the conductive layer 12 is usually about 10 nm and its sheet resistance is as small as about 1000Ω, MTJ elements of about 1 byte (about 8) can be connected in series. Since the series resistance is about 10 kΩ, which is about the same as a fine transistor, a necessary write current can be supplied.

When the byte selection transistors 31 and 32 are turned on by the control circuit 110, the write current _Iw is supplied to the conductive layer 12. In the case of the memory cell 10 shown in FIG. 1, polarized electrons having spin in the depth direction of the paper are accumulated on the upper surface of the conductive layer 12 due to scattering of electrons due to the spin-initiated interaction in the conductive layer 12. Polarized electrons 13a and 13b having spins in the front direction of the paper are accumulated on the lower surface.

In the memory cell 10 having such a configuration, the bits are non-selected state, a write current when I _w exceeds the threshold current I _c0, accumulated interaction polarized electrons and the magnetization of the storage layer 21 (Spin Transfer Torque ) Can write information.

Similarly, the bit is half-selected state, when the write current I _w exceeds the threshold current I _{c0 / 2,} by interaction with accumulated spin-polarized electrons and the magnetization of the storage layer 21 (Spin Transfer Torque), information Can be written.

(Writing method)
Next, a writing method to the memory cell 10 shown in FIG. 1 will be described with reference to FIGS. In the present embodiment, writing to the memory cell 10 is performed in two stages. 2 and 3, the writing to the memory cell 10 shows the case where (0, 1, 1, 0, 0, 0, 0, 1) is written as 1-byte information.

First, as shown in FIG. 2, the byte select transistors 31 and 32, the ON bit selection transistors ₂₅ 1 to 25 ₈ by using a control circuit 110 and control circuit 120, the reference layer 23 of the MTJ element ₂₀ 1 to 20 ₈ A first potential (for example, a positive potential) is applied, and a write current _{Iw is} passed between the first terminal 12 a and the second terminal 12 b of the conductive layer 12. At this time, the magnetization stability (uniaxial magnetic anisotropy) of the storage layer 21 of all the MTJ elements 20 _{1 to} 20 ₈ becomes weak, and the threshold current thereof becomes I _c0 → I _ch . Therefore, the information “0”, that is, (0, 0, 0, 0, 0, 0, 0, 0) is _stored in all the MTJ elements 20 _{1 to} 20 ₈ with the write current I _w0 (I _w > I _w0 > I _ch ) ) Is written. Usually, it is allowed to flow 1.5 times the write current threshold current _{I ch,} since the write error rate can be reduced to about ^10-11,
I _{w0 to} 1.5 I _ch (2)
It becomes.

  Note that the increase and decrease in voltage polarity and perpendicular magnetic anisotropy vary depending on the nonmagnetic material and the storage layer material.

  In the simulation described below, the calculation is performed on the assumption that the anisotropy of the storage layer increases when a positive voltage is applied to the reference layer and the anisotropy decreases when a negative voltage is applied.

Simulation results supporting the above are shown in FIGS. 11 to 12C. FIG. 11 shows a threshold at which magnetization reversal occurs in the memory layer of the MTJ element when current is passed through the conductive layer when +0.5 V, 0 V, and −0.5 V are applied to the reference layer of the MTJ element. The result which _{calculated |} required electric current _Ic0 by simulation is shown. In FIG. 11, the vertical axis represents the voltage applied to the reference layer of the MTJ element, and the horizontal axis represents the threshold current I _c0 .

In FIG. 11, point P ₁ indicates that when a voltage of +0.5 V is applied to the reference layer of the MTJ element, the magnetization direction of the storage layer is parallel to the magnetization direction of the reference layer from the anti-parallel (AP) state (P ) shows the point where the change in the state, the point P _2, when a voltage is applied to the reference layer to + 0.5V of the MTJ element, parallel (P) state with respect to the magnetization directions of the reference layer of the storage layer It shows the point that changed from the anti-parallel (AP) state.

The point P _3, when applying a voltage of 0V to the reference layer of the MTJ element, that the magnetization direction of the storage layer is changed from anti-parallel (AP) state with respect to the magnetization direction of the reference layer in parallel (P) state The point P ₄ indicates that when a voltage of 0 V is applied to the reference layer of the MTJ element, the magnetization direction of the storage layer changes from the parallel (P) state to the anti-parallel (AP) state with respect to the magnetization direction of the reference layer. Indicates changed points.

Point P ₅ indicates that when a voltage of −0.5 V is applied to the reference layer of the MTJ element, the magnetization direction of the storage layer changes from the antiparallel (AP) state to the parallel (P) state with respect to the magnetization direction of the reference layer. A point P ₆ indicates a point where the magnetization direction of the storage layer is opposite from the parallel (P) state with respect to the magnetization direction of the reference layer when a voltage of −0.5 V is applied to the reference layer of the MTJ element. The point which changed to the parallel (AP) state is shown. A broken line connecting points P ₁ , P ₃ , and P ₅ indicates that the MTJ element changes from the AP state to the P state when the voltage applied to the reference layer of the MTJ element is changed from +0.5 V to −0.5 V. The threshold current I _c0 is shown. A broken line connecting points P ₂ , P ₄ , and P ₆ indicates that the MTJ element changes from the P state to the AP state when the voltage applied to the reference layer of the MTJ element is changed from +0.5 V to −0.5 V. The threshold current I _c0 when changing is shown.

12A to 12C show hysteresis curves when voltages of +0.5 V, 0 V, and −0.5 V are applied to the reference layer of the MTJ element, respectively. In these hysteresis curves, the vertical axis represents the resistance R of the MTJ element, and the horizontal axis represents the current I passed through the conductive layer. Points P _{1 to} P _{6 in} FIGS. 12A to 12C correspond to points P _{1 to} P ₆ shown in FIG. 11, respectively.

As can be seen from FIGS. 11 to 12C, when a positive voltage is applied to the reference layer of the MTJ element, the threshold current I _c0 is lower than when no voltage is applied. On the other hand, when a negative polarity voltage is applied to the reference layer of the MTJ element, the threshold current I _c0 increases as compared to the case where no voltage is applied.

FIG. 13 shows the experimental results for determining the relationship between the voltage applied to the MTJ element and the current value I _{SO, switching} observed in the magnetization reversal in the memory cell of the first embodiment.

  In this experiment, MgO / CoFeB was used for the nonmagnetic material / memory layer. In this combination of materials, the anisotropy of the memory layer decreased when a positive voltage was applied to the reference layer, and the anisotropy increased at a negative voltage.

FIG. 13 shows a characteristic in which the voltage V _MTJ applied to the MTJ element is taken on the vertical axis, and the current value _{ISO, switching} in which the magnetization reversal is observed flowing through the conductive layer is taken on the horizontal axis.

In FIG. 13, the region indicated by “P” indicates that the magnetization directions of the storage layer and the reference layer of the MTJ element are in parallel with each other, and the region indicated by “AP” refers to the storage layer of the MTJ element. It shows that the magnetization directions of the layers are antiparallel to each other. In FIG. 13, the current I flowing through the conductive layer is measured with a pulse width of several ms, and the absolute value itself should be smaller than the value of the threshold current I _{c0 in} the ns order. However, the change in the threshold current I _c0 when a voltage is applied supports the rough simulation result.

Then, bit select transistors of the bit to be written to data "1", for example, the ON by the bit selection transistor _{25 2,} 25 3, 25 ₈ control circuit 120, MTJ element _{20 2,} 20 3, 20 ₈ of the reference layer A second potential (for example, a positive potential) is applied to 23. At this time, the byte selection transistors 31 and 32 are also turned on using the control circuit 110, and the write current I _w1 (I _c0 > I _w1 > I _{ch in the} opposite direction to the case where information “0” is written to the conductive layer 12). ). Then, each of the storage layer 21 of the MTJ element _{20 2,} 20 3, 25 ₈ information "1" is written (Figure 3). At this time, as in the case described above,
I _w1 ~1.5I _ch (3)
It becomes. As a result, 1-byte information (0, 1, 1, 0, 0, 0, 0, 1) can be written by two write operations. The two write operations can be performed by the control circuit 110 and the control circuit 120 performing a cooperative operation. That is, the first writing circuit that performs the first stage writing and the second writing circuit that performs the second stage writing out of the two stages are configured across the control circuit 110 and the control circuit 120.

  The writing principle that has been well studied so far is called an STT (Spin Transfer Torque) writing method in which spin-polarized electrons are injected into a storage layer through a tunnel barrier.

  The writing used in the present embodiment uses an SOT (Spin Orbit Torque) writing method and a voltage writing method for setting a bit to a half-selected state. The principle of the SOT writing method is the interaction between the same polarized electrons and the electrons in the storage layer. Therefore, there is no significant difference in the write current threshold.

In the present embodiment, the write charge q _w = Qw / bit required per bit is q _w = (I _w1 × t _p + I _w0 × t _p ) / 8 (4)
It becomes. Here, t _p is a write pulse width.

On the other hand, the writing electric charge _{q w '' = Q w '} ' / bit per bit write charge _{q w '= Q w' /} bit, and normal SOT write per bit of a conventional STT writing,
q _w ′ = q _w ″ = (I _w ′ × t _p ) / 1
= 1.5I _c0 (5)
It is.

Therefore, according to the present embodiment, the write charge ratio (q _w / q _w ′, q _w / q _w ″) per bit is expressed as q _w / q _w ′ = q _w / q _w ″.
_{= {(I w1 × t p} + I w0 × t p) / 8} / {(I w '× t p) / 1}
= (I _w1 + I _w0 ) / (8I _w ′) = 3I _ch / (12I _c0 )
= 3I _ch / (24I _ch ) = 3/24 = 1/8
It can be.

  That is, according to this embodiment, the write charge can be reduced by almost an order of magnitude, and as a result, the write energy can be reduced by almost an order of magnitude.

Next, a method for selecting a write bit in the magnetic memory in which the memory cells 10 shown in FIG. 1 are arranged in an array will be described with reference to FIGS. FIG. 4 is a circuit diagram showing the magnetic memory 1 in which the memory cells 10 shown in FIG. 1 are arranged in a 2 × 2 array. This magnetic memory has memory cells 10 ₁₁ , 10 ₁₂ , 10 ₂₁ , 10 ₂₂ arranged in a 2 × 2 array.

In the memory cells 10 _i1 and 10 _i2 in the i-th (i = 1, 2) rows, the control terminal of the byte selection transistor 31 is connected to the byte selection word line SWL _i , and the second terminal is the first write word line WWL1 _i. The second terminal of the byte select transistor 32 is connected to the second write word line WWL2 _i . In the memory cells 10 _1j and 10 _2j in the j-th (j = 1, 2) column, the control terminal of the byte selection transistor 32 is connected to the byte selection bit line SBL _j .

In each memory cell 10 _ij (i, j = 1, 2), the bit selection transistor 25 _k (k = 1,..., 8) has the control terminal connected to the bit selection bit line bSBL _jk , and the second The terminal is connected to the write bit line bWBL _jk .

  An example of an equivalent circuit of the magnetic memory 1 configured as described above is shown in FIG.

4 and the bit selection method in the magnetic memory shown in FIG. 5, the case of selecting the MTJ element _{20 2,} 20 3, 20 ₈ of the memory cell _{10 12} as an example. First, select the byte to be written. That is, the byte selection word line SWL ₁ , the byte selection bit line SBL ₂ , the first write word line WWL _{1 1} , and the second write word line WWL 2 ₁ are activated. During this byte selection, the bit selection bit lines bSBL ₂₂ , bSBL ₂₃ , bSBL ₂₈ and the write bit lines bWBL ₂₂ , bWBL ₂₃ , bWBL ₂₈ are activated in advance to be in a half-selected state. As a result, information can be written into selected bits (for example, MTJ elements 20 ₂ , 20 ₃ , and 20 ₈ ) in a selected byte (for example, memory cell 10 ₁₂ ).

Reading is performed as follows. For example, when reading from the memory cell _{10 12,} and byte select transistors 31 and 32 of the memory cell _{10 12,} ON the bit selection transistor ₂₅ 1 to 25 _8, select read bit, write bit lines bWBL ₂₁ ~ The resistance of the bit selected by the current flowing through the bWBL ₂₈ is measured to determine the information. The resistance of the selected bit is measured by passing a constant current through the write bit lines bWBL _{21 to} bWBL ₂₈ and measuring the voltage between the reference layer and the storage layer of the selected bit (MTJ element). Also good.

  In the above case, the bit selection makes the bit easy to write, but the bit selection can increase the uniaxial magnetic anisotropy and conversely make writing difficult. For example, a negative potential is applied to the reference layer 23 of the selected bit. In this case, only non-selected bits are written. This has already been described with reference to FIGS.

  In addition, by setting the voltage application direction to a direction (polarity) in which writing is difficult even during reading, it is possible to completely prevent erroneous writing during reading. When the STT writing method is used, it is difficult to eliminate erroneous writing at the time of reading because spin torque acts regardless of which polarity is set. This problem is called “read disturb”, and is one of the major factors that hinder the STT write MRAM from increasing in capacity.

  In the above-described or later-described embodiments, an in-plane magnetization type MTJ element will be described as an example. However, the magnetoresistive element is not limited to this, and for example, a perpendicular magnetization type MTJ element can be used. Also in this case, as in the case of the in-plane magnetization type MTJ element, the bit selection transistor is turned on, and the bit is selected by decreasing or increasing the write threshold current.

(First modification)
A magnetic memory according to a first modification of the first embodiment will be described with reference to FIGS. 14A to 14C.

In the magnetic memory of the first modified example, the bit selection transistors 25 _{1 to} 25 ₈ connected to the reference layer 23 of each MTJ element are deleted in the magnetic memory of the first embodiment shown in FIG. The voltage applied to the layer 23 and the application timing are controlled by the control circuit 120.

14A and 14B are a cross-sectional view and a plan view, respectively, of the memory cell of the magnetic memory of the first modification. The lower layer of the MTJ element ₂₀ 1 to 20 ₈ are arranged conductive layer 12, arranged transistors 31 and 32 for controlling the ON / OFF of the write current, the bit line BL to the reference layer 23 of the MTJ element ₂₀ 1 to 20 ₈ It has a configuration which is arranged to connect the ₁ to BL _8. These bit lines BL _{1 to} BL ₈ are electrically connected to the control circuit 120 shown in FIG. 14B has a configuration in which two memory cells sharing bit lines BL _{1 to} BL ₈ are arranged, and a cross section of one of the memory cells is shown in FIG. 14A.

  Transistors 31 and 32 are arranged in semiconductor layers 4a and 4b, respectively. The transistor 31 has one of a source and a drain connected to the conductive layer 12 through the plug 5a, and the other connected to the word line WL1 through the plug 6a. The transistor 32 has one of a source and a drain connected to the conductive layer 12 through the plug 5b and the other connected to the word line WL2 through the plug 6b.

The magnetic memory of the first modified example configured as described above can be highly integrated as follows. When the in-plane magnetization method is used for the MTJ element, the aspect ratio is set to 2.5, for example, and the short side width is F, the 1-bit footprint (cell size) is (1 + 1) F × (2.5 + 1) ) may be a F = 7F ^2. In addition, when the perpendicular magnetization method is used for the MTJ element, the aspect ratio is set to 1, and the short side width is F, the 1-bit footprint (cell size) is (1 + 1) F × (1 + 1) F = 4F. ² is possible.

  Note that the integration can be further increased by using the configuration shown in FIG. 14C. In FIG. 14C, the conductive layer 12 of adjacent memory cells is shared, and the plug connecting one of the source and drain of the transistor 32 and the conductive layer 12 is shared to form one plug 5c. Yes. Note that a plug connecting one of the source and the drain of the transistor 31 and the conductive layer 12 may be shared to form one plug. With the configuration as shown in FIG. 14C, the MTJ elements are arranged at a constant pitch over a wide range, so that the patterning accuracy can be improved.

(Second modification)
A magnetic memory according to a second modification of the first embodiment will be described with reference to FIGS. 15A and 15B. FIG. 15A is a cross-sectional view of the memory cell of the magnetic memory of the second modified example. The memory cell 10 of the second modified example is the same as the memory cell of the first modified example shown in FIG. 14A, except that the bit selection is performed between the MTJ element 20 _i (i = 1,..., 8) and the bit line BL _i. The transistor 25 _i is arranged. In FIG. 15A, what is arranged on the side surface of each transistor 25 _i (i = 1,..., 8) is a gate 66 of each transistor. A gate insulating film 42 is disposed between the side surface of each transistor and the gate 66. That is, these transistors are vertical transistors.

Similarly to the magnetic memory of the first modification, the magnetic memory of the second modification can be highly integrated. Further, by adopting a configuration as shown in FIG. 15B, higher integration can be achieved. FIG. 15B shows a configuration in which a bit selection transistor 25 _i is arranged between the MTJ element 20 _i (i = 1,..., 8) and the bit line BL _{i in} the memory cell of the first modification shown in FIG. 14B. have. That is, when two memory cells shown in FIG. 15A are adjacent to each other, the conductive layer 12 of the adjacent memory cell is shared, and the plug that connects one of the source and drain of the transistor 32 and the conductive layer 12 is shared. To have a single plug 5c.

  In the first and second modified examples, the transistors 31 and 32 may be single crystal transistors or vertical transistors.

  As described above, according to the first embodiment and the modifications thereof, it is possible to provide a magnetic memory capable of realizing a reduction in energy consumption. In addition, high integration can be achieved.

(Second Embodiment)
In the magnetic memory shown in FIGS. 4 and 5, if you select the MTJ element _{20 2,} 20 3, 20 ₈ of the memory cell _{10 12,} MTJ element of the memory cell _{10 12 20 1,} 20 4 to 20 ₇ is in byte half-selected bit, MTJ element of the memory cell _{10 22 20 2,} 20 3, 20 ₈ is the bit half select bit. As described above, since there are many two types of half-selected bits, there is a possibility that erroneous writing occurs when the variation of the inversion current threshold value is large. Therefore, a magnetic memory having an array configuration that reduces the number of half-selected bits and substantially eliminates erroneous writing will be described as a second embodiment.

A magnetic memory according to the second embodiment is shown in FIG. The magnetic memory 1 of the second embodiment has memory cells 10 ₁₁ to 10 ₂₂ arranged in a 2 × 2 array. Each memory cell 10 _ij (i, j = 1, 2) has the same configuration as the memory cell 10 shown in FIG.

In the memory cells 10 _i1 and 10 _i2 in the i-th (i = 1, 2) _-th row, the control terminals of the byte selection transistors 31 and 32 are connected to the byte selection bit line SBL _i .

In the memory cells 10 _1j and 10 _2j in the j-th (j = 1, 2) column, the second terminal of the byte selection transistor 31 is connected to the first write word line WWL1 _j , and the second terminal of the byte selection transistor 32 is It is connected to the second write word line WWL 2 _j.

In each memory cell 10 _ij (i, j = 1, 2), the bit selection transistor 25 _k (k = 1,..., 8) has the control terminal connected to the bit selection word line bSWL _kj , and the second The terminal is connected to the common bit line BL _i .

  Writing in the magnetic memory of the second embodiment is performed as follows.

In the second embodiment, when a memory cell is selected and writing is performed to one or a plurality of MTJ elements of the selected memory cell (selected byte), the bit selection transistor 25 is used for the MTJ element to be written. the half-selected state by the corresponding bit select transistors of _to 253 ₈ to oN, by passing current through the conductive layer 12 by turning oN the byte select transistor 31 and byte select transistor 32, the half-selected state The MTJ element is written.

On the other hand, at the time of reading, to select the memory cell to be read, and the bit selection transistor 25 ₁ to 25 ₈ of the MTJ element that reads in the selected memory cell to ON, further byte select transistor 31 and byte select transistor 32 By turning on one or both of them, the MTJ element to be read is energized, and the data stored in the MTJ element is read.

  In the above case, the bit selection makes the bit easy to write, but the bit selection can increase the uniaxial magnetic anisotropy and conversely make writing difficult. In this case, only non-selected bits are written.

  According to the second embodiment, it is possible to provide a magnetic memory capable of realizing a reduction in energy consumption as in the first embodiment.

(Third embodiment)
A magnetic memory according to the third embodiment is shown in FIG. The magnetic memory 1 of the third embodiment has memory cells 10 ₁₁ to 10 ₂₂ arranged in a 2 × 2 array. Each memory cell 10 _ij (i, j = 1, 2) has a configuration in which the byte selection transistor 32 is deleted from the memory cell 10 shown in FIG.

In the memory cells 10 _i1 and 10 _i2 in the i-th (i = 1, 2) _-th row, the second terminal of the byte selection transistor 31 is connected to the first write bit line WBL1 _i , and the second terminal of the conductive layer 12 is the first 2 is connected to the write bit line WBL2 _i .

In the memory cells 10 _1j and 10 _2j in the j-th (j = 1, 2) column, the control terminal of the byte selection transistor 31 is connected to the byte selection word line SWL _j .

In each memory cell 10 _ij (i, j = 1, 2), the bit selection transistor 25 _k (k = 1,..., 8) has the control terminal connected to the bit selection word line bSWL _kj , and the second The terminal is connected to the common bit line BL _i .

  The magnetic memory of the third embodiment can be written and read by the same operation as the magnetic memory of the second embodiment. In the case of the third embodiment, even one byte selection transistor 31 can be written and read. However, as with the second embodiment shown in FIG. 5, the conductive layer 12 is opposite to the byte selection transistor 31. On the side, a byte selection transistor 32 and a wiring connected to the control terminal of the byte selection transistor 32 may be provided.

  According to the third embodiment, it is possible to provide a magnetic memory capable of realizing a reduction in energy consumption as in the second embodiment.

(Fourth embodiment)
A magnetic memory according to the fourth embodiment is shown in FIG. The magnetic memory 1 of the fourth embodiment has memory cells 10 ₁₁ to 10 ₂₂ arranged in a 2 × 2 array. Each memory cell _{10 ij (i, j = 1,2} ) has a structure in which a diode ₂₇ 1-27 ₈ instead of bit selection transistors ₂₅ 1 to 25 ₈ from the memory cell 10 shown in FIG. 1 . The cathode of each diode 27 _i (i = 1,..., 8) is connected to the second terminal of the corresponding MTJ element 20 _i .

In the memory cells 10 _i1 and 10 _i2 in the i-th (i = 1, 2) _-th row, the control terminals of the byte selection transistors 31 and 32 are connected to the byte selection bit line SBL _i .

In the memory cells 10 _1j and 10 _2j in the j-th (j = 1, 2) column, the second terminal of the byte selection transistor 31 is connected to the first write word line WWL1 _j , and the second terminal of the byte selection transistor 32 is It is connected to the second write word line WWL 2 _j.

In each memory cell 10 _ij (i, j = 1, 2), the anode of the diode 27 _k (k = 1,..., 8) is connected to the bit selection word line bSWL _kj .

  Next, writing in the magnetic memory 1 of the fourth embodiment will be described.

  In the magnetic memory 1 according to the fourth embodiment, when a memory cell is selected and writing is performed on one or a plurality of MTJ elements of the selected memory cell (selected byte), the MTJ element is connected. By applying a voltage to the selected bit selection word line (one or a plurality), the MTJ element to be written is set in a half-selected state, and the byte selection transistor 31 and the byte selection transistor 32 are turned on to form the conductive layer 12. A current is applied to write the MTJ element in the half-selected state.

  In the above case, the bit selection makes the bit easy to write, but the bit selection can increase the uniaxial magnetic anisotropy and conversely make writing difficult. In this case, only non-selected bits are written.

On the other hand, at the time of reading, a voltage is applied to the bit selection word line connected to the MTJ element that performs reading, and one or both of the byte selection transistor 31 and the byte selection transistor 32 are turned on, thereby reading the MTJ element. Is energized to read data stored in the MTJ element. A diode is connected to each of the magnetoresistive elements, which can prevent the read current from flowing around and greatly improve the S / N ratio of the read signal.
In the fourth embodiment, a plurality of MTJ elements can be connected to the two byte selection transistors 31 and 32. In FIG. 8, two byte selection transistors 31 and 32 are connected to _eight MTJ elements 20 _{1 to} 20 ₈ . One perpendicular magnetization type MTJ element can be formed with a 4F ² footprint. Here, F indicates a design rule. Since the footprint of the eight MTJ elements is 32F ² and a normal transistor can be created with a footprint of 6F ² , two transistors can be formed below the MTJ element. As a result, one bit of the footprint can be 4F ^2.

In the fourth embodiment, the cathode of each diode 27 _i (i = 1,..., 8) is connected to the second terminal of the corresponding MTJ element 20 _i , but the MTJ element to which the anode corresponds. 20 _i may be connected to the second terminal.

  According to the fourth embodiment, it is possible to provide a magnetic memory capable of realizing a reduction in energy consumption as in the first embodiment.

(Fifth embodiment)
In the magnetic memory 1 of the fourth embodiment, similarly to the magnetic memory of the first embodiment shown in FIG. 4, the magnetoresistive element connected to the bit line is in a half-selected state, and erroneous writing may occur. Therefore, a magnetic memory having an array configuration that reduces the number of half-selected bits and substantially eliminates erroneous writing will be described as a fifth embodiment.

FIG. 9 shows a magnetic memory according to the fifth embodiment. The magnetic memory 1 of the fifth embodiment has a configuration in which a plurality of cell groups are arranged in the column direction, and each cell group has the memory cells of the magnetic memory of the fourth embodiment arranged in 6 rows × 2 columns. has a configuration further provided with transistors ₂₈ 1 to 28 ₈ between cell groups in adjacent. By using such a configuration, the number of MTJ elements connected to the same bit line can be limited, the number of half-selected bits can be reduced, and erroneous writing can be suppressed.

In FIG. 9, each cell group has memory cells 10 ₁₁ to 10 ₆₂ arranged in 6 rows × 2 columns. Each memory cell 10 _ij (i = 1,..., 6, j = 1, 2) has the same configuration as the memory cell of the magnetic memory 1 of the fourth embodiment.

Transistors 28 ₁ to 28 ₈ disposed in the same row, the gate (control terminal) is connected to a wiring 34 provided newly, one of a source and a drain (first terminal) is the corresponding bit select word line (Fig. is connected to a corresponding one of the 8 reference), it is connected to a corresponding one of the source and drain of the other (second terminal) wiring is newly provided 35 _{1-35 8.}

  In FIG. 9, each cell group is composed of memory cells having the same number of rows, but may be composed of memory cells having different numbers of rows.

  Similarly to the fourth embodiment, the fifth embodiment can also provide a magnetic memory capable of realizing a reduction in energy consumption.

(Sixth embodiment)
A magnetic memory according to the sixth embodiment will be described with reference to FIG. The magnetic memory 1 of the sixth embodiment has the same configuration as the magnetic memory 1 of the first embodiment shown in FIG.

This writing method is performed in two stages as in the first embodiment. First, two kinds of potentials are applied to the selected bit to create a bit that is easy to write and a bit that is difficult to write. The number of MTJ elements connected to the bit line is reduced. For example, as shown in FIG. 10, the bit in the bit (MTJ _element) 20 2-20 ₈ to activate, the via the corresponding bit line selection transistors ₂₅ 2-25 ₈ for example positive potential Va, inactivate to (MTJ element) 20 _1, and applies a negative potential Vp via a corresponding bit line select transistor 25 _1. At this time, a write current is passed through the conductive layer 12 from the first terminal 12a toward the second terminal 12b, for example. Thus, the bit of activating (MTJ _element) in 20 2-20 _8, information "0" is written. Then, to apply a positive potential Va via the bit line selection transistor 25 ₁ to the MTJ element 20 _1, the MTJ element ₂₀ 2-20 _8, via the bit line selection transistor ₂₅ 2-25 ₈ example negative A potential Vp is applied, and a write current is passed through the conductive layer 12 from the second terminal 12b toward the first terminal 12a. Thus, the MTJ element 20 ₁ information "1" is written. As a result, digital information (1, 0, 0, 0, 0, 0, 0, 0) is written into the memory cell 10.

Assuming that the threshold current I _cha (= I _c0 / 2) of the activation bit and the threshold current I _chp of the inactivation bit, I _chp is I _chp = 1.5 I _c0 (6)
It is also possible to set. Therefore, the write current I _w0 is I _{w0 to} 1.5I _cha = 0.75 I _c0 (7)
And
I _w0 = 0.5 I _chp (8)
It becomes. As a result, the probability of occurrence of erroneous writing can be set to a negligible (<10 ⁻⁹ ) level.

  Note that writing in the present embodiment is performed using the control circuits 110 and 120 shown in FIG. 1 as in the first embodiment.

  The sixth embodiment can also provide a magnetic memory capable of realizing a reduction in energy consumption as in the first embodiment.

  As described above, according to each embodiment, digital information can be written to a plurality of magnetoresistive elements by two write operations, and the write energy can be reduced by almost one digit.

  Next, a method for further improving the write error rate WER (Write Error Rate) will be described.

したがって、非書き込み確率Ｐｎ_ＳＷは、Ｐｎ_ＳＷ＝１−Ｐ_ＳＷとなる。 The writing probability P _sw by one writing is approximated as follows (Springer Science + Business Media Dordrecht 2013 Yongbing Xu, David D. Awshalom and Junsaku Nitta, Handbook of Spintronics 10.1007 / 978-94-007-76004- 3_39-1).

Therefore, the non-write probability Pn _SW is Pn _SW = 1−P _SW .

Here, _{f 0} is usually considered to 1 × ¹⁰ 9 Hz order called trial frequency (attempt frequency). t _p is the write pulse width, I _w is the write current, and I _c0 is the inversion current value (write probability 50%) when interpolated to the write pulse width t _p = 1 ns. Δ _SW is an index indicating thermal stability, where ΔE _SW is a switching energy, k _B is a Boltzmann constant, and T is an absolute temperature. Δ _SW = (ΔE _SW / (k _B T)) It is represented by Moreover, x is a value of 1-2, and is a value determined by the magnetic memory.
The first method of improving a write error rate WER is to simply increase the write pulse width t _p. The ideal bit (memory elements, namely MTJ element), the write pulse width t inversion current value and _p increasing I _c0, i.e. by such a pulse width t _p is increased, in accordance with the above-described equation, the non-write probability Pn _SW Can be reduced.

For applications of storage class memory, it is possible to increase the write pulse width t _p to about 200 ns. Alternatively, it is also effective to apply a plurality of times a write pulse t _p.

Assuming that the write probability of the selected bit by one write pulse width t _p is P _sw and the non-write probability Pn _sw of the non-selected bit, a write pulse having a width of 2 t _p is applied, or two write pulses of the width t _p are applied. By applying twice, the probability that the selected bit cannot be written is (1−PS _sw ) ² , and the non-write probability of the non-selected bit is about 2Pn _sw . For example, when (1-PSsw) is set to 1 × 10 ⁻⁶ and Pn _SW is set to 1 × 10 ⁻¹¹ , the selection bit can be set by applying a write pulse having a width of 2 tp or applying a write pulse having a width tp twice. The write probability is about 1 × 10 ⁻¹² , and the non-write probability 2Pn _SW of the non-selected bit is 2 × 10 ⁻¹¹ . That is, by applying this write pulse, the probability of writing the selected bit and the probability of not writing the non-selected bit can be greatly improved. As a result, the write error rate WER can be reduced to 1 × 10 ⁻¹¹ units.

In the above description, an example in which the write current _Iw0 is reduced by applying a voltage and activating the bit has been described. However, when the in-plane magnetization type MTJ is used, a method of reducing the reversal current value _Ic0 itself Is described below.

As described above, the reversal current value I _c0 is proportional to the uniaxial magnetic anisotropy of the storage layer, more precisely to the uniaxial magnetic anisotropy energy ΔE _ret . Further, the inversion current value I _c0 is proportional to the switching energy ΔE _sw . For this reason, it can be described as shown in the following equation (9).
I _c0 = 4eα / hθ _SH (ΔE _ret + ΔE _sw ) t _be w _be / ARw _sl ² (9)
Here, e, α, h, θ _SH , ΔE _ret , ΔE _sw, AR, t _be , w _be , _sl , and w _sl are the electron charge, damping constant, reduced Planck constant, and spin injection, respectively. Efficiency, uniaxial magnetic anisotropy energy (retention energy), switching energy, storage layer (MTJ) spectrum ratio, conductive layer thickness, conductive layer width, storage layer thickness, storage layer width.

The switching energy ΔEsw is approximately the demagnetizing field energy in the vertical direction of the storage layer. If a perpendicular magnetic anisotropy having an appropriate magnitude is applied to the memory layer, the uniaxial magnetic anisotropy energy ΔE _ret can be maintained, and the decrease can be suppressed accurately, and the reversal current value I _c0 can be reduced. A calculation example of this effect is shown in FIG. FIG. 16 is a diagram showing the relationship between the interface magnetic anisotropy (Ks) generated at the interface between the storage layer and the tunnel barrier and the reversal current value I _c0 . As shown by the arrow in FIG. 16, the reversal current value I _c0 can be reduced to about ¼ by setting the interface magnetic anisotropy Ks to about 1.6 erg / cm ² . In this calculation, the damping constant α is set to 0.01.

(Example)
In the magnetic memories of the first to sixth embodiments and their modifications, adjacent bits (MTJ elements) are arranged close to each other, so that there is a concern that an interaction between bits may occur during miniaturization. Hereinafter, a magnetic memory that reduces the interaction between the bits and ensures a stable memory operation will be described as an example.

(First embodiment)
A magnetic memory according to the first embodiment will be described with reference to FIG. FIG. 17 is a cross-sectional view of the magnetic memory of the first embodiment in which the distance P _MTJ between the bits is simply increased and adjacent bits are arranged in a portion where the magnetic flux does not reach from the storage layer. If the distance P _MTJ between the bits is simply increased, the resistance of the conductive layer 12 is increased and adverse effects occur. Therefore, the thickness of the conductive layer 12 between the bits is increased, and the increase in the resistance of the conductive layer 12 is reduced. That is, a layer 50 of a material having a high conductivity is arranged between adjacent MTJ elements 20 _i , 20 _{i + 1} (i = 1,..., 8). For the layer 50, for example, Ta, W, Cu, or the like is used.

  Naturally, even when the distance between the bits is not increased, if the layer 50 is disposed between the bits to increase the thickness of the conductive layer 12 and suppress the increase in the resistance of the conductive layer 12, the voltage effect at the same portion can be reduced. Adverse effects and further reduction of energy consumption can be achieved.

In these cases, it is preferable to set the distance d between the MTJ element and the thick conductive layer 50 such that d ≧ λs to prevent an increase in the threshold current I _c0 . Here, λs is the spin diffusion length of the conductive layer 12 and is typically about 0.5 nm to 1 nm. In order to avoid increasing the resistance of the conductive layer 12, the distance d is
2λs> d ≧ λs
It is preferable to set to.

  18 to 21 show a method of manufacturing the magnetic memory of the first embodiment. First, a magnetic layer to be the storage layer 21, a nonmagnetic layer 22, and a magnetic layer to be the reference layer 23 are sequentially formed on the conductive layer 12. A mask 40 for patterning the MTJ element is formed on the magnetic layer 23 (FIG. 18).

  Next, the magnetic layer 23, the nonmagnetic layer 22, and the magnetic layer 21 are patterned using the mask 40 to form the MTJ element 20. Thereafter, a side wall 42 made of an insulator is formed on the side surface of the MTJ element 20 (FIG. 19). The thickness of the side wall 42 is the distance D between the MTJ element 20 and the thick layer 50.

  Next, as shown in FIG. 20, a layer 50 of a material having high conductivity is deposited. Subsequently, the layer 50 is etched until the upper surface of the sidewall 42 is exposed. Thereafter, the depth direction of the MTJ element 20 and the layer 50 is defined and processed. The mask 40 is removed to complete the memory cell of the magnetic memory (FIG. 21).

  According to this manufacturing method, since the conductive layer 50 between the bits can be formed by a self-alignment process, the thickness of the conductor layer between the bits can be increased even when the space between the bits is not increased. This is particularly effective for storage class memory applications in which a large number of bits are arranged on the same conductive layer.

  As shown in FIG. 22, a conductor 52 such as a via may be disposed under the conductive layer 12 to increase the thickness of the conductive layer between the bits, thereby suppressing an increase in resistance of the conductive layer. If the vias at both ends of the memory cell, that is, the plugs shown in FIG. 14A are used, they can be formed without increasing the cost.

(Second embodiment)
In the magnetic memory of the second embodiment, a synthetic memory layer 21A such as CoFeB / Ru / CoFeB is used as the memory layer 21 of the MTJ element which is a memory element (FIG. 23). In this case, since the leakage magnetic flux itself from the memory layer 21A can be reduced, the interaction between the memory layers of adjacent MTJ elements can be reduced even if the distance between the bits is short.

(Third embodiment)
As shown in FIG. 24, the magnetic memory of the third example includes a soft magnetic layer 60 made of, for example, NiFe or CoFeB below the conductive layer 12 in each memory cell of the magnetic memory of the first to sixth embodiments. Is added. By using such a configuration, the magnetic flux leakage from the storage layer can be absorbed by the soft magnetic layer 60, and the interaction between the storage layers of adjacent MTJ elements can be reduced while the distance between bits is short. In addition, the retention energy of the storage layer can be increased.

(Fourth embodiment)
As shown in FIG. 25, the magnetic memory of the fourth embodiment has a configuration in which a soft magnetic layer 66 is added around each of the MTJ elements 201 to 208 via an insulating layer 64. By using such a configuration, not only can the leakage magnetic flux from the storage layer be sucked by the soft magnetic layer 55, but the interaction between the storage layers of adjacent MTJ elements can be reduced while the distance between bits is short. The retention energy of the storage layer can also be increased. The magnetic film thickness (Ms × t ′) of the soft magnetic layer 66 is preferably set larger than the magnetic film thickness (Ms × t) of the storage layer. Here, Ms is the saturation magnetization of the storage layer, t is the thickness of the storage layer, Ms ′ is the saturation magnetization of the soft magnetic layer, and t ′ is the thickness of the soft magnetic layer.

  Note that, as shown on the left side in FIG. The MTJ element 20 may be disposed so as to surround the four side surfaces of the MTJ element 20, or may be disposed so as to cover the two opposite side surfaces of the MTJ element 20 as shown on the right side in FIG. . FIG. 26 is a plan view of a memory element (MTJ element).

  A manufacturing method in the case where the soft magnetic layer 66 is disposed so as to cover two opposing side surfaces of the MTJ element 20 is shown in FIGS.

  First, a magnetic layer to be the storage layer 21, a nonmagnetic layer 22, and a magnetic layer to be the reference layer 23 are sequentially formed on the conductive layer 12. A mask 40 for patterning the MTJ element is formed on the magnetic layer 23 (FIG. 27).

  Next, the magnetic layer 23, the nonmagnetic layer 22, and the magnetic layer 21 are patterned using the mask 40 to form the MTJ element 20. Thereafter, a side wall 42 made of an insulator is formed on the side surface of the MTJ element 20 (FIG. 28). The thickness of the side wall 42 is the distance D between the MTJ element 20 and the thick layer 50.

  Next, as shown in FIG. 29, after depositing the soft magnetic layer 66, a layer 50 of a material having high conductivity is deposited. Subsequently, the layer 50 is etched until the upper surface of the sidewall 42 is exposed. Thereafter, the depth direction of the MTJ element 20 and the layer 50 is defined and processed. The mask 40 is removed to complete the memory cell of the magnetic memory (FIG. 30). In this manufacturing method, since the layer 50 is formed between the adjacent bits, the resistance between the bits can be reduced.

  In the following, a device for writing the magnetic memory of the present invention at a higher speed will be described.

(5th Example)
A magnetic memory of the fifth embodiment will be described with reference to FIGS. 31A and 31B. The magnetic memory of this sixth embodiment has a configuration in which the long side direction of each MTJ element 20 is arranged in an oblique direction rather than 90 degrees with respect to the direction in which the conductive layer 12 extends (FIG. 31A). ).

  In the first to sixth embodiments and the first to first examples, the long side direction of each MTJ element 20 is arranged to be approximately 90 degrees with respect to the direction in which the conductive layer 12 extends. . For this reason, since the spin direction of electrons on the surface of the conductive layer 12 and the magnetization of the storage layer are parallel or antiparallel at the initial stage after the writing current flows, the spin transfer torque does not work in principle. Actually, a weak spin transfer torque works due to disturbance of the magnetization direction, etc., and after the precession of magnetization becomes large, a large spin transfer torque works to complete writing.

  In contrast, in the sixth embodiment, as shown in FIG. 31B, the magnetization 70 of the storage layer of the MTJ element faces the longest diagonal line. As a result, the spin direction of electrons on the surface of the conductive layer 12 and the magnetization of the storage layer have an angle θ that is parallel or antiparallel. Therefore, when a write current flows, a large spin transfer torque works and writing can be performed at high speed.

  The above has been described from the viewpoint of data writing. However, in practice, data reading must also be considered. In particular, in increasing the capacity and miniaturization, it is necessary to consider both the reduction in writing energy and the increase in resistance change rate (MR) of the magnetoresistive element.

  In this case, the point is to crystallize the interface of the storage layer with the nonmagnetic layer (for example, MgO) and to make (001) orientation together with MgO. For the MgO side of the memory layer, an amorphous material such as Co or Fe to which B (boron) or the like is added is usually used. Annealing this and releasing additional elements such as B to crystallize Co, Fe, etc., can realize an MR of 300%. For this reason, it is effective to arrange a material that absorbs an additive element such as B at the interface. In the first to sixth embodiments and Examples 1 to 6, it is effective to use a material that absorbs an additive element such as B for the conductive layer, and increasing the thickness is effective for increasing the MR.

(Sixth embodiment)
Next, a magnetic memory according to the sixth embodiment will be described with reference to FIGS. The magnetic memory of the sixth embodiment can be read at high speed.

  As shown in FIG. 32, one bit is composed of a pair of MTJ elements 20a and 20b, and information of opposite polarity is recorded in each MTJ element 20a and 20b. The read electrode 70 is disposed between the pair of MTJ elements 20a and 20b, the power supply voltage Vdd is applied to the reference layer 23 of the MTJ element 20b, the reference layer 23 of the MTJ element 20a is grounded, and the read voltage Vread is applied to the electrode 70. Thus, information is read through the electrode 70 (FIGS. 33 and 34). This improves the reliability of information and enables high-speed reading. Two transistors 72 a and 72 b are disposed below the conductive layer 12. In the transistor 72a, one of a source and a drain is connected to the conductive layer 12 through a plug 74a, and the other is connected to the wiring 77a through a plug 76a. In addition, one of a source and a drain of the transistor 72b is connected to the conductive layer 12 through the plug 74b, and the other is connected to the wiring 77b through the plug 76b. Information is written to the MTJ element 20 a by turning on the transistor 72 a and passing a write current between the wiring 77 a and the electrode 70. Information is written to the MTJ element 20 b by turning on the transistor 72 b and passing a write current between the wiring 77 b and the electrode 70.

(Seventh embodiment)
A magnetic memory according to the seventh embodiment will be described with reference to FIGS. The magnetic memory of the seventh embodiment is an example that realizes a significant improvement in writing speed. In the seventh embodiment, the major axis of the MTJ element is arranged to be inclined, and the inclination angle θ is set to θ <45 ° (see FIGS. 35 and 36). In the examples so far, the magnetization of the memory layer is reversed while precessing, so that a finite time, for example, several ns is required for writing. However, in the seventh embodiment, it does not cause precession and reverses. Therefore, writing can be performed in a time of 1 ns or less.

(Eighth embodiment)
A magnetic memory of the eighth embodiment will be described with reference to FIG. The magnetic memory of the eighth embodiment is used for a high-speed medium-capacity memory such as LLC (Last Level Cache). In the eighth embodiment, there are a plurality of bits arranged on the conductive layer 12, and each bit includes a pair of MTJ elements 20a and 20b and an electrode 71 arranged between the MTJ elements 20a and 20b. It is equipped with. Opposite polarity information is stored in the pair of MTJ elements 20 a and 20 b in each bit, and an intermediate potential between the pair of MTJ elements 20 a and 20 b is measured by the electrode 71.

(Seventh embodiment)
A magnetic memory according to the seventh embodiment is shown in FIG. The magnetic memory according to the seventh embodiment has a configuration in which peripheral circuits such as a write circuit and a read circuit are added to the magnetic memory 1 shown in FIG.

The first write word lines WWL1 ₁ and WWL1 ₂ of the magnetic memory 1 are connected to the first write circuit 120 via the first word line selection circuit 110, respectively. The first word line selection circuit 110 includes switch elements (FETs) 112 <1> and 112 <2> that are turned on / off by control signals Ayn <1> and Ayn <2>, respectively.

The cell selection circuit 114 sends the control signals Ac <k, 1> (k = 1,..., 8) to the bit selection word line bSWL _k1 of the magnetic memory 1, and the control signals Ac <k, 2> (k = 1,..., 8) are sent to the bit selection word line bSWL _k2 of the magnetic memory 1.

The second write word lines WWL2 ₁ and WWL2 ₂ of the magnetic memory 1 are connected to the second write circuit 125 via the second word line selection circuit 115, respectively. The second word line selection circuit 115 includes switch elements (FETs) 117 <1> and 117 <2> that are turned on / off by control signals Ays <1> and Ays <2>, respectively.

  The first write circuit 120 includes switch elements (FETs) 122a and 122b that are on / off controlled by control signals SRCn and SNKn, respectively.

  The second write circuit 125 includes switch elements (FETs) 127a and 127b that are on / off controlled by control signals SRCs and SNKs, respectively.

The byte selection bit lines SBL ₁ and SBL ₂ of the magnetic memory 1 receive control signals Axw <1> and Axw <2> from the second bit line selection circuit 140, respectively.

The bit lines BL ₁ and BL ₂ of the magnetic memory 1 are connected to the first read circuit 130 and the MTJ voltage application circuit 150 via the first bit line selection circuit 142, respectively. The second bit line selection circuit 142 includes switch elements (FETs) 142a and 142b that are on / off controlled by control signals Axe <1> and Axe <2, respectively.

  The first readout circuit 130 includes a switch element (FET) 130a that is ON / OFF controlled by a control signal SRCr, and a sense amplifier 139b.

  The second read circuit 135 includes a switch element (FET) 135a that is ON / OFF controlled by a control signal SNKr, and is connected to the switch elements 117 <1> and 117 <2> of the second word line selection circuit 115.

  The MTJ voltage application circuit 150 includes switch elements (FETs) 152a and 152b that are on / off controlled by control signals SRCv and SNKv, respectively.

  Control signals SRCv, SRCs, SRCn, SRCr, SNKv, SNKs, SNKn, and SNKr are output from the control circuit 160.

  Control signals Axw, Axe, Ayn, Ays, Ac are output from the decoder 170.

  In the seventh embodiment, the conductive layer to be energized at the time of writing is selected by the first word line selection circuit 110, the second word line selection circuit 115, and the first bit line selection circuit 140. The polarity of energization is performed by controlling the first write circuit 120 and the second write circuit 125. The MTJ element to which a voltage is applied at the time of writing is selected by the first bit line selection circuit 142 and the cell selection circuit 114. The voltage applied to the MTJ element is adjusted by the MTJ voltage application circuit 150, the first write circuit 120, and the second write circuit 125.

  Cell selection at the time of reading is performed by using the cell selection circuit 114, the second bit line selection circuit 140, the first bit line selection circuit 142, and the second word line selection circuit 115. The read current is performed by energizing between the first read circuit 130 and the second read circuit 135.

  The seventh embodiment can also provide a magnetic memory capable of realizing a reduction in energy consumption as in the second embodiment. Further, similarly to the second embodiment, the number of half-selected bits can be reduced, and erroneous writing can be substantially eliminated.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof as well as included in the scope and gist of the invention.

1 Magnetic Memory 10, 10 ₁₁ to 10 ₂₂ Memory Cell 12 Conductive Layer 12a First Terminal 12b Second Terminal 13a Electron with Up Spin 13b Electron with Down Spin 20 _{1 to} 20 ₈ Magnetoresistive Element (MTJ Element)
21 memory layer 22 a non-magnetic layer 23 reference layer 25 _{1-26 8-bit} select transistors 27 ₁ to 27 ₈ diodes 28 _{1-28 8} transistor 31 byte select transistor 32 byte select transistor 110 control circuit 120 control circuit

Claims (17)

A conductive layer having a first terminal and a second terminal;
And a plurality of magnetoresistive elements disposed apart from each other in the conductive layer between the first terminal and the second terminal, wherein each magnetoresistive element includes a reference layer, the reference layer, and the conductive layer. A plurality of magnetoresistive elements each including a storage layer disposed between the storage layer and a nonmagnetic layer disposed between the storage layer and the reference layer;
A magnetoresistive element to which data is to be written among the plurality of magnetoresistive elements by applying a first potential to the reference layer of the plurality of magnetoresistive elements and passing a first write current between the first terminal and the second terminal. A circuit for applying a second potential to the reference layer and flowing a second write current in a direction opposite to the first write current between the first terminal and the second terminal;
With magnetic memory. A conductive layer having a first terminal and a second terminal;
And a plurality of magnetoresistive elements disposed apart from each other in the conductive layer between the first terminal and the second terminal, wherein each magnetoresistive element includes a reference layer, the reference layer, and the conductive layer. A plurality of magnetoresistive elements each including a storage layer disposed between the storage layer and a nonmagnetic layer disposed between the storage layer and the reference layer;
A second group of magnetoresistive elements different from the first group of the plurality of magnetoresistive elements, wherein a first potential is applied to the reference layer of the first group of magnetoresistive elements of the plurality of magnetoresistive elements. A second potential different from the first potential is applied to the reference layer, a first write current is passed between the first terminal and the second terminal, and the first layer is applied to the reference layer of the magnetoresistive element. A second potential is applied and the first potential is applied to the reference layer of the second group of magnetoresistive elements, and a second direction opposite to the first write current is applied between the first terminal and the second terminal. A circuit for passing a write current;
With magnetic memory. A plurality of first transistors provided corresponding to the plurality of magnetoresistive elements, each transistor having a third and a fourth terminal and a first control terminal, the third terminal corresponding; A plurality of first transistors electrically connected to the reference layer of the magnetoresistive element;
A second transistor having fifth and sixth terminals and a second control terminal, wherein the fifth terminal is electrically connected to the first terminal;
The magnetic memory according to claim 1, further comprising:   4. The magnetic memory according to claim 3, wherein the plurality of first transistors have the first control terminals connected to a plurality of first wirings different from each other, and the fourth terminals are connected to one second wiring.   4. The magnetic memory according to claim 3, further comprising a third transistor having seventh and eighth terminals and a third control terminal, wherein the seventh terminal is electrically connected to the second terminal. The plurality of first transistors have the first control terminal connected to a plurality of first wirings different from each other, the fourth terminal connected to one second wiring,
6. The magnetic memory according to claim 5, wherein the second control terminal and the third control terminal are connected to one third wiring. A plurality of diodes provided corresponding to the plurality of magnetoresistive elements, each diode having a plurality of diodes electrically connected to the reference layer of the magnetoresistive element corresponding to one of a cathode and an anode; ,
A first transistor having third and fourth terminals and a first control terminal, wherein the third terminal is electrically connected to the first terminal;
The magnetic memory according to claim 1, further comprising:   The magnetic memory according to claim 7, further comprising a second transistor having fifth and sixth terminals and a second control terminal, wherein the fifth terminal is electrically connected to the second terminal.   The magnetic memory according to claim 8, wherein the first control terminal and the second control terminal are connected to one first wiring.   The magnetic memory according to claim 1, wherein in the magnetoresistive element, the nonmagnetic layer is an insulating layer. A first conductive layer having a first terminal and a second terminal;
A first magnetoresistive element and a second magnetoresistive element which are spaced apart from each other in the first conductive layer between the first terminal and the second terminal, wherein each of the first and second magnetoresistive elements is A first layer having a reference layer, a storage layer disposed between the reference layer and the first conductive layer, and a nonmagnetic layer disposed between the storage layer and the reference layer. 2 magnetoresistive elements;
A first potential is applied to the reference layers of the first and second magnetoresistive elements, a first write current is passed between the first terminal and the second terminal, and data of the first and second magnetoresistive elements is transmitted. A circuit for applying a second potential to the reference layer of the magnetoresistive element to be written and flowing a second write current in a direction opposite to the first write current between the first terminal and the second terminal;
With magnetic memory. A third terminal disposed in the conductive layer between the first terminal and the second terminal, wherein the first and second magnetoresistors are disposed in a region between the first terminal and the third terminal; A third terminal where the element is located;
A third magnetoresistive element and a fourth magnetoresistive element disposed in a region of the first conductive layer between the third terminal and the second terminal so as to be spaced apart from each other; Each includes a reference layer, a storage layer disposed between the reference layer and the first conductive layer, and a nonmagnetic layer disposed between the storage layer and the reference layer. And a fourth magnetoresistive element;
Further comprising
The circuit is
When writing to at least one of the first and second magnetoresistive elements, the first potential is applied to the reference layer of the first and second magnetoresistive elements, and the first terminal and The first write current is allowed to flow between three terminals, the second potential is applied to the reference layer of the magnetoresistive element to which data is to be written out of the first and second magnetoresistive elements, and the first terminal and the third terminal Passing the second write current between the terminals;
When writing to at least one of the third and fourth magnetoresistive elements, a third potential is applied to the reference layer of the third and fourth magnetoresistive elements, and the second terminal and third A third write current is allowed to flow between the terminals, a fourth potential is applied to the reference layer of the magnetoresistive element to which data is to be written out of the third and fourth magnetoresistive elements, and between the second terminal and the third terminal. The magnetic memory according to claim 11, wherein a fourth write current having a direction opposite to the third write current is passed. A first conductive layer having a first terminal and a second terminal;
A first magnetoresistive element and a second magnetoresistive element which are spaced apart from each other in the first conductive layer between the first terminal and the second terminal, wherein each of the first and second magnetoresistive elements is A first layer having a reference layer, a storage layer disposed between the reference layer and the first conductive layer, and a nonmagnetic layer disposed between the storage layer and the reference layer. 2 magnetoresistive elements;
A first potential is applied to the reference layer of the first magnetoresistive element and a second potential different from the first potential is applied to the reference layer of the second magnetoresistive element, and the first terminal and the second terminal A first write current is applied between the first magnetoresistive element, the second potential is applied to the reference layer of the first magnetoresistive element, and the first potential is applied to the reference layer of the second magnetoresistive element. A circuit for passing a second write current in a direction opposite to the first write current between a terminal and a second terminal;
With magnetic memory. A third terminal disposed in the conductive layer between the first terminal and the second terminal, wherein the first and second magnetoresistors are disposed in a region between the first terminal and the third terminal; A third terminal where the element is located;
A third magnetoresistive element and a fourth magnetoresistive element disposed in a region of the first conductive layer between the third terminal and the second terminal so as to be spaced apart from each other; Each includes a reference layer, a storage layer disposed between the reference layer and the first conductive layer, and a nonmagnetic layer disposed between the storage layer and the reference layer. And a fourth magnetoresistive element;
Further comprising
The circuit is
When writing to one of the first and second magnetoresistive elements, the first potential is applied to the reference layer of the first magnetoresistive element and the reference layer of the second magnetoresistive element And applying the second potential to the reference layer of the first magnetoresistive element, applying the second potential to the reference layer of the first magnetoresistive element, and applying the second potential to the reference layer. Applying the first potential to the reference layer of the resistive element and passing the second write current between the second terminal and the third terminal;
When writing to one of the third and fourth magnetoresistive elements, a third potential is applied to the reference layer of the third magnetoresistive element and applied to the reference layer of the fourth magnetoresistive element. Applying a fourth potential different from the third potential, passing a third write current between the second terminal and the third terminal, applying the fourth potential to the reference layer of the third magnetoresistive element; and 14. The fourth write current is applied to the reference layer of the fourth magnetoresistive element and a fourth write current having a direction opposite to the third write current is applied between the second terminal and the third terminal. Magnetic memory. A second conductive layer;
The first conductive layer has first to third parts, and the first part is located between the second part and the third part,
The memory layer of the first magnetoresistive element is located between the second part and the nonmagnetic layer of the first magnetoresistive element, and the third part and the nonmagnetic layer of the second magnetoresistive element The storage layer of the second magnetoresistive element is located between
The magnetic memory according to claim 11, wherein the second conductive layer is disposed in the first portion.   The magnetic memory according to claim 11, further comprising a soft magnetic layer disposed on each side portion of the first and second magnetoresistive elements.   The magnetic memory according to claim 1, wherein the circuit performs writing using a plurality of write pulses.

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