JP2005018650A - Nonvolatile semiconductor storage device and data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of easily, surely, and speedily performing interruption processing for requesting real-time responsiveness, and a data processor using this nonvolatile semiconductor storage device. <P>SOLUTION: In a flash memory, an interruption signal externally inputted to an interruption input terminal A is detected. When a writing/erasing operation is executed in the flash memory when the interruption signal is detected, suspending processing for interrupting the writing/erasing operation is executed. After switching to an array reading mode of the flash memory is ended, the flash memory outputs an interruption signal to a processor through an interruption output terminal B. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is used in, for example, a handheld computer, an electronic notebook, a mobile phone device, a memory card reader, and the like, and is a non-volatile semiconductor device capable of writing, erasing, or reading data, and a data processing device using the same as a data storage medium Related to
[0002]
[Prior art]
This type of non-volatile semiconductor device is used as a code storage type memory, a flash memory having a memory array structure called NOR type, for example, a handheld computer, an electronic notebook, a mobile phone device, a memory card reader, etc. It is. The flash memory has a characteristic of being nonvolatile and rewritable, and the memory contents can be easily corrected from this characteristic. As a result, the flash memory has rapidly become a code storage type memory, replacing the mask ROM which is difficult to modify the memory contents.
[0003]
FIG. 10 is a block diagram showing a main configuration of a conventional data processing apparatus using a flash memory as a code storage type memory.
[0004]
In FIG. 10, a data processing device 30 includes a flash memory 31 that is a nonvolatile semiconductor device capable of writing, erasing, and reading data, and a processor that executes write processing, erasing processing, and reading processing on the flash memory 31 32, and a plurality of buses connected to transmit various data between the flash memory 31 and the processor 32.
[0005]
The flash memory 31 includes a memory array, and a write / erase control circuit (WSM, Write State Machine) that controls a write operation and an erase operation for the memory array.
[0006]
The processor 32 includes the interrupt signal input unit 32a, and executes a write / erase routine processing unit 32b and an interrupt routine processing unit 32c. At this time, a suspend command is given to the flash memory 31 to temporarily interrupt the rewrite operation, and a software dual work method described later that switches to the read mode is used.
[0007]
The bus is equivalent to a bus when SRAM is used as a code storage type memory. With this bus configuration, the processor 32 directly fetches an instruction code (instruction code) indicating the type of instruction that the processor 32 operates from the flash memory 31, and executes instruction processing according to the instruction code.
[0008]
Hereinafter, the software dual work method used here will be described from the problem of the flash memory which is the premise.
[0009]
When a flash memory is used as a code storage type memory, it is required that the program code can always be accessed at the timing requested by the processor. As long as the flash memory is used as a ROM (code storage type memory), there is no problem at this point.
[0010]
However, in the data processing device 30, there is a need to provide not only the code storage function but also the flash memory 31 with the data storage function by using the rewrite function (write function and erase function) of the flash memory 31.
[0011]
When the flash memory 31 is used as a data storage type memory, the following first and second problems occur.
[0012]
First, the rewriting process of the flash memory 31 requires a very long latency (takes time) compared to SRAM and DRAM.
[0013]
Second, the processor 32 cannot read data stored in the memory array of the flash memory 31 during the rewrite operation of the flash memory 31. The reason why the data in the memory array cannot be read during the rewriting operation is that the contents stored in the register in the flash memory 31 are output in the flash memory 31 during the rewriting operation.
[0014]
For the above reasons, in the data processing device 30 on the premise of rewriting using the flash memory 31 as a data storage type memory, i) reading (that is, interrupt processing) to the memory array on the flash memory 31 is generated during the rewriting operation. And ii) there is a restriction that a program that must be executed during rewriting, including program code for rewriting, must not be placed in the flash memory 31.
[0015]
i) means that if there is an access request to the flash memory 31 from the outside during the rewrite operation, the response time of the flash memory 31 with respect to the access request becomes longer, and ii) the system of the data processing device 30 This means that the degree of freedom of design is significantly impaired.
[0016]
As a method for relaxing the constraints i) and ii), there are 1) a hardware dual work method and 2) a software dual work method.
[0017]
1) Hardware dual work method
The memory array portion of the flash memory 31 is divided into a plurality of banks. By limiting the memory array that cannot be accessed by rewriting to only the memory array in the same bank, an arbitrary read operation from the memory array in another bank can be performed. Thus, by dividing the memory array portion into a plurality of banks, the memory array for rewriting data and the memory array for storing the program code can be operated independently of each other. Thereby, the simultaneity of the rewrite operation and the read operation is ensured. Furthermore, by separating the code and data arrangement according to the bank configuration, the simultaneity of the rewrite operation and the read operation is ensured as described above, and the code fetch (instruction read operation) is inhibited during the data rewrite. never. An example of this method is disclosed in Patent Document 1.
[0018]
2) Software dual work method
By dynamically controlling the operating state of the flash memory 31 using software, the response from the external input to the response is improved. Specifically, a suspend command for interrupting the operation of the flash memory element and a resume command for resuming the interrupted operation are used for the flash memory 31. The state of the flash memory 31 being rewritten and the access request to the flash memory 31 for reading data are simultaneously monitored by software. When the software detects an access request to the flash memory 31, the software gives a suspend command to the flash memory 31, thereby temporarily interrupting the rewrite operation and then switching to the read mode.
[0019]
The operation of this software dual work method will be described with reference to FIG.
[0020]
FIG. 11 is a sequence diagram showing the operation of the conventional software dual work method. Here, the write / erase routine processing unit of the processor 32 controls all of the access request and the write processing, erase processing, and read processing of the flash memory 31, and the interrupt routine processing unit of the processor 32 executes the interrupt processing and A process related to the execution of the interrupt process (for example, a process of reading the program code of the interrupt process from the flash memory 31) is controlled.
[0021]
Operations (1) to (8) of this software dual work method are as follows.
[0022]
(1) In order to centrally manage the operation state of the flash memory 31, interrupt processing and task switching processing by the software dual work method are prohibited before writing / erasing. Access requests during this prohibition period are monitored by software in the write / erase routine processing unit 32b.
[0023]
(2) An access request from the outside is first detected by the monitoring process in the write / erase routine processing unit 32b and once held (stored).
[0024]
(3) A suspend command is issued to the flash memory 31 using an access request as a trigger.
[0025]
(4) After the suspend process is completed in the flash memory 31, the flash memory 31 is shifted to the array read mode.
[0026]
(5) After confirming the transition to the array read mode, the prohibition of interrupt and task switching processing is canceled. Thereafter, the held access request is released, the program code necessary for the process having the access request is read from the flash memory 341, and the process branches to the process having the access request.
[0027]
(6) After the process that requested the access is completed, the write / erase routine processing unit 32b of the flash memory 31 again prohibits the interrupt / task switching process.
[0028]
(7) A resume command for restarting the interrupted operation is issued to the flash memory 31, and the write / erase operation is restarted.
[0029]
(8) The operations of (2) to (7) are repeated as necessary, and after writing / erasing is completed, the interrupt is permitted and the processing is terminated.
[0030]
In such a software dual work system, the latency required to interrupt the rewrite operation is much shorter than the latency required to end the rewrite operation, so that the response speed of the system to an access request from the outside can be improved.
[0031]
In addition, the software dual work method allows more flexible system design with respect to the code / data arrangement compared to the hardware dual work method (however, the monitoring code for rewriting can be arranged / Exclusive access is mandatory for the memory to be executed).
[0032]
An example of this software dual work system is disclosed in Patent Document 2.
[0033]
Such a hardware dual work system and a software dual work system have been used in fields requiring low cost and high responsiveness as typified by mobile phone devices.
[0034]
[Patent Document 1]
JP-A-6-180999
[Patent Document 2]
JP-A-2-61896
[0035]
[Problems to be solved by the invention]
However, the conventional hardware dual work method and software dual work method have the following problems.
[0036]
The hardware dual work method cannot cope with an access request to a bank that is being rewritten. For example, i) the system used by the user is incompatible with the flash memory bank size, so that part of the instruction code extends to the memory array in the data rewrite bank. Ii) There are cases where there is an access request to the data itself recorded in the memory array in the rewrite bank as well as an access request to the instruction code. In such a data processing apparatus, it is essential to use a software dual work method.
[0037]
In the software dual work method, the overhead of the software portion is very large compared with the time required for the suspend operation of the flash memory 31, and the response speed of the data processing device 30 depends on the implementation method in the data processing device 30. As a result, the response speed may be lower than required. For example, i) the data processing device is a real-time system with severe restrictions on response time, and ii) the data processing device is hardware-based interrupt processing. There may be a processing system that cannot be controlled by software for an access request.
[0038]
To summarize the above, in the hardware dual work method and the software dual work method, (a) there is a code that needs to be processed at high speed in the memory array in the bank where the rewrite operation occurs, and (b) to this code There is a problem that it is not possible to cope with the case where the access of the software cannot be restricted by software, or (c) the case where the delay of the software dual work process is not allowed.
[0039]
It is the guarantee of the dual work operation in the interrupt processing that essentially includes such a problem.
[0040]
Interrupt processing is processing that occurs unexpectedly and is executed with priority, completely separate from processing currently being executed in the computer.
[0041]
Usually, a processor has one or a plurality of interrupt signal input terminals, and executes an interrupt process using an interrupt signal input to the interrupt signal input terminals as a trigger. The procedure for interrupt processing is as follows.
[0042]
1) The processor 32 interrupts the currently executing process using the input interrupt signal as a trigger, and saves the interrupted process.
[0043]
2) The processor 32 reads the branch destination address corresponding to the interrupt signal from the interrupt vector table, reads the interrupt subroutine stored in the branch destination designated by this address, and executes it with the highest priority. The interrupt vector table is a recording area in which the branch destination to the interrupt processing is described, and the interrupt subroutine is a program code of the interrupt processing itself.
[0044]
3) After the interrupt process is completed, the processor 32 returns to the temporarily saved process and executes it again.
[0045]
In such an interrupt process, a code necessary for executing the process may be recorded in the memory array in the bank where the rewrite operation occurs (corresponding to the above problem (a)).
[0046]
Further, since the processes 1) and 2) are automatically performed by the processor 32, software cannot normally interfere with these processes regardless of the user system. Further, since such interrupt processing is an accidental processing, the memory during the rewriting operation is predicted by executing the processing of 1) and 2) at the branch destination by predicting the occurrence of the interrupt processing in advance. Cannot be restricted by software (corresponding to (b) of the above problem).
[0047]
Even if software intervention is possible before the start of interrupt processing, such as by masking the interrupt signal, the interrupt handling program generally has a large overhead, so the execution of interrupt processing may be significantly delayed. Many. The interrupt processing is required to be processed at high speed, and the delay due to the software dual work method is not allowed for the interrupt processing (corresponding to (c) of the above problem).
[0048]
Therefore, in the data processing device 30 that uses the flash memory 31 as the code storage type memory and the data storage type memory, before the interrupt signal is input to the interrupt signal input terminal (interrupt signal input unit) of the processor 32, the interrupt vector and The branch destination must be accessible.
[0049]
The present invention solves the above-described conventional problems, and can perform a simple, reliable, and high-speed interrupt process that requires real-time responsiveness, and a data processing apparatus using the nonvolatile semiconductor memory device The purpose is to provide.
[0050]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device according to the present invention is an electrically readable / writable / erasable nonvolatile semiconductor memory device in which an interrupt signal input unit to which an interrupt signal is input from the outside and in response to the input interrupt signal And an interrupt signal output unit for outputting an interrupt signal to the outside after a predetermined interrupt preparation process, thereby achieving the above object.
[0051]
The control unit executes the predetermined interrupt preparation process, and the control unit responds to the input interrupt signal during the data write operation or the erase operation as the predetermined interrupt preparation process. At least a suspend process for interrupting the data write or erase operation and a process for shifting to the data read mode after the suspend process may be executed.
[0052]
After the above interrupt signal is output to the outside, interrupt processing is performed, and after detecting the input of a resume command for resuming the data write or erase operation, the processing for returning from the end of the interrupt processing to the data write or erase operation is performed. As a predetermined period for performing, a period for continuing the data reading operation may be provided.
[0053]
The control unit may perform control so that the write operation or the erase operation is resumed when a predetermined external signal indicating the end of the interrupt process is detected.
[0054]
The control unit stores a final address recorded in the program code of the interrupt processing in a memory array, and performs the write operation or the erase operation when the final address signal matches an externally input address signal. You may control to restart.
[0055]
The nonvolatile semiconductor memory device further includes a random access memory, and the control unit stores the final address recorded in the program code of the interrupt processing in the random access memory, and is input with the final address signal from the outside. Control may be performed so that the write operation or the erase operation is resumed when the address signal matches.
[0056]
The control unit may be configured with hardware.
[0057]
A data processing apparatus comprising: the nonvolatile semiconductor memory device; and a memory control unit that controls a data writing process, an erasing process, or a reading process for the nonvolatile semiconductor memory apparatus, and that can execute an interrupt process. The semiconductor memory device includes a control unit that outputs the interrupt signal to the memory control unit after interrupting the write operation or the erase operation in response to the input interrupt signal and shifting to the data read mode. The objective is achieved.
[0058]
The memory control means may execute interrupt processing on the nonvolatile semiconductor memory device by inputting the interrupt signal, and output a resume command to the nonvolatile semiconductor memory device at the end of the interrupt processing.
[0059]
With the above configuration, the operation of the present invention will be described below.
[0060]
In the present invention, during interrupt processing, an interrupt signal input unit (input terminal) to which an interrupt signal is input prior to the processor, and an interrupt signal output unit (output) that provides an interrupt signal to the processor after completion of the memory side preparation processing Terminals) or wiring lines are provided on the flash memory side.
[0061]
An interrupt signal input from the outside is first input to an interrupt input terminal on the flash memory side. An interrupt signal output from the flash memory is input to an interrupt input terminal on the processor side. Thereby, the flash memory can always know the occurrence of the interrupt processing prior to the processor. That is, before the processor starts the interrupt process, the flash memory can enter a preparatory process operation for the interrupt.
[0062]
The preparatory operation for an interrupt always includes the following items. That is, 1) interruption of the write / erase operation by suspend, and 2) switching to the array read mode. These operations can be automatically performed by hardware logic on the flash memory side regardless of software control. After executing at least the above two items, the flash memory outputs an interrupt signal to the processor, and the processor starts normal interrupt processing.
[0063]
When the interrupt process is completed, the flash memory must return to the original write / erase operation. In other words, when the interrupt process is finished and the process returns to the original process, it is necessary to resume the flash memory using some means.
[0064]
Therefore, by providing the interrupt signal input unit and the interrupt signal output unit on the flash memory side, the interrupt signal can be easily detected, and various preparation processes in the flash memory are performed prior to the interrupt process from the memory control means by the detection. It becomes possible. As a result, the present invention can provide a nonvolatile semiconductor memory device capable of processing interrupt processing that requires real-time responsiveness simply, reliably, and at high speed, and a data processing device using the nonvolatile semiconductor memory device. become.
[0065]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, Embodiments 1 to 3 of the present invention of the data processing apparatus will be described with reference to the drawings.
[0066]
[Embodiment 1]
FIG. 1 is a schematic diagram of the main components of the data processing apparatus according to the first embodiment.
[0067]
In FIG. 1, a data processing apparatus 10 according to the first embodiment includes a flash memory 11 that is a nonvolatile semiconductor device that can electrically write, erase, or read data, and write processing and erasure on the flash memory 11. The processor 12 is a memory control means for executing processing and reading processing, and the flash memory 11 and the processor 12 are provided with a plurality of buses connected to transmit various data.
[0068]
The flash memory 11 includes a memory array, a write / erase control circuit (WSM) as a control unit for controlling write operations and erase operations for the memory array, an interrupt input unit 11a, and an interrupt to which an interrupt signal is externally input. An input terminal [A] as a signal input input unit, a register for holding an externally input interrupt signal, and an output terminal [B] as an interrupt signal output unit for outputting the interrupt signal held in the register to the processor Including.
[0069]
The processor 12 executes a write / erase routine processing unit 12 a that controls write processing and erase processing, and an interrupt routine processing unit 12 b that executes interrupt processing in response to an interrupt signal input from the flash memory 11.
[0070]
Due to the bus configuration arranged between the flash memory 11 and the processor 12, the processor 12 has an address bus that transmits an address to the flash memory 11, a data bus that transmits and receives data between the processor and the flash memory, and a flash A control bus for transmitting control signals (for example, a chip enable signal, an output enable signal, and a write enable signal) for controlling processing of the memory is included. In FIG. 1, CE represents a chip enable signal, OE represents an output enable signal, WE represents a write enable signal, Address represents an address signal, and DQ represents data.
[0071]
The features of the first embodiment will be described below.
[0072]
The feature of the first embodiment is that interrupt preparation processing such as interruption processing (suspend processing) of the writing operation and erasing operation and switching to the array reading mode of the flash memory is performed on the flash memory side (hardware) according to the external input of the interrupt signal. (The software side), and the interrupted write operation or erase operation is resumed (resume processing) after the interrupt processing is completed, and the issue of a resume command (instruction) is left to the software side. That is, the suspend process is handled by hardware, and the resume process is handled by software.
[0073]
The reason is as follows.
[0074]
When viewed from a software perspective, interrupt processing is a kind of subroutine call. The activation is an irregular call by an external response, and the start timing and start address are not uniquely determined. For this reason, it is difficult to control the activation of interrupt processing by software. Conversely, the end of the interrupt process is determined by a return code explicitly written in the program code written by the user, and the return address is unique. Therefore, it is easy to control the end of interrupt processing by software. Therefore, it is desirable to leave the issue of the resume command to the software side rather than to the hardware side.
[0075]
Further, by leaving the issue of the resume command to the software side, the hardware side does not need a special mechanism for monitoring the timing of issuing the resume command, and the hardware logic can be simplified. It also leads to a reduction in processing load caused by monitoring resume timing.
[0076]
On the other hand, in terms of hardware, the detection is easy because the input to the dedicated input terminal is performed when the interrupt process is started. On the other hand, when the interrupt process ends, the return address depends on the branch destination and is not unique, so it is difficult to detect. Therefore, it is desirable to leave the interruption of the write operation and the erase operation according to the external input of the interrupt signal to the hardware side (that is, the flash memory side).
[0077]
The operation of interrupt processing by the data processing apparatus 10 according to the first embodiment will be described below.
[0078]
FIG. 2 shows a sequence diagram of interrupt processing by the data processing apparatus of the first embodiment.
[0079]
Operations (1) to (8) of this interrupt processing are as follows.
[0080]
(1) The write / erase control circuit of the flash memory 11 executes a suspend operation of a write / erase operation when an interrupt signal is externally input to the interrupt input terminal [A].
[0081]
(2) The write / erase control circuit of the flash memory 11 switches to the array read mode after the suspend operation is completed.
[0082]
(3) The flash memory write / erase control circuit causes the processor to output an interrupt signal INT from the interrupt signal output terminal [B] after completion of switching to the array read mode.
[0083]
(4) It is assumed that the processor 12 always issues a resume command to the flash memory 11 immediately before the return instruction at the end of interrupt processing. The write / erase control circuit of the flash memory 11 continues the array read mode for a period necessary for fetching the return instruction before entering the resume process in response to the input of the resume command.
[0084]
In response to the input of the resume command, the flash memory 11 maintains the array read mode for the period [C] necessary for fetching the return instruction before entering the resume operation, and then performs the resume operation. This ensures that the processor 12 executes the return instruction immediately after the resume operation.
To do.
[0085]
FIG. 3 is a flowchart showing the automatic suspend operation executed in the flash memory 11.
[0086]
The flash memory 11 detects an interrupt signal externally input to the interrupt input terminal [A]. If a write / erase operation is being executed in the flash memory 11 when an interrupt signal is detected, the interrupt signal is held (recorded) (S1), and then a suspend process is executed to interrupt the write / erase operation. (S2). Next, the flash memory 11 performs switching to the array read mode by saving data related to the write / erase operation to a predetermined buffer by the write / erase control circuit (S3). Until this stage, the externally input interrupt signal is held (recorded) in the flash memory 11 and is not output to the processor 12. After the flash memory 11 is switched to the array read mode, the flash memory 11 outputs an interrupt signal to the processor 12 through the interrupt output terminal [B].
[0087]
On the other hand, if the flash memory 11 is already in the array read mode when the flash memory 11 detects an interrupt signal externally input to the interrupt input terminal [A], the flash memory 11 does not hold the interrupt signal and does not hold the interrupt signal. The signal is output through from the interrupt signal output terminal to the processor.
[0088]
FIG. 4 is a flowchart showing the procedure of the resume process (5) shown in FIG.
[0089]
The flash memory 11 maintains an array read mode of several cycles from the input of the resume command to the start of the resume process (that is, the return instruction fetch period [C] shown in FIG. 2) (S11). When the period [C] has elapsed (in the case of YES) (S12), the flash memory executes a resume operation (S13). When the period of [C] has not elapsed (in the case of NO) (S12), the flash memory 11 maintains the array read mode.
In the return instruction fetch period, the processor 12 fetches the return instruction (that is, the return code), ends the interrupt processing, and executes the return from the interrupt routine processing unit 12b to the write / erase routine processing unit 12a.
[0090]
When an interrupt signal is input during the fetch period of the return instruction, the interrupt signal is held until the flash memory 11 finishes the resume process. The held interrupt signal serves as a trigger for the next suspend process performed after the resume process is completed.
[0091]
In parallel with the return of the processor 12 from the interrupt process or after the return is completed, the flash memory 11 starts the resume process and resumes the write / erase operation.
[0092]
[Embodiment 2]
The configuration of the data processing apparatus 10A of the second embodiment is the same as the configuration of the data processing apparatus 10 of the first embodiment except for the internal configuration of the flash memory. The components of the second embodiment that are the same as the components of the first embodiment are indicated by the same reference numerals as in the first embodiment. The description of the same components as those in the first embodiment is omitted.
[0093]
In addition to the components of the flash memory 11 of the first embodiment, the flash memory 11A of the second embodiment further includes a buffer for storing an arbitrary address therein (the address value on the buffer can be changed to an arbitrary value by the user) Comparison to determine whether the address on the address bus (address signal indicating this address) and the address stored in the buffer (memory array) (address signal indicating this address) match. Including For this match determination, data matching means can be used in addition to the comparator, and the data matching means can be constituted by a logic circuit such as an AND circuit.
[0094]
It is assumed that the final address describing the return code at the end of the program code for interrupt processing is registered on this buffer.
[0095]
This address is an address that triggers a suspend operation.
[0096]
The features of the second embodiment will be described below.
[0097]
The feature of the second embodiment is that, as in the first embodiment, in addition to entrusting the suspend process to the hardware (flash memory) side, the resume command issuance is also entrusted to the flash memory 11A side.
[0098]
As described above, from the viewpoint of hardware, at the end of interrupt processing, the return address depends on the branch destination and is difficult to detect because it is not unique.
[0099]
However, the resume command issuance can be automatically executed on the flash memory 11A side by making the resume command issuance trigger the detection of the address input on the address bus. As an address to be detected, an address value on a buffer prepared in the flash memory 11A is used. This address value can be set to an arbitrary value by the user's hand.
[0100]
In order to trigger the resume command issuance to detect the address input on the address bus, for example, it is necessary to cover the end address of the interrupt processing and hold it in the flash memory 11A. Whether or not the end address of the interrupt process can be covered and held on the flash memory 11A depends on the implementation of the architecture for the interrupt process of the processor 12.
[0101]
Therefore, the practical limitation of entrusting the issue of the resume command to the flash memory 11A side is the implementation of the architecture. For example, an architecture in which interrupt input signals and interrupt processing correspond one-to-one like the X86 architecture can be realized relatively easily by preparing buffers for the number of signals.
[0102]
As a result, in the data processing apparatus 10A of the second embodiment, it is possible to immediately perform the return processing to the write / erase operation after completing the interrupt processing. Further, in the data processing apparatus according to the second embodiment, no special consideration is required for the suspend / resume operation of the flash memory 11A for interrupt processing on the user side and the system side, thereby greatly reducing the system design burden. .
[0103]
The operation of the data processing apparatus 10A according to the second embodiment that executes interrupt processing will be described below.
[0104]
FIG. 5 shows a sequence diagram of interrupt processing by the data processing apparatus 10A of the second embodiment.
[0105]
The write / erase control circuit of the flash memory 11A receives the interrupt input from the interrupt processing input terminal [A] and suspends the write / erase operation. This automatic suspend operation is the same as the suspend operation of the first embodiment (see FIG. 3).
[0106]
Next, the write / erase control circuit of the flash memory 11A switches to the array read mode after the suspend operation is completed.
[0107]
The write / erase control circuit of the flash memory 11A causes the processor 22 to output an interrupt signal from the interrupt processing output terminal [B] after completing the switching to the array read mode.
[0108]
In the suspended array read mode, the flash memory 11A compares the address on the input address bus with the address on the buffer one by one by the comparator. If the two match, the flash memory 11A executes the resume operation.
[0109]
The method for registering addresses in the address buffer conforms to Japanese Patent Laid-Open No. 2001-306400.
[0110]
FIG. 6 shows a flowchart relating to the resume operation (4) of the second embodiment.
[0111]
The flash memory 11A monitors the address bus after shifting to the suspended state (S21). Address monitoring is performed even when the flash memory 11A is not selected.
[0112]
The comparator of the flash memory 11A compares the input value to the address bus with the address value in the buffer in the flash memory 11A to determine whether both values match (YES) or not (NO). (S22).
[0113]
The timing at which the address value on the address bus matches the address value on the buffer is the timing at which the processor 12 fetches the return code, and it can be determined that the interrupt processing has been completed at this timing. Therefore, the write / erase control circuit of the flash memory 11A according to the second embodiment executes the resume process when the address on the address bus matches the address on the buffer (S23). It is assumed that the address value registered in the buffer is the same as the address where the return code is arranged in the flash memory 11A.
[0114]
[Embodiment 3]
FIG. 7 is a main part schematic diagram of the data processing apparatus configuration of the third embodiment.
[0115]
The configuration of the data processing apparatus of the third embodiment is different from the configuration of the data processing apparatus 10A of the second embodiment in the following points.
[0116]
In the data processing device 20 of the third embodiment, the flash memory 21 shares a bus for transmitting DQ, CE signal (S-CE signal) and WE signal (S-WE signal) from the processor 23 to the RAM 22 with the RAM. To do. The flash memory 21 is provided with a return address detection chip select terminal and a write enable terminal in addition to a normal chip select terminal. The return address detection chip select terminal is connected to the chip select input from the processor 23 to the RAM 22 together with the chip select terminal provided in the RAM 22. As a result, the flash memory 21 can monitor the CE signal or the WE signal transmitted from the processor to the RAM via the data bus. As a result, the flash memory 21 can acquire the timing when the processor 23 saves the program counter in the RAM 22.
[0117]
The RAM 22 transmits a CE signal (S-CE signal), a WE signal (S-WE signal), and an OE signal (S-OE signal) only to the RAM 22 from the processor 23, and S to the RAM 22 from the processor 23. An address bus for transmitting addresses;
[0118]
As in the second embodiment, the third embodiment is characterized in that the suspend process is left to the hardware (flash memory) side and the resume command issuance is left to the flash memory side.
[0119]
The trigger for issuing the resume command is to detect a specific address input to the address bus. As an address to be detected, an address value on a buffer prepared in the flash memory 21 is used. Each time an interrupt process occurs, the flash memory 21 reads the value of the program counter that the processor 23 saves on the stack area of the RAM 22 and automatically sets it in the buffer. Note that the value of the program counter is a return address that is restored when interrupt processing ends.
[0120]
Detection of saving of the program counter is performed by monitoring the chip select and write enable of the RAM 22 when the program counter is written on the RAM 22 having the stack area immediately after the processor 23 starts interrupt processing. When the flash memory 21 detects saving of the program counter, the flash memory 21 saves the program counter input from the data bus on the buffer. Since the saved program counter is a return address that is restored at the end of interrupt processing, it is determined that the interrupt processing has ended when the address next appears on the address bus, and the resume operation of the flash memory 21 is performed. Can be executed.
[0121]
As a practical limitation, whether or not the program counter can be detected and stored in the flash memory 21 depends on the architecture of the processor 23 for interrupt processing. Many conventional processors that do not have a shadow register dedicated to interrupt processing push the current program counter onto the stack area simultaneously with the start of interrupt processing. The configuration of the data processing apparatus according to the third embodiment can be applied to such a processor.
[0122]
FIG. 8 is a sequence diagram of interrupt processing by the data processing device 20 according to the third embodiment.
[0123]
(1) The write / erase control circuit of the flash memory 21 receives the interrupt input from [A] and executes the suspend process of the write / erase operation.
[0124]
(2) The flash memory write / erase control circuit switches to the array read mode after the suspend process is completed.
[0125]
(3) The write / erase control circuit of the flash memory 21 outputs an interrupt to the processor 23 from the interrupt signal output terminal [B] after completing the switching to the array read mode.
[0126]
(4) The flash memory 21 monitors the chip select terminal and the write enable terminal of the RAM 22 having the stack area, and detects that the processor 23 has saved the program counter on the stack. The data on the data bus at the time of detection is the program counter, and the flash memory 21 sets the value of the program counter in its own buffer.
[0127]
(5) In the suspended array read mode, the flash memory 21 compares the input address on the address bus with the address on the buffer. If the two match, the flash memory 21 resumes. The resume operation of the data processing device 20 of the third embodiment is the same as the resume operation (see FIG. 6) of the data processing device of the second embodiment.
[0128]
FIG. 9 shows a flowchart of the automatic suspend operation by the data processing apparatus 20 of the third embodiment.
[0129]
If the flash memory 21 detects that an interrupt signal is input to the interrupt input terminal [A] and the write / erase operation is being performed, the flash memory 21 holds the interrupt signal (S31), and then performs the write / erase operation. Suspend processing is executed (S32). Next, the flash memory 21 is switched to the array read mode (S33). The interrupt signal is held in the flash memory 21 and is not output to the processor 23 from when the interrupt input is detected until the array read mode is switched. After the switching to the array read mode is completed, the flash memory 21 releases (outputs) an interrupt signal to the processor through the interrupt output terminal [B] (S34).
[0130]
If the flash memory 21 is in the array read mode when it detects that an interrupt signal is input to the interrupt input terminal, the flash memory 21 does not hold the interrupt signal in the flash memory 21 but sends an interrupt signal to the processor 23. Through output. After the interrupt signal is output to the processor 23, the flash memory 21 monitors the RAM data bus in preparation for saving the program counter by the processor (S35). The monitoring of the data bus is performed even when the flash memory 21 is not selected.
[0131]
When the flash memory 21 outputs an interrupt signal to the processor 23, the processor 23 saves the program counter value in the stack area on the RAM.
[0132]
If there is a write to the SRAM (in the case of YES) (S36), the flash memory 21 considers that the program counter has been saved, and stores the read program counter value in the buffer inside the flash memory 21 (S37). When there is no writing in the SRAM (NO) (S36), the flash memory 21 continues to monitor the RAM data bus in preparation for saving the program counter by the processor (S35).
The processor 23 issues a resume command using this program counter value.
[0133]
In the first to third embodiments, the suspend process or the suspend process and the resume process are supported on the flash memory side. However, if the controller is configured by hardware, a controller outside the flash memory is provided. It may be done.
[0134]
【The invention's effect】
As described above, the data processing apparatus of the present invention processes the suspend process or the suspend process and the resume process with the control device configured by hardware. As a result, the present invention can provide a nonvolatile semiconductor memory device capable of processing interrupt processing requiring real-time responsiveness easily, reliably, and at high speed, and a data processing device using the nonvolatile semiconductor memory device. To.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a main part of a configuration of a data processing apparatus according to an embodiment of the present invention.
FIG. 2 shows a sequence diagram of interrupt processing in the embodiment of the present invention.
FIG. 3 is a flowchart related to an automatic suspend operation executed in a flash memory.
FIG. 4 is a flowchart showing a resume process procedure shown in FIG. 2;
FIG. 5 shows a sequence diagram of an interrupt in another embodiment of the present invention.
FIG. 6 is a flowchart related to a resume operation according to another embodiment of the present invention.
FIG. 7 is a schematic diagram of a main part of a configuration of a data processing apparatus according to still another embodiment of the present invention.
FIG. 8 is a sequence diagram of interrupt processing by a data processing apparatus according to still another embodiment of the present invention.
FIG. 9 shows a flowchart of an automatic suspend operation by a data processing apparatus according to still another embodiment of the present invention.
FIG. 10 is a schematic diagram showing the main components of a conventional data processing apparatus.
FIG. 11 is a sequence diagram showing the operation of the conventional software dual work method.
[Explanation of symbols]
10 Data processing device
11 Flash memory
11a Interrupt input part

Claims (10)

In a nonvolatile semiconductor memory device capable of electrically writing, erasing or reading data,
Nonvolatile semiconductor memory device having an interrupt signal input unit to which an interrupt signal is input from the outside, and an interrupt signal output unit for outputting an interrupt signal to the outside after a predetermined interrupt preparation process in response to the input interrupt signal . The control unit executes the predetermined interrupt preparation process, and the control unit responds to the input interrupt signal during the data write operation or the erase operation as the predetermined interrupt preparation process. The nonvolatile semiconductor memory device according to claim 1, wherein at least a suspend process for interrupting the data write operation or erase operation and a process for shifting to a data read mode after the suspend process are executed. After the interrupt signal is output to the outside, interrupt processing is performed according to an instruction from the outside, and after detecting the input of a resume command for resuming the data writing operation or erasing operation, data writing from the end of the external interrupt processing is performed. 3. The nonvolatile semiconductor memory device according to claim 2, wherein a period for continuing the data reading operation is provided as a predetermined period for performing the return processing to the erasing operation. 4. The nonvolatile semiconductor memory device according to claim 3, wherein when the return processing to the interrupted write operation or erase operation is completed, the control unit controls to resume the interrupted write operation or erase operation. 5. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the control unit performs control so that the write operation or the erase operation is resumed when a predetermined external signal indicating the end of the interrupt process is detected. 5. The control unit stores the final address recorded in the program code of the interrupt processing in a memory array, and performs the write operation or erase operation when the final address signal matches an address signal input from the outside. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is controlled to resume. The nonvolatile semiconductor memory device further includes a random access memory, and the control unit stores the final address recorded in the program code of the interrupt processing in the random access memory, and the final address signal is input from the outside. 6. The nonvolatile semiconductor memory device according to claim 1, wherein control is performed so that the write operation or erase operation is resumed when the address signal matches. The nonvolatile semiconductor memory device according to claim 1, wherein the control unit is configured by hardware. 9. The non-volatile semiconductor memory device according to claim 1, and a memory control means for controlling a data write process, an erase process or a read process for the non-volatile semiconductor memory apparatus so as to execute an interrupt process. In a data processing apparatus having
The nonvolatile semiconductor memory device has a control unit that outputs the interrupt signal to the memory control means after interrupting the write operation or the erase operation in response to the input interrupt signal and shifting to the data read mode. apparatus. 10. The memory control unit according to claim 9, wherein the memory control unit executes an interrupt process for the nonvolatile semiconductor memory device in response to the input of the interrupt signal, and outputs a resume command to the nonvolatile semiconductor memory device at the end of the interrupt process. The data processing apparatus described.

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