JP2001117819A - Instruction memory circuit and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of a CPU by shortening its stall time. SOLUTION: This invention is constituted by dividing the instruction memory space of a main storage device 7 into an fixed area memory 1 and a cache memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction memory circuit and an information processing system in which an instruction memory space is divided into a fixed area memory and a cache memory.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a conventional information processing system using a cache memory. In FIG.
U101 fetches an instruction code from the cache memory 102. At this time, if a cache miss occurs,
The instruction code is transferred from the main storage device 103 to the cache memory 102 via the data transfer path 104, and thereafter,
The instruction code transferred from the main storage device 103 due to the cache miss is fetched from the cache memory 102 to the CPU 101. As described above, while the instruction code is being transferred from the main storage device 103 to the cache memory 102, the CPU 101 is in a stalled state.

On the other hand, the CPU 101 has an interrupt processing function. When an interrupt process occurs during execution of an instruction by the CPU 101, a cache miss occurs in the instruction before the interrupt process occurs, and the cache memory 102 is transferred from the main storage device 103 to the cache memory 102 via the data transfer path 104. If the instruction code is being transferred, interrupt processing has been started after this transfer processing has been completed.

[0004] For this reason, it is not possible to start an interrupt process that requires a quick response as soon as it occurs, and it is not possible to process the interrupt process promptly. further,
If the interrupt handling routine makes a cache miss,
Since the transfer of the instruction code from the main storage device 103 to the cache memory 102 is required again, more time is required for the interrupt processing, and the CPU 101 is in a stalled state during this time, and the processing capability is reduced.

[0005]

As described above,
In a conventional information processing system having a cache memory, during a refill operation due to a cache miss, the CP
U was in a stalled state and could not perform interrupt processing. For this reason, it has been difficult to perform interrupt processing quickly. Furthermore, when the instruction code for performing the interrupt process has a cache miss, the stall time of the CPU becomes longer, causing a problem that the processing capability of the CPU is reduced.

Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide an instruction memory circuit which reduces the stall time of a CPU and contributes to an improvement in processing performance, and an instruction memory circuit for the same. It is an object of the present invention to provide an information processing system including:

[0007]

In order to achieve the above object, a first means for solving the problem is to store a part of an instruction code stored in a main storage device, and to store the stored instruction code during operation. A fixed area memory for holding codes, a cache memory for storing instruction codes stored in the main storage device other than the instruction codes stored in the fixed storage area from the main storage device, and before operation starts, Transfers and stores an instruction code from the main storage device to the fixed area memory.During operation, receives a read address for reading the instruction code, and stores the instruction code stored in the fixed area memory or the cache memory. A cache controller for controlling a refill operation of the cache memory at the time of reading and a cache miss, and decoding the read address; A decoder for outputting a decoding result specifying the fixed area memory or the cache memory to be accessed, and a selector for receiving an output of the decoder and selecting an instruction code read from the fixed area memory or the cache memory And characterized in that:

[0008] The second means is the first means,
The fixed area memory stores an instruction code of an interrupt processing routine.

The third means includes an instruction memory circuit of the first or second means, and a C for reading and executing an instruction code from the fixed area memory or the cache memory.
It has a PU and a main storage device for storing instruction codes stored in the fixed area memory and the cache memory.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an information processing system including an instruction memory circuit according to one embodiment of the present invention.

Referring to FIG. 1, an instruction memory circuit includes a fixed area memory 1, a cache memory 2, a cache controller 3, a decoder 4 and a selector 5. The instruction memory circuit and a CPU 6 serving as a control center of the system.
The information processing system is provided with a main storage device 7 for storing instruction codes to be executed and processed by this system.

The fixed area memory 1 allocates a partial space, for example, 1/8 of the entire instruction space of instruction codes stored in the main storage device 7 and executed and processed in the information processing system. For example, all or a part of an instruction code of an interruption routine for executing an interruption process is stored. Therefore, the fixed area memory 1
Assuming that the number of bits of a program counter (not shown) for providing a read address of the fixed area memory 1 and the cache memory 2 included in the CPU 6 is, for example, 10 bits, the value of the upper three bits of the value of the address counter is, for example, " 0 ”is allocated as a memory space.
In the fixed area memory 1, an instruction code read from the main storage device 7 and given through the cache controller 3 is written based on an address given from the cache memory controller 3, and the written instruction code is stored in the cache memory controller 3. 3 and is output to the selector 5 based on the address given from the selector 3.
The write operation of the fixed area memory 1 is performed after the power is turned on and before the execution of the instruction code is started. During the operation of the system, the write operation is not performed, and the stored contents are retained without being rewritten.

In the cache memory 2, instruction codes stored in the main memory 7 and not stored in the fixed area memory 1 are transferred from the main memory 7 and stored. Writing and reading are performed in the cache memory 2 based on the address given from the cache controller 3, and the read instruction code is output to the selector 5.

The cache controller 3 receives the value of the program counter of the CPU 6, accesses the fixed area memory 1 with this value, calculates the refill address of the cache memory 2 based on the program counter value, and calculates the calculated address. According to the cache memory 2
Refill. The cache controller 3 gives a read request and a read address to the main storage device 7 at the start of operation after the power is turned on, thereby reading an instruction code stored in the fixed area memory 1 from the main storage device 7 and reading the read instruction. The code is written to the fixed area memory 1 according to the generated address. Cache controller 3
Determines a cache hit / miss by the cache hit / miss determination circuit 8 based on the value of the program counter provided from the CPU 6 and supplies a hit / miss signal (hitmiss) of the determination result to the CPU 6. When the cache memory 2 is accessed according to the value of (1) and a miss is made, a read request and a read address are given to the main storage device 7, whereby the missed instruction code is read from the main storage device 7, and the read instruction code is read. , And writes it to the cache memory 2 according to the calculated refill address. The cache controller 3 controls the transfer of the instruction code by the state machine 9.

The decoder 4 receives the value of the program counter provided from the CPU 6 and decodes this value.
The selector 5 is switched and controlled according to the decoding result. As described above, the access address of the fixed area memory 1 is, for example, the upper 3 bits of the 10-bit address counter value.
When the bit value is assigned to "0", the decoding result is, for example, "1" when the upper three bits of the program counter value are "0", and otherwise, the decoding result is "0".

The selector 5 selects an instruction code output from the fixed area memory 1 or the cache memory 2 based on the decoding result given from the decoder 4 and
Give to. That is, the selector 5 selects the instruction code output from the fixed area memory 1 when the decoding result “1” is provided, and provides the selected instruction code to the CPU 6. The output instruction code is selected and given to the CPU 6.

In such a configuration, after the system is powered on, for example, all or a part of the interrupt routine stored in the main storage device 7 (according to the storage capacity of the fixed area memory 1) is stored in the fixed area memory 1 And stored based on the address generated by the cache controller 3.

Thereafter, the CPU 6 fetches an instruction code based on the value of the program counter in order to execute a program execution process. When the instruction code to be fetched exists in the cache memory 2 and a cache hit occurs, the instruction code is given from the cache memory 2 to the CPU 6 via the selector 5 and fetched, and the instruction code is sequentially executed. . On the other hand, when a cache miss occurs in the instruction code fetch operation, the missed instruction code is transferred from the main storage device 7 to the cache memory 2 under the control of the cache controller 3 and stored therein. It is given to the CPU 6 via the unit 5 and fetched. While the instruction code is being transferred from the main storage device 7 to the cache memory 2, the CPU 6 is in a stalled state.

As described above, when an interrupt process occurs while the instruction code is transferred from the main storage device 7 to the cache memory 2 due to the cache miss, the C
The PU 6 changes the value of the program counter to a value for fetching the instruction code of the interrupt routine in order to branch to the interrupt routine to execute the interrupt processing. The changed value of the program counter is given to the cache controller 3, the fixed area memory 1 is accessed based on this value, and the instruction code of the interrupt routine is read from the fixed area memory 1 to the selector 5. On the other hand, the value of the program counter is decoded by the decoder 4, and the decoding result of “1” is given to the selector 5. As a result, the instruction code read from the fixed area memory 1 is selected by the selector 5, and the selected instruction code is given to the CPU 6 and fetched. As described above, the operation of transferring the instruction code from the main storage device 7 to the cache memory 2 and the operation of fetching the instruction code from the fixed area memory 1 are performed in parallel. The instruction code has not been transferred from the main storage device 7 to the cache memory 2 and C
Even when an interrupt process occurs when the PU 6 is not stalled, the instruction code is fetched from the fixed area memory 1 to the CPU 4 in the same manner as described above.

When the interrupt processing is executed according to the instruction code given to the CPU 6 and the processing is terminated, the value of the program counter is returned to the value before the change. At this point, if the transfer operation to the cache memory 2 has been completed, the programs are sequentially executed based on the value of the program counter before the change, while if the transfer has not been completed, the transfer is completed. Until the termination, the CPU 6 is in a stalled state.

Therefore, in the above embodiment, the interrupt routine stored in the fixed area memory 1 can be executed while the refill operation of the cache memory 2 is performed at the time of a cache miss, and the interrupt processing can be performed. It can be executed quickly, and the stall time of the CPU 6 due to a cache miss can be reduced.
6 can be improved.

Here, assuming that the time during which the CPU is stalled due to a cache miss is T, the probability of a cache miss is average r, and the number of steps of the instruction code to be executed is S, the time during which the CPU processes the instruction code The stall time t1 is expressed by the following equation.

[0024]

T1 = SrT (1) On the other hand, when the fixed area memory is provided as in the above embodiment, the ratio of the area of the fixed area memory to the entire instruction space is A (0 ≦ A ≦ 1). Then, the stall time t2 while the CPU processes the instruction code is expressed by the following equation.

[0025]

T2 = S (1-A) rT = SrT-SArT (2) As is apparent from the above equations (1) and (2), the stall time t2 (equation (2)) is the stall time t1. It is smaller than (Equation (1)) by SArT. Therefore,
By providing the fixed area memory, the stall time of the CPU is reduced, and the stall time can be shortened as the ratio A of the fixed area increases. On the other hand, if the ratio A of the fixed area is increased, the circuit size is increased and the cost is increased, which is a trade-off with the stall time.

FIG. 2 is a block diagram showing an embodiment when the instruction memory circuit shown in FIG. 1 and an information processing system including this instruction memory circuit are implemented as an LSI. In FIG. 2, an LSI 21 of the information processing system is integrated into one chip, and a processor module (CRISC) 22 and an MMU
A plurality of modules including a module 23;
A main storage device (SDRAM) 24 is provided outside the LSI 21 as an externally connected memory. The processor module 22 includes a plurality of sub-modules including an rcache module 25, an rcore module 26 serving as a core of the CPU, and a print server module 27 for controlling interrupt processing. The MMU module 23 arbitrates access requests of other modules included in the CRISC 22 and the LSI 21 and
It functions as a module for controlling access to the H.24.

FIG. 3 is a block diagram showing an embodiment of the rcache module 25 shown in FIG. 3, the rcache module 25 includes the fixed area memory 1, the cache memory 2, the cache controller 3, the decoder 4, and the selector 5 shown in FIG. 1. The fixed area memory 1 is, for example, a memory of 32 bits × 2048 words. The cache memory 2 is composed of a memory of, for example, 32 bits × 512 words, and the decoder 4 is, for example, an NA for inputting the upper 3 bits of a program counter.
It is composed of an ND gate. The rcache module 25 compares the tag address output from the tag memory 31 accessed by the partial value of the program counter value with the partial value of the program counter value by the comparator 32, and determines a cache hit / miss. The resulting hit / miss signal (hitmiss) is output.

In the above embodiment, the instruction code stored in the fixed area memory 1 has been described as the instruction code of the interrupt routine. However, the instruction code stored in the fixed area memory 1 is replaced with the instruction code of the interrupt routine. The present invention is not limited to this. For example, even if an instruction code for monitoring the status of a module other than the CPU 6 is stored, the same effect as the above embodiment can be obtained.

[0029]

As described above, according to the present invention, the instruction memory space of the main memory is divided into the fixed area memory and the cache memory, so that the CPU stall time due to a cache miss can be reduced. , CPU
Can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an information processing system including an instruction memory circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment when the instruction memory circuit shown in FIG. 1 and an information processing system including the instruction memory circuit are formed into an LSI.

FIG. 3 is a block diagram showing a configuration of an rcache module shown in FIG. 2;

FIG. 4 is a diagram showing a configuration of a conventional information processing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Fixed area memory 2 Cache memory 3 Cache controller 4 Decoder 5 Selector 6 CPU 7 Main storage device 8 Cache hit / miss judgment circuit 9 State machine 21 LSI 22 Processor module (CRISC) 23 MMU module 24 Main storage device (SDRAM) 25 rcache module 26 rcore module 27 printcomp module 31 tag memory 32 comparator

Claims (3)

[Claims] 1. A fixed area memory for storing a part of an instruction code stored in a main storage device and holding the stored instruction code during operation, and a command stored in the fixed area memory from the main storage device. A cache memory in which an instruction code stored in the main storage device other than the instruction code is stored; and before starting operation, transfer and store the instruction code from the main storage device to the fixed area memory; A cache controller that receives a read address for reading an instruction code, reads an instruction code stored in the fixed area memory or the cache memory, and controls a refill operation of the cache memory at the time of a cache miss; To decode the fixed area memory or the cache memory to be accessed. An instruction memory circuit, comprising: a decoder that outputs a code result; and a selector that receives an output of the decoder and selects an instruction code read from the fixed area memory or the cache memory. 2. The instruction memory circuit according to claim 1, wherein said fixed area memory stores an instruction code of an interrupt processing routine. 3. The instruction memory circuit according to claim 1 or 2, a CPU that reads and executes an instruction code from the fixed area memory or the cache memory, and is stored in the fixed area memory and the cache memory. An information processing system, comprising: a main storage device for storing an instruction code.