JP2000357090A - Microcomputer and cache control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten access time with instruction fetch to a main memory in condition branching instruction execution time without providing a complicated branch predicting mechanism in a CPU. SOLUTION: This device has a CPU 12 which incorporates the branch predicting mechanism for shortening time for access to a main memory 18 when a cache error occurs because of a condition branching instruction, a cache memory 10 to be the execution object of instruction fetch due to the CPU 12 at ordinary time, a branch establishment prefetch queue 14 to be the execution object of instruction fetch due to the CPU 12 when branch is established, a branch non-establishment prefetch queue 16 to be the execution object of instruction fetch due to the CPU 12 when branch is not established, a predecoder 22 provided outside the CPU 12 for judging the branching instruction and a memory controller 20 having an address generating function for memory access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control technique for a microcomputer, and more particularly to a technique for reducing the access time of a conditional branch instruction execution time associated with an instruction fetch to a main memory without providing a complicated branch prediction mechanism in a CPU. The present invention relates to a microcomputer and a cache control method for improving performance by simultaneously avoiding complication of a circuit configuration.

[0002]

2. Description of the Related Art In a conventional memory control device of an information processing device having a hierarchical structure of an instruction cache, an instruction prefetch buffer, and a main memory, a prefetched memory block is accessed last (Most R).
The newly used memory block is a memory block at an address next to a memory block (consisting of a predetermined number of words). For example, assuming blocks in the memory ordered as a set according to the address, when accessing the memory block Li, the next memory block Li + 1 exists in the instruction cache and the instruction prefetch buffer due to locality of the behavior of the normal program. If not, the memory block Li + 1 is prefetched from the main memory.

However, in the conventional memory control device, if a branch instruction is included in an instruction executed by the CPU, a prefetched instruction may be wasted. That is, a copy of the instruction at the branch destination address
Is not present in the instruction cache memory and is not present in the instruction prefetch buffer, it is necessary to newly read (read) a memory block including the instruction at the address from the main memory, and the instruction which has already been prefetched is required. Is wasted. The processing performance of a high-speed processor having a cache memory depends on a high hit rate for the cache memory, and there is a problem that the processing performance may be reduced when executing a branch instruction. Also, while the memory controller is prefetching instructions from main memory, the CP
When a request for a branch destination instruction comes from U, the ongoing memory read operation must be interrupted and the memory block containing the branch destination instruction must be read from the main memory. However, there is a problem in that the time required until the memory control device has no prefetch function is longer.

As a prior art for solving such a problem, for example, Japanese Patent Application Laid-Open No. 8-28691 is disclosed.
There is one described in Japanese Patent Publication No. That is, the prior art
Decoding means for detecting a branch instruction to be transferred to the cache memory and generating and outputting a branch destination address is provided at the preceding stage of the cache memory, and the address of the next memory block to be prefetched is determined based on the output of the decoding means. A memory control device of an information processing device, comprising: a decoder for receiving an output of a selector for selecting and outputting one of an output of a main memory and an output of an instruction prefetch buffer; When an instruction required by the CPU is not present in the instruction cache memory and is transferred from the main memory or the instruction prefetch buffer to the instruction cache memory, the instruction being transferred is input and decoded. Control means outputs from the decoding means. When the branch instruction detection signal to be activated is in the active state, the address of the memory block including the branch destination address is read from the main memory as the address of the memory block to be prefetched next, and the branch output from the decoding means during the memory block transfer. It is disclosed that when an instruction detection signal is in an inactive state, an address of a memory block next to a transferred memory block is read from a main memory as an address of a memory block to be prefetched next. In such a conventional technique, an instruction being transferred to the instruction cache memory is decoded, and if there is a branch instruction, the branch destination instruction is prefetched, thereby improving the prefetch efficiency and improving the processing performance. When the CPU executes the instruction transferred to the instruction cache memory, the memory block including the branch destination address is already stored in the prefetch buffer, so that it is not necessary to read the memory block from the main memory. The effect is described that a reduction in the processing performance in the case of can be suppressed.

[0005]

However, the prior art has the following problems. First, a first problem is that a logic circuit for executing branch prediction and a branch target cache for storing the execution history of a branch instruction are required, and many resources are required. Also the second
The problem is that, in the prefetch operation of the CPU having the conventional branch prediction mechanism, the memory controller executes the prefetch sequentially based on the address of the instruction sequence on the branch prediction side, and the prefetched data is written to the cache memory. Therefore, if the branch prediction fails, there is a high possibility that a cache miss occurs after the execution of the conditional branch instruction. The third problem is that
If a cache mishit occurs after the execution of a conditional branch instruction, a refill time of the cache from the main memory is required for the instruction sequence on the side where the conditional branch has failed, and the execution speed decreases. And the fourth problem is that
If a cache miss occurs after execution of a conditional branch instruction and the prediction of the conditional branch fails, the prefetch operation fetches originally unnecessary data, and the original cache line is destroyed when stored in the cache. As a result, the cache hit rate is reduced, and the performance is further degraded.

The present invention has been made in view of such a problem, and an object of the present invention is to accompany the instruction fetch of the conditional branch instruction execution time to the main memory without providing a complicated branch prediction mechanism in the CPU. It is an object of the present invention to provide a microcomputer and a cache control method for shortening access time and improving performance by avoiding complication of a circuit configuration.

[0007]

The gist of the present invention is to reduce the access time associated with the instruction fetch of the conditional branch instruction execution time from the main memory without providing a complicated branch prediction mechanism in the CPU. At the same time, a microcomputer for improving the performance by avoiding the complexity of the circuit configuration, the CPU having a built-in branch prediction mechanism for shortening the access time to the main memory when a cache miss occurs due to a conditional branch instruction And the CPU at normal times
A cache memory to be subjected to the instruction fetch of
A branch taken prefetch queue to be executed by the CPU when the branch is taken, a branch taken prefetch queue to be executed by the CPU when the branch is not taken, and a branch instruction provided outside the CPU are determined. A microcomputer includes a predecoder and a memory controller having a memory access address generation function. Claim 2
SUMMARY OF THE INVENTION The gist of the invention described in (1) is to reduce the access time associated with the instruction fetch to the main memory of the conditional branch instruction execution time without providing a complicated branch prediction mechanism in the CPU, and at the same time, to avoid the complexity of the circuit configuration and improve the performance. A microcomputer having a built-in branch prediction mechanism for shortening access time to a main memory when a cache miss occurs due to a conditional branch instruction; A cache memory to be executed, a branch taken prefetch queue to be executed by the CPU when the branch is taken, a branch taken prefetch queue to be executed by the CPU when the branch is not taken, and: Break the data of the other prefetch queue that was not targeted for execution A microcomputer including a branch non-use-side prefetch cache memory for storing without storing the data, a predecoder provided outside the CPU for determining a branch instruction, and a memory controller having a memory access address generation function. Exist. The gist of the invention according to claim 3 is that the pre-decoder comprises:
It is configured to control data transfer from the main memory to the branch taken prefetch queue and / or the branch taken prefetch queue, which are two prefetch queues on the branch taken side and / or the branch not taken side. A microcomputer according to claim 1 or 2. The gist of the invention described in claim 4 is that, when a cache miss occurs in the instruction fetch, the predecoder determines a branch instruction from the main memory based on fetch data held in a prefetch buffer, Said cache memory,
3. The microcomputer according to claim 1, wherein the microcomputer is configured to determine which one of the branch taken prefetch queue and the branch not taken prefetch queue is to transfer the fetch data. The gist of the invention described in claim 5 is that the CP
U fetches a branch instruction in the cache memory, and then determines which of the branch taken prefetch queue and the branch not taken prefetch queue is to be accessed according to a result of the execution of the branch instruction, and 5. The microcomputer according to claim 4, wherein the microcomputer is configured to execute a fetch process. The gist of the invention described in claim 6 is to reduce the access time associated with the instruction fetch to the main memory for the execution time of the conditional branch instruction without providing a complicated branch prediction mechanism in the CPU, and to increase the complexity of the circuit configuration. A cache control method for avoiding and improving performance, comprising: controlling a CPU to execute a branch prediction process to reduce access time to a main memory when a cache miss occurs due to a conditional branch instruction; A step of managing a cache memory which is an execution target of the instruction fetch of the CPU in a normal state; a step of managing a branch taken prefetch queue which is an execution target of the CPU instruction fetch when a branch is taken; Managing a branch not-taken prefetch queue to be executed, and providing the queue outside the CPU. A step of managing the predecoder is to determine branch instruction resides in cache control method characterized by comprising the step of managing a memory controller having an address generation function of the memory access. The gist of the invention described in claim 7 is that
A cache control method for reducing the access time associated with the instruction fetch to the main memory of the conditional branch instruction execution time without providing a complicated branch prediction mechanism in the PU, and at the same time, avoiding a complicated circuit configuration and improving the performance. hand,
Controlling the CPU to execute a branch prediction process in order to reduce the access time to the main memory when a cache miss occurs due to the conditional branch instruction;
A step of managing a cache memory as an execution target of the instruction fetch of U; a step of managing a branch taken prefetch queue as an execution target of the instruction fetch of the CPU when the branch is taken; and the execution of the instruction fetch of the CPU when the branch is not taken. A step of managing a target branch unsatisfied prefetch queue, and a step of managing a branch non-use side prefetch cache memory that stores data of the other prefetch queue that has not been subjected to the instruction fetch of the CPU without discarding the same. A cache control method including a step of managing a predecoder provided outside the CPU and determining a branch instruction, and a step of managing a memory controller having a memory access address generation function. The gist of the invention described in claim 8 is:
The predecoder is configured to control data transfer from the main memory to the branch taken prefetch queue and / or the branch not taken prefetch queue, which are two prefetch queues on the branch taken side and / or the branch not taken side. The cache control method according to claim 6 or 7, wherein The gist of the invention described in claim 9 is that the step of managing the pre-decoder includes, when a cache miss occurs in the instruction fetch, executing a branch instruction from the main memory based on fetch data held in a prefetch buffer. 8. The cache according to claim 6, further comprising: determining which of the cache memory, the branch taken prefetch queue, and the branch not taken prefetch queue the fetch data is to be transferred to. 8. It lies in the control method. The gist of the invention according to claim 10 is that the step of controlling the CPU to execute the branch prediction processing includes, after fetching a branch instruction in the cache memory, the branch taken prefetch according to a result of the execution of the branch instruction. 10. The cache control method according to claim 9, further comprising determining which one of a queue and the branch failure prefetch queue is to be accessed, and executing a process of loading the fetch data into the CPU. The gist of the invention described in claim 11 is that the memory controller executes a prefetch of an instruction access from the main memory before executing the instruction, and normally stores data in the cache memory;
The PU fetches an instruction from the cache memory, executes a predecode of the prefetched instruction to determine a branch instruction and a conditional branch instruction as other instructions, and if the predecode result is a branch instruction, the predecoder jumps. Calculating a destination address, and when there is no data in the cache memory, the predecoder stores the prefetch data of the jump address from the main memory in the cache memory, fetches an instruction from the cache memory, and When the decoding result is a conditional branch instruction, the predecoder calculates the jump address, and when no data exists in the cache memory, stores the prefetch data of the jump address from the main memory in the branch taken prefetch queue. And
A step of simultaneously executing a sequential instruction prefetch when the branch is not taken and storing the same in the branch unsatisfied prefetch queue; The instruction fetch is executed from the prefetch queue that matches the judgment, the fetch data at the time of execution of the instruction fetch is stored in the cache memory, and the data in the other prefetch queue, the prefetch queue in which the instruction fetch has not been executed, is discarded. 7. The cache control method according to claim 6, comprising a step. The gist of the present invention is that the memory controller executes prefetch of an instruction access from the main memory to store data in the cache memory before executing the instruction, and stores the data in the cache memory.
Fetching an instruction from the cache memory, performing pre-decoding of the prefetched instruction, and distinguishing a branch instruction and a conditional branch instruction from other instructions;
U fetches an instruction from the cache memory and executes predecoding of the prefetched instruction to determine a branch instruction and a conditional branch instruction as other instructions. A jump address is calculated, and based on the calculation result, when data does not exist in the cache memory, prefetch data of the jump address is stored in the cache memory from the main memory. In the case of an instruction, a jump address is calculated, and if no data exists in the cache memory, prefetch data of the jump address is stored in the branch taken prefetch queue from the main memory. Prefetch is also executed immediately after the branch The step of storing in a taken prefetch queue and the two prefetch queues of a branch taken side and a branch not taken side execute an instruction fetch from a prefetch queue that matches the branch determination at the time of branch determination of branch instruction execution, and fetch data into the cache memory. And storing the data in the other prefetch queue not used for instruction fetch in the branch non-use side prefetch cache memory without discarding the same conditional branch instruction again when the cache memory is used. 8. The cache control method according to claim 7, further comprising the step of executing the instruction stored in the branch non-use side prefetch cache memory when executing an instruction sequence not present in the cache memory. Exist.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A feature of each embodiment described below is that a branch prediction mechanism is incorporated in a CPU in order to reduce access time to a main memory when a cache miss occurs due to a conditional branch instruction. This eliminates the need for a high-speed branch prediction mechanism such as an existing CPU that determines the access direction of the main memory after a conditional branch instruction, and eliminates the need for a RAM for storing branch prediction information for each conditional branch instruction. Prefetch queue (branch taken prefetch queue, branch not taken prefetch queue) on the branch taken side and branch not taken side, a predecoder provided outside the CPU to determine a branch instruction, and an address of memory access The hardware controller is simplified by reducing essential components to three memory controllers with a generation function. As a result, the performance of the microcomputer can be improved at low cost, and the data in the cache memory is destroyed. That is, unnecessary prefetch from the main memory to the cache memory due to the branch instruction and the conditional branch instruction does not occur. As a result, it is possible to improve the performance of the microcomputer represented by the improvement of the hit rate of the cache memory. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a functional block diagram for explaining a microcomputer 100 according to the embodiment. In FIG. 1, 1
0 is a cache memory, 12 is a CPU, 14 is a branch taken prefetch queue, 16 is a branch not taken prefetch queue, 18 is a main memory, 20 is a memory controller, 22 is a predecoder, 26 is a prefetch buffer, and 28 is a first internal data bus. , 30 indicate a second internal data bus, and 100 indicates a microcomputer. Referring to FIG. 1, in the present embodiment, CPU 1
As means for executing the second instruction fetch, a normal cache memory 10, a branch taken prefetch queue 14, and a branch not taken prefetch queue 16 are provided. The first internal data bus 28 has a cache memory 1
0, a CPU 12, a branch taken prefetch queue 14, and a branch not taken prefetch queue 16. The cache memory 10, the branch taken prefetch queue 14, the branch not taken prefetch queue 16, and the prefetch buffer 26 are connected to the second internal data bus 30.

The predecoder 22 is connected to the memory controller 20 and the prefetch buffer 26, and is provided with two prefetch queues (branch prefetch queue 1) on the branch taken side and the branch not taken side from the main memory 18.
4. A function for controlling data transfer to the branch not taken prefetch queue 16). When a cache miss occurs in the instruction fetch, the branch instruction is determined from the main memory 18 based on the fetch data held in the prefetch buffer 26, It has a function of determining where in the cache memory 10, the branch taken prefetch queue 14, and the branch not taken prefetch queue 16 the fetch data is transferred via the second internal data bus 30.

After fetching a branch instruction in the cache memory 10, the CPU 12 determines which of the branch taken prefetch queue 14 and the branch not taken prefetch queue 16 is to be accessed according to the result of the instruction execution. It has the function of executing the capture process of

Next, the operation of the microcomputer (cache control method) will be described with reference to FIG. First,
Before the instruction is executed, the memory controller 20 executes a prefetch of the instruction access from the main memory 18 and usually stores the data in the cache memory 10.

In response, CPU 12 fetches an instruction from cache memory 10 and executes predecoding of the prefetched instruction to determine a branch instruction and a conditional branch instruction as other instructions.

At this time, when the predecode result is a branch instruction, the predecoder 22 calculates the jump address, while when no data exists in the cache memory 10, the jump address of the jump address is read from the main memory 18. The prefetch data is stored in the cache memory 10.

Subsequently, the CPU 12 sets the cache memory 1
Fetch the instruction from 0. If the predecode result is a conditional branch instruction, the predecoder 22 calculates the jump address, while if there is no data in the cache memory 10, the prefetch data of the jump address is taken from the main memory 18 as a branch. The data is stored in the prefetch queue 14. Immediately after this, a sequential instruction prefetch when the branch is not taken is also executed and stored in the branch not taken prefetch queue 16.

Subsequently, at the time of branch determination for execution of a branch instruction, data of two prefetch queues (branch-taken prefetch queue 14 and branch-not-taken prefetch queue 16) on the branch-taken side and the branch-not-taken side are stored in a prefetch queue matching the branch determination. That is, the instruction fetch is executed from one of the branch taken prefetch queue 14 and the branch not taken prefetch queue 16 to store the fetch data at that time in the cache memory 10, and at the same time, the other prefetch queue, that is, the instruction fetch is executed. The data of the prefetch queue that is not performed is discarded.

As described above, according to the first embodiment, the following effects can be obtained. First, the first effect is
Without providing a complicated branch prediction mechanism in the CPU 12, it is possible to shorten the access time of the conditional branch instruction execution time associated with the instruction fetch to the main memory 18 and improve the performance without complicating the circuit configuration. That is, the branch prediction mechanism is built in the CPU 12 to reduce the access time to the main memory 18 when a cache miss occurs due to the conditional branch instruction, so that the access direction of the main memory 18 after the conditional branch instruction is determined. Existing CPU
12, a high-speed branch prediction mechanism such as 12 is not required, and a RAM for storing branch prediction information of each conditional branch instruction is not required. As a result, a large cost reduction can be realized.

The second effect is that two prefetch queues (a branch taken prefetch queue 14 and a branch not taken prefetch queue 1) are provided on the branch taken side and the branch not taken side.
6) The hardware can be simplified by reducing the three essential components of the pre-decoder 22 provided outside the CPU 12 for determining a branch instruction and the memory controller 20 having a memory access address generation function. As a result, the performance of the microcomputer 100 can be improved at low cost.

The third effect is that the cache memory 1
As a result of destroying the data of 0, that is, preventing the unnecessary prefetch from the main memory 18 to the cache memory 10 due to the branch instruction and the conditional branch instruction, the microscopic data represented by the improvement in the hit rate of the cache memory 10 is obtained. That is, the performance of the computer 100 can be improved.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a functional block diagram for explaining a microcomputer 100 according to the embodiment. In FIG. 2, 1
0 is a cache memory, 12 is a CPU, 14 is a branch taken prefetch queue, 16 is a branch not taken prefetch queue, 18 is a main memory, 20 is a memory controller, 22 is a predecoder, 24 is a branch non-use side prefetch cache memory, and 26 is Prefetch buffer,
28 is a first internal data bus, 30 is a second internal data bus, and 100 is a microcomputer. The same portions as those already described in the first embodiment are denoted by the same reference numerals, and duplicate description will be omitted. Referring to FIG. 2, in the present embodiment,
The above-described cache memory 10, branch taken prefetch queue 14, and branch not taken prefetch queue 16
In addition, a branch non-use side prefetch cache memory 24 for storing data of the other unused prefetch queue without discarding is connected to the first internal data bus 28, and the same conditional branch instruction is stored in the cache memory 10 again. When executing at the time of use and not currently in the cache memory 10, that is, when executing the instruction sequence on the side not used last time,
It is characterized in that the instructions stored in the branch non-use side prefetch cache memory 24 are executed.

In the present embodiment, the operation of the predecoder 22 is the same as in the first embodiment. Before executing the instruction, the memory controller 20 prefetches the instruction access from the main memory 18 and usually stores the data in the cache memory 10. Subsequently, the CPU 12 fetches an instruction from the cache memory 10, executes predecoding of the prefetched instruction, and determines a branch instruction and a conditional branch instruction as other instructions.

Subsequently, the predecoder 22 calculates the jump destination address when the predecode result is a branch instruction. As a result, when there is no data in the cache memory 10, the predecoder 22 calculates the jump address from the main memory 18. The prefetch data is stored in the cache memory 10. On the other hand, when the predecode result is a conditional branch instruction, the jump destination address is calculated.
If there is no data at 0, the prefetch data at the jump address from the main memory 18 is stored in the branch taken prefetch queue 14. Further, the predecoder 2
No. 2 also performs the sequential instruction prefetch immediately after the branch is not taken and stores it in the branch not taken prefetch queue 16.

The two prefetch queues (the branch taken prefetch queue 14 and the branch taken prefetch queue 14,
The data in the branch failure prefetch queue 16) is a prefetch queue that matches the branch determination at the time of branch determination of branch instruction execution, that is, the branch taken prefetch queue 14
Alternatively, the operation from executing the instruction fetch from any one of the branch failure prefetch queues 16 and storing the fetch data in the cache memory 10 is the same as that of the first embodiment.

Subsequently, the other prefetch queue not used for instruction fetch, that is, the branch taken prefetch queue 14 or the branch not taken prefetch queue 1
6 without discarding the data of the prefetch queue which is not the prefetch queue used for the instruction fetch,
It is stored in the branch non-use side prefetch cache memory 24.

Subsequently, the same conditional branch instruction is executed again when the cache memory 10 is used, and when the instruction sequence which is not currently in the cache memory 10, ie, the instruction sequence not used last time is executed, the branch non-use side prefetch cache is executed. The instruction stored in the memory 24 is executed.

As described above, according to the second embodiment, even if a conditional branch instruction is present at the time of a cache hit, the memory access time can be shortened.
There is an effect that the execution time can be further reduced as compared with the first embodiment which is effective only for the branch instruction existing at the time of instruction fetch at the time of a cache miss.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0028]

Since the present invention is configured as described above, the following effects can be obtained. The first effect is that C
An object of the present invention is to provide a PU that does not have a complicated branch prediction mechanism, can shorten the access time of the conditional branch instruction execution time associated with the instruction fetch to the main memory, and can improve the performance without complicating the circuit configuration. That is, by incorporating a branch prediction mechanism in the CPU to reduce the access time to the main memory when a cache miss occurs due to a conditional branch instruction, the existing CPU that determines the main memory access direction after the conditional branch instruction Such a high-speed branch prediction mechanism is not required, and a RAM for storing branch prediction information of each conditional branch instruction is not required. As a result, a large cost reduction can be realized. The second effect is essential to three prefetch queues on the branch taken side and the branch not taken side, a predecoder provided outside the CPU to determine a branch instruction, and a memory controller having a memory access address generation function. As a result, hardware can be simplified by reducing the number of components, so that the performance of the microcomputer can be improved at low cost. The third effect is that the data in the cache memory is destroyed, that is, unnecessary prefetch from the main memory to the cache due to the branch instruction and the conditional branch instruction can be prevented. The performance of the microcomputer to be improved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram for explaining a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram for explaining a microcomputer according to a second embodiment of the present invention.

[Description of Signs] 10 cache memory 12 CPU 14 branch taken prefetch queue 16 branch not taken prefetch queue 18 main memory 20 memory controller 22 predecoder 24 branch non-use side prefetch cache memory 26 prefetch buffer 28 ... first internal data bus 30 ... second internal data bus 100 ... microcomputer

Claims (12)

[Claims] 1. A method for shortening an access time associated with an instruction fetch to a main memory during a conditional branch instruction execution time without providing a complicated branch prediction mechanism in a CPU, and at the same time, improving a performance by avoiding a complicated circuit configuration. A microcomputer comprising: a CPU having a branch prediction mechanism for shortening access time to a main memory when a cache miss occurs due to a conditional branch instruction; and a cache to which an instruction fetch of the CPU is normally executed. A memory; a branch taken prefetch queue to be executed by the CPU when the branch is taken; a branch taken prefetch queue to be executed by the CPU when the branch is not taken; and a branch instruction provided outside the CPU. Pre-decoder to determine memory access and memory access address generation function A microcomputer comprising a memory controller having the following. 2. The method according to claim 1, wherein the CPU is not provided with a complicated branch prediction mechanism, so that the access time associated with the instruction fetch to the main memory with the conditional branch instruction execution time is reduced, and the performance is improved by avoiding the complicated circuit configuration. A microcomputer comprising: a CPU having a branch prediction mechanism for shortening access time to a main memory when a cache miss occurs due to a conditional branch instruction; and a cache to which an instruction fetch of the CPU is normally executed. A memory; a branch taken prefetch queue to be executed by the CPU when the branch is taken; a branch not taken prefetch queue to be executed by the CPU when the branch is not taken; Without destroying the data in the other prefetch queue A branch unused side prefetch cache memory for storing a pre-decoder for determining a branch instruction provided outside of the CPU, a microcomputer, characterized in that it comprises a memory controller having an address generation function of the memory access. 3. The predecoder controls data transfer from the main memory to the branch taken prefetch queue and / or the branch not taken prefetch queue, which are two prefetch queues on a branch taken side and / or a branch not taken side. The microcomputer according to claim 1, wherein the microcomputer is configured as follows. 4. When a cache miss occurs in an instruction fetch, the predecoder determines a branch instruction from the main memory on the basis of fetch data held in a prefetch buffer. 3. The microcomputer according to claim 1, wherein the microcomputer is configured to determine to which of the prefetch queue and the branch failure prefetch queue the fetch data is transferred. 5. After fetching a branch instruction in the cache memory, the CPU determines which of the branch taken prefetch queue and the branch not taken prefetch queue is to be accessed according to a result of the execution of the branch instruction. 5. The microcomputer according to claim 4, wherein the microcomputer is configured to execute a process of loading the fetch data into the CPU. 6. A CPU for providing a conditional branch instruction execution time without providing a complicated branch prediction mechanism in a CPU, thereby shortening an access time associated with an instruction fetch to the main memory, and at the same time, avoiding a complicated circuit configuration and improving performance. A cache control method, comprising: controlling a CPU to execute a branch prediction process in order to reduce an access time to a main memory when a cache miss occurs due to a conditional branch instruction; Managing a cache memory to be executed by the CPU; a step of managing a branch taken prefetch queue to be executed by the CPU instruction fetch when the branch is taken; and a branch not taken by the CPU to execute the instruction fetch when the branch is not taken. Managing a prefetch queue; determining a branch instruction provided outside the CPU Cache control method characterized by comprising the steps of: managing a predecoder, a step of managing a memory controller having an address generation function of the memory access that. 7. A CPU that is not provided with a complicated branch prediction mechanism, reduces the access time of a conditional branch instruction execution time associated with an instruction fetch to a main memory, and avoids a complicated circuit configuration to improve performance. A cache control method, comprising: controlling a CPU to execute a branch prediction process in order to reduce an access time to a main memory when a cache miss occurs due to a conditional branch instruction; Managing a cache memory to be executed by the CPU, a step of managing a branch taken prefetch queue to be executed by the CPU when the branch is taken, and a branch to be executed by the CPU when the branch is not taken. A step of managing an unsuccessful prefetch queue; Managing a branch non-use side prefetch cache memory for storing data of the other prefetch queue that has not been lost without discarding; managing a predecoder provided outside the CPU for determining a branch instruction; A cache control method comprising a step of managing a memory controller having an access address generation function. 8. The predecoder controls data transfer from the main memory to the branch taken prefetch queue and / or the branch not taken prefetch queue, which are two prefetch queues on a branch taken side and / or a branch not taken side. The cache control method according to claim 6, wherein the cache control method is configured as follows. 9. A process for managing the predecoder, comprising: determining a branch instruction from the main memory based on fetch data held in a prefetch buffer when a cache miss occurs in an instruction fetch; 8. The cache control method according to claim 6, further comprising the step of determining which of the branch taken prefetch queue and the branch not taken prefetch queue is to transfer the fetch data. 10. The step of controlling the CPU to execute the branch prediction process includes fetching a branch instruction in the cache memory, and then executing the branch taken prefetch queue and the branch not taken prefetch queue in accordance with a result of the execution of the branch instruction. 10. The cache control method according to claim 9, further comprising: determining which one of the CPUs is to be accessed, and executing a process of loading the fetch data into the CPU. 11. The memory controller executes a prefetch of an instruction access from the main memory before executing an instruction, and usually stores data in the cache memory, and the CPU fetches the instruction from the cache memory. The pre-decoder executes a pre-decode of the pre-fetched instruction to determine a branch instruction and a conditional branch instruction as other instructions, and when the pre-decode result is a branch instruction, the pre-decoder performs calculation of a jump destination address; When there is no data in the memory, the predecoder stores prefetch data of a jump address from the main memory in the cache memory, fetches an instruction from the cache memory, and if the predecode result is a conditional branch instruction, Predecoder calculates jump address If no data exists in the cache memory, the prefetch data of the jump address is stored in the branch taken prefetch queue from the main memory, and a sequential instruction prefetch when the branch is not taken is also executed to execute the branch not taken. Storing the data in a prefetch queue, and, when determining a branch for execution of a branch instruction, with respect to data in two prefetch queues on a branch taken side and a branch not taken side,
The instruction fetch is executed from the prefetch queue that matches the branch determination, the fetch data at the time of execution of the instruction fetch is stored in the cache memory, and the data of the other prefetch queue, the prefetch queue in which the instruction fetch was not executed, is discarded. 7. The cache control method according to claim 6, further comprising the step of: 12. The memory controller executes instruction access prefetch from the main memory to store data in the cache memory before executing the instruction, and the CPU fetches the instruction from the cache memory and executes the prefetched instruction. Executing the pre-decoding of the instruction and determining the branch instruction and the conditional branch instruction as other instructions; and the CPU fetching the instruction from the cache memory and executing the pre-decoding of the prefetched instruction to execute the branch instruction and the conditional instruction. A branch instruction is determined to be another instruction, and the predecoder executes a calculation of a jump destination address when the predecode result is a branch instruction, and based on the calculation result, when there is no data in the cache memory. Prefetch data of the jump address from the main memory When the predecode result is a conditional branch instruction, the jump address is calculated. When no data exists in the cache memory, the prefetch data of the jump address is read from the main memory into the branch taken prefetch. Storing the instruction in a queue and immediately executing a sequential instruction prefetch when the branch is not taken, and storing the instruction in the branch unsatisfied prefetch queue. Executing an instruction fetch from the prefetch queue that coincides with the branch determination and storing the fetch data in the cache memory, and the branch non-use side without discarding the data of the other prefetch queue not used for the instruction fetch. Prefetch cache memory Storing the same conditional branch instruction again when the cache memory is used, and executing the instruction stored in the branch non-use side prefetch cache memory when executing an instruction sequence not present in the cache memory. 8. The cache control method according to claim 7, comprising: