JP2006285727A - Cache memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make an instruction code and data, which should be reside, resident in a cache memory 3 to improve a cache hit. <P>SOLUTION: This device comprises a CPU 1 for processing a program and data to operate a system, a main memory device 2 of a low speed and large capacity for housing the instruction code and data of the program, a cache memory 3 of a higher speed and a smaller capacity than those of the main memory device 2 for temporarily housing the instruction code and data, a cache memory control circuit 4 for replacing and reading the cache memory 3, and a replacement candidate control circuit 5 for eliminating an area of the instruction code and data resident in the cache memory 3 from a replacement object in replacement operation, and thus is provided with an area of the cache memory 3 where the instruction code and data to reside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

    The present invention relates to a cache memory device for performing memory access at high speed.

  A conventional general cache memory device will be briefly described. As shown in FIG. 10, the cache memory device includes a CPU 1 for processing a program and data for operating the system, a low-speed and large-capacity main storage device 2 for storing instruction codes and data of the program, The cache memory 3 has a smaller capacity than the main storage device 2 but a high speed, and a cache memory control circuit 4 for controlling these operations.

  The cache memory 3 is a kind of buffer memory for reducing the time corresponding to the waiting time when accessing the CPU 1 and the main storage device 2 and improving the processing speed. Normally, the cache memory 3 has a smaller capacity than the main storage device 2, but uses a memory capable of high-speed response to accesses from the CPU 1, and temporal locality (data read / written will be used again soon). ) And spatial locality (data near read / write data is likely to be used in the near future), and the overall system speed can be improved. To do.

  The instruction code and data are stored in the main storage device 2 in advance, but when the CPU 1 accesses an arbitrary address from the initial state (the state in which nothing is stored in the cache memory 3), the data is stored in the cache memory 3. Therefore, the first access is made to the low-speed main storage device 2. At the same time, the cache memory 3 stores the address of the main storage device 2 accessed by the CPU 1 and the instruction code and data output from the main storage device 2 based on this address. The cache memory control device 4 constantly monitors the access to the storage device executed by the CPU 1, and the cache memory control circuit 4 operates at a low speed when the same address (stored address) is accessed for the second and subsequent times. Access to the storage device 2 is stopped (no control signal is output to the main storage device 2), and the instruction code or data corresponding to the corresponding address is transferred from the high-speed cache memory 3 to the CPU 1. This reduces the time corresponding to the waiting time when the CPU 1 accesses the main storage device 2 and improves the processing speed. As described above, by having the small-capacity but high-speed cache memory 3, if the data required by the CPU 1 exists in the cache memory, the instruction code and the high-speed instruction can be transferred at high speed without accessing the low-speed main storage device 2. Data can be read and written.

  If the highest speed system is to be realized, it can be realized by making the low-speed and inexpensive main storage device 2 and the high-speed and expensive cache memory 3 the same size. However, since this is not realistic from the viewpoint of cost, the cache memory 3 is generally mounted with a smaller size than the main storage device 2.

  As described above, since the cache memory 3 is smaller in size than the main storage device 2, only a part of the data in the main storage device 2 is stored on the cache memory 3.

  As an ideal operation of the cache memory 3, it is desirable to store instruction codes and data with a high probability required by the CPU 1 in the cache memory 3 before the CPU 1 actually uses them. When there is no free space on the cache memory 3, processing is performed to replace the instruction code and data required by the CPU 1 with the instruction code and data that is considered to be least necessary. However, which instruction code or data is actually stored or replaced on the cache memory 3 depends on the replacement control circuit of the cache memory control circuit 4 and is not used as a typical control method. Methods such as the LRU (Least Recently Used) method that selects the block with the longest time as the replacement target, the Round-Robin method that changes the replacement target in order, and the random random method that is the replacement target are often used. Yes. The cache memory 3 usually has a plurality of sets of tags (information such as the address of the main memory 2 stored for each line of the cache memory 3), so that a plurality of instruction codes or data can be stored even at the same entry address. Can be stored. The number of tag sets (hereinafter referred to as ways) is called association.

    When the instruction code or data required by the CPU 1 is not stored in the cache memory 3, a replacement operation (line for transferring a new instruction code or data from the main storage device 2 to the line of the cache memory 3 from the main storage device 2. Called fetch). The line selected on the cache memory 3 is generally obtained by decoding a part of the address at which the CPU 1 accesses the main memory 2 as described in “Computer Configuration and Design” by Patterson & Hennessy. Determined. This will be described with reference to FIG. FIG. 11 is a diagram illustrating a replacement candidate way when a replacement operation is performed in the cache memory. The replacement candidate 12 when the replacement operation is performed covers all of the ways 0 to 3 and can be replaced with the way line selected by the replacement control circuit.

As described above, it is often more efficient to make necessary instruction codes and data resident in the cache memory 3. For this reason, there has been proposed a technique for prohibiting line data replacement by adding a resident flag to a flag bit in a tag on a line for a program resident in a cache memory, thereby improving the hit rate. Is disclosed. In this technique, a resident flag is provided for each line of the cache memory, and the replacement of the cache memory 3 is controlled according to the state of the resident flag by referring to the resident flag when determining a cache hit or miss.
JP-A-6-195267 Patterson & Hennessy, "Computer Configuration and Design", Nikkei BP Publishing, September 25, 1998, p421

  Such a replacement operation of the conventional cache memory 3 is performed depending on the program and the replacement control circuit of the cache memory control circuit 4 regardless of whether the instruction code or data is required to be accessed at high speed. There is no guarantee that the instruction code and the data for which high speed access is required are always stored in the cache memory 3. As a result, there is a problem that the effect of the cache memory 3 may not be obtained as expected. For example, even if a program that is not desired to be evicted is stored in any one of the ways, there is a problem that the corresponding line of the way becomes a replacement candidate according to the replacement control circuit of the cache memory control circuit 4.

  In addition, as a different method, there is a method of improving the cache hit rate (so that necessary instruction codes and data exist in the cache memory 3 as much as possible) by programming. In this case, the specification of the cache memory 3 is used. It is necessary to generate object code that takes into account and operation, and current compilers and assemblers often fail to take measures against that part. In addition, when the cache memory 3 cannot be used effectively, access to the main storage device 2 increases as a result, which not only has an influence from the viewpoint of speeding up the processing, but also the main storage device 2. Since the path to the path is frequently activated, the state change increases, resulting in an increase in power consumption.

  In the invention disclosed in Japanese Patent Laid-Open No. 6-195267, it is necessary to always refer to the resident flag line by line in the cache memory 3 for determination of cache hits and misses, so that the operation speed of the circuit can be reduced at that part. However, it is guaranteed that instruction codes and data that require high-speed access are always stored in the cache memory 3, but the performance of the cache memory 3 may not be obtained as expected. there were.

  The cache memory device of the present invention has a CPU for processing an instruction code or data including at least a resident instruction code for setting a resident area, and two or more ways for temporarily storing the instruction code or data. The cache memory includes a cache memory, a cache memory control circuit for performing replacement control and read control of the cache memory, and replacement candidate control means for setting a resident area in a predetermined area by the resident instruction code.

  The replacement candidate control means has resident area setting means for setting a resident area by the resident instruction code, and way selection means for selecting a way for performing a replacement operation.

  In addition, the way selection means is configured such that the way of the resident area candidate is uniquely determined in advance in the circuit when the resident instruction code is executed, and the way in which the resident area is excluded during the replacement operation when the resident instruction code is not executed. select.

  The predetermined resident area is a continuous line on the way selected by the way selection means.

  The resident area setting means designates a head address for determining a resident area and a size of the area. Alternatively, the resident area setting means designates a start address and an end address for determining the resident area.

  Further, the replacement candidate control means includes setting means for determining validity / invalidity of the area setting in which the instruction code or data to be resident in the cache memory is stored, and when the setting means is deactivated, The resident setting by the resident area setting means becomes invalid.

  According to the present invention, it is possible to improve the access speed to the resident instruction code and data by making the resident instruction code and data resident in a predetermined area. Also, by excluding instruction codes and data that are resident in the cache memory from replacement candidates, it becomes possible to make them resident in the cache memory, resulting in an improved cache hit rate and instruction codes and data executed by the CPU. High speed processing is achieved. Further, the state change of the data bus or the like can be reduced by reducing the access to the main storage device. As a result, a favorable effect can be expected for reduction of power consumption. In addition, since replacement candidates are excluded in order from the way determined in advance in terms of circuit, simplification of circuit resources required for mounting can also be achieved.

  FIG. 1 shows the basic configuration of the cache memory device of this embodiment. The cache memory device according to the present embodiment includes a CPU 1 that processes a program and data for operating the system, a low-speed and large-capacity main storage device 2 that stores program instruction codes and data, and a main memory. A cache memory 3 for temporarily storing instruction codes and data that is smaller and faster than the device 2, a cache memory control circuit 4 that performs replacement and read operations of the cache memory 3, and a cache memory 3 that is resident in the cache memory 3. And a replacement candidate control circuit 5 for excluding the instruction code and data areas from the replacement target during the replacement operation.

  The replacement control circuit built in the cache memory control circuit 4 performs replacement control such as LRU method, Round-Robin method, and random method at the time of replacement operation.

  Further, FIG. 2 shows a configuration diagram of the replacement candidate control circuit 5 of the present embodiment. The replacement candidate control circuit 5 according to the present embodiment compares the resident area setting register 50 for setting an area to be resident and whether or not an address output from the CPU 1 (hereinafter referred to as a CPU address) is the resident area. And a way selection circuit 54 for controlling way selection.

  In the present embodiment, when the CPU 1 executes an instruction code for setting the resident area (hereinafter referred to as resident instruction code) when setting the resident area, the CPU 1 writes the set value in the resident area setting register 50, Further, if the execution of the instruction code is a cache miss, the resident instruction code is read from the main storage device 2 and placed in the cache memory 3.

  The resident area setting register 50 includes a resident area head address register 51 for setting the head address of the area to be resident and a resident area size register 52 for setting the size of the resident area. By writing the setting values in these two registers, the head address and size for setting the resident area are determined, so the resident area is set.

  The comparator 53 compares the resident area head address of the resident area head address 51 with the resident area size of the resident area size register 52 and the CPU address, and determines whether or not the line is the same as the resident area.

  The way selection circuit 54 selects a specific way when the resident instruction code is executed based on the determination result of the comparator 53, excludes the resident area when the resident instruction code is not executed, and excludes the resident area. The way is selected according to the replacement control circuit 4.

  The replacement operation when the resident instruction code is not executed after the resident area is set in the cache memory 3 is performed by the replacement control circuit of the cache memory control circuit 4 for the area excluding the resident area.

  In other words, in the replacement operation at the time of executing the resident instruction code, an area to be resident in order from a way determined in advance in a circuit is assigned regardless of the current state of the cache memory. Further, when the resident instruction code is not executed and the replacement operation is performed, the resident area is excluded from the replacement candidates, and the replacement operation in the replacement control circuit of the cache memory control circuit 4 is performed.

  Here, the operation of the cache memory device of this embodiment will be described with reference to FIGS. 1 and 2. Here, for simplicity of explanation, the way selection circuit 54 is configured so that the association degree of the cache memory is 4, and the order of the ways to which the area to be resident is assigned is the order of ways 0, 1, 2, and 3. Describe the case.

  When a plurality of resident areas are set, it can be assumed that a plurality of resident area setting registers 50 are required. Here, the case where the number is one will be described first.

  When the CPU 1 executes the resident instruction code during program execution, the resident area setting register 50 is written. Here, since the instruction code and data before being resident are before being written to the cache memory 3, a physical resident area is not yet set. After executing the resident instruction code, the resident instruction code and data are replaced with way 0 regardless of the replacement control circuit of the cache memory control circuit 4 such as LRU method, Round-Robin method, and random method.

  After the replacement operation is completed, the end state is judged by a circuit and the setting of the resident area is reflected. When the resident area setting register 50 is set, from the next replacement, when the CPU address points to the same line as the resident area in the cache memory 3, only the way except way 0 becomes a replacement candidate. A way is selected from the way 3 by the replacement control circuit of the cache memory control circuit 4, and the replaced instruction code and data are stored on the way line.

  As described above, when the resident area is set in the way 0, the instruction code and data stored in the area where the resident setting is set in the cache memory 3 can be excluded from the replacement operation. Data can be resident in the cache memory. On the other hand, when a line other than the same line as in the resident area is pointed out, all the ways become replacement candidates.

  FIG. 3 is a diagram showing the replacement candidates in the cache memory 3. FIG. 3A shows a case where the CPU address indicates the same line as the area of way 0 for which the resident setting has already been made at the time of the replacement operation, and the way order for selecting the way to reside is way 0, 1, 2 3 is the operation when the order is 3. Since the way 0 having the resident area 11 is excluded from the replacement candidates, the replacement candidate 12 is any one of the ways 1, 2, and 3. Which of the ways 1, 2, and 3 is selected is selected according to the replacement control circuit of the cache memory control circuit 4 such as the LRU method, the Round Robin method, and the random method, except that the way 0 is not selected.

  FIG. 3B shows a case where the CPU address points to a line different from the resident area. The replacement candidate 12 may be any of the ways 0, 1, 2, and 3, and is selected depending on the replacement control circuit of the cache memory control circuit 4. In this way, it is possible to exclude the instruction code and data stored in the cache memory 3 from the normal replacement operation, and the result instruction code and data can be resident in the cache memory.

  FIG. 4 shows the flow of a program for operating the system using the cache memory device of the above embodiment. As shown in FIG. 4, the program has a resident instruction code 13 followed by a resident area 14 composed of instruction codes and data to be resident. The CPU 1 basically executes the program in order from the top, but when the resident instruction code 13 is executed in the middle, the head address and area size of the resident area are written in the resident setting register 50. In this case, no resident area is formed. After the resident instruction code 13 is executed, the program having the instruction code and data of the line to be resident is replaced with a continuous line of a way uniquely determined in advance in the cache memory. In one case, it is always replaced with way 0. After the replacement operation is completed, the setting of the resident setting register 50 is reflected and the resident area 14 is formed. Thereafter, the resident area is excluded from the candidates for replacement.

FIG. 5 shows an embodiment in which a plurality of resident areas can be set.
A resident area setting register 501 having a plurality of resident area setting registers 50 capable of setting a resident area, a comparator 531 having the same number of comparators 53 corresponding to the plurality of resident area setting registers 50, and a comparator 531 The way selection circuit 541 for selecting the way based on the determination result in FIG. The resident area setting registers 501 are provided with a plurality of resident area setting registers 50, and the same number of comparators 531 are provided corresponding to the resident area setting registers 50.

  The way selection circuit 541 selects a specific way when executing the selected resident instruction code based on the determination result of the comparator 531 and excludes the resident area during the replacement operation when the resident instruction code is not executed. The way is selected according to the replacement control circuit 4.

  The comparator 531 determines whether or not the CPU address is the resident area based on the resident area head address and the resident area size output from the resident area setting register 501, respectively. Based on the result, the way selection circuit 541 selects a replacement candidate. decide. As described above, the resident areas can be set as many as the number of registers in the resident area setting register 501.

  Next, an example in which a plurality of resident areas are set will be described based on the embodiment. FIG. 6A is a diagram illustrating an example of a method for selecting a resident way when lines overlap. In this case, when there is a resident area in way 0, a new resident area is set, and if one line overlaps with the resident area of way 0, way 1 is selected. This method has an advantage that the way selection circuit can be easily mounted. The exclusive control of the plurality of resident areas is performed by the way selection circuit 541 based on the output result of the comparator 531.

  FIG. 6B is a diagram illustrating an example in which an area to be newly resident overlaps a line in which way 0 has already been set to reside in order to efficiently use a physical area of the cache. In this case, a method may be considered in which way 1 is selected for a line for which resident setting has already been made, and way 0 is selected for a line for which resident setting has not been made. Of course, which method should be selected may be determined at the time of circuit design according to the application to be realized. Further, when a new resident area is set and the CPU address points to the same line as in the resident area, and the way 0 and 1 are already resident, the next is way 2 and the next. Becomes the order of way 3.

  FIG. 6C is a diagram illustrating an example in which the line indicated by the CPU address overlaps the resident area in all ways. In this case, the operation of the cache memory device is the same as that when the cache is turned off, and the main memory device 2 is accessed.

  In addition, in order to provide a degree of freedom for replacement of the cache, a method of limiting the number of ways that can be resident can be considered. The number of resident areas may be determined at the time of circuit design according to the application to be realized. Of course, the order of which way is selected at the time of resident setting may be any order regardless of where it starts as long as it is uniquely determined in advance.

  Next, a replacement flow of the cache memory device of the present invention will be described based on the flowchart shown in FIG.

  Processing is started in response to an access request from the CPU 1 to the main storage device 2, and the cache memory control circuit 4 first checks the contents of the tag memory (S1). It is determined whether or not it exists in the cache memory 3, that is, whether or not the cache is hit or miss (S2).

  If the instruction code or data requested for access exists in the cache memory 3 (hit), the desired instruction code or data is transferred from the cache memory 3 to the CPU 1 (S3), and this process is terminated.

  If the instruction code or data requested to be accessed does not exist in the cache memory 3 (miss), the cache memory control circuit 4 reads the instruction code or data from the main memory 2 and stores it in the cache memory 3. At this time, the next processing differs depending on whether or not an instruction code or data that is read from the main storage device 2 and stored in the cache memory 3 is resident in the cache memory 3 (S4). 4 is determined by the presence / absence of a resident instruction code 13 such as 4.

  When there is no need to make the instruction code or data resident in the cache memory 3 resident, a cache memory control circuit such as an LRU method, a round robin method, or a random method is selected from the areas excluding the resident area by the way selection circuit 54 In accordance with the replacement control circuit in step 4, the replacement operation of the selected way to the line is performed (S7).

  Next, when the instruction code or data stored in the cache memory 3 is indicated by the resident instruction code 13 to be resident in the cache memory, the way selection circuit 54 causes the LRU method, the Round Robin method, the random method, etc. Regardless of the replacement control circuit, a replacement operation is performed for the resident area on the way whose order is determined in advance (S5). After the replacement operation, the setting value of the resident area setting register 50 is reflected, and The set area is excluded from the next replacement candidates, and as a result, the place becomes a resident area (S6).

  As shown in the prior art, the control methods employed by the replacement control circuit of the cache memory control circuit 4 for determining the replacement way of the cache memory include the LRU method, the Round Robin method, and the random method. However, the present invention can be applied to any method.

  In the above embodiment, the resident area set by the cache memory device is determined by the head address and the size of the resident area, but can also be realized by setting the head address and the last address of the resident area. The embodiment is shown in FIG.

  The replacement candidate control circuit 5 shown in FIG. 8 includes a resident area setting register 50 for setting a resident area, a comparator 53 for determining whether or not the CPU address is the resident area, and a way for controlling way selection. The selection circuit 54 is configured.

  The present embodiment is characterized in that instead of the resident area size register 52 in the resident area setting register 50 of the embodiment of FIG. 2, a resident area final address register 55 that can set the final address of the resident area is replaced. is there.

  Next, how to cancel the resident setting will be described. Various methods can be considered as means for releasing the resident setting. As an example, the setting of the resident area size register 52 is set to “0” in the embodiment of FIG. 2, or the setting of the resident area final address register in the embodiment of FIG. It can be easily realized by the same method as the setting of the resident area start address register. It can also be implemented by providing means for determining whether the resident area is valid or invalid.

  FIG. 9 shows a configuration diagram showing an embodiment in which a resident area valid register is added to the embodiment of FIG. The replacement candidate control circuit 5 shown in the embodiment of FIG. 9 includes a resident area setting register 50 for setting a resident area, a comparator 53 for determining whether or not the CPU address is the resident area, and way selection. The product of the setting of the way selection circuit 54 to be controlled, the setting of the resident area valid register 56 for setting whether to enable or disable the setting of the resident area setting register 50, and the setting of the resident area setting register 50. It is composed of an AND circuit 57 for taking.

  This embodiment can be realized by adding the resident area valid register 56 to the embodiment of FIG. 2, and whether the resident area is valid or invalid is determined by the value of the resident area valid register 56. When the setting of the resident area valid register 56 is in an inactive state, that is, when it is set to ‘0’, the setting of the resident area setting register 50 becomes invalid. Also, when the setting of the resident area valid register 56 is in an active state, that is, when it is set to “1”, the setting of the resident area setting register 50 becomes valid.

  As described above, in the present invention, by removing the instruction codes and data that are resident in the cache memory 3 from the replacement candidates and making them resident, the cache hit rate is improved and the processing of instructions and data is accelerated. Is done. Furthermore, by reducing the data bus state change by reducing the access to the main storage device 2 and reducing the access to the main storage device 2, it is possible to expect a good effect in terms of reducing the power consumption. In addition, since a resident area is set in order from a circuit-determined way and excluded from replacement candidates, simplification of circuit resources required for mounting can be achieved.

It is a block diagram of the cache memory device of the present invention. It is a block diagram which shows embodiment of the replacement candidate control circuit of this invention. It is a figure which shows the resident area | region of the cache memory in the cache memory apparatus of this invention. It is a figure which shows the flow of the program for operating the system using the cache memory apparatus of this invention. It is a block diagram which shows embodiment which enables the setting of a several residence area. It is a figure which shows operation | movement when the resident area | region of the cache memory overlaps in the cache memory apparatus of this invention. 4 is an operation flowchart of the cache memory device of the present invention. FIG. 3 is a configuration diagram showing an embodiment when the end of the resident area is set as a final address designation from the embodiment of FIG. 2. It is a block diagram which shows embodiment which added the resident area | region effective register to embodiment of FIG. It is a block diagram of the conventional cache memory device. It is a figure which shows the replacement candidate of the cache memory in the conventional cache memory device.

Explanation of symbols

1 CPU
2 Main storage device 3 Cache memory 4 Cache memory control circuit 5 Replacement candidate control circuit 11 Resident area on cache memory 12 Replacement candidate on cache memory 111 First resident area on cache memory 112 Second resident area on cache memory Area 113 Third resident area on cache memory 114 Fourth resident area on cache memory 50 Resident area setting register 51 Resident area head address register 52 Resident area size register 53 Comparator 54 Way selection circuit 55 Resident area last address register 56 Resident area valid register 57 AND circuit 501 Plural resident area setting register 531 Plural comparators 541 Way selection circuit

Claims (7)

A CPU for processing instruction codes or data, including at least a resident instruction code for setting a resident area;
A cache memory having two or more ways for temporarily storing the instruction code or data;
A cache memory control circuit for performing replacement control and read control of the cache memory;
A cache memory device comprising replacement candidate control means for setting a resident area in a predetermined area by the resident instruction code. The replacement candidate control means includes resident area setting means for setting a resident area by the resident instruction code, and way selection means for selecting a way for performing a replacement operation. Cache memory device. The way selection means uniquely selects the way of the resident area candidate in advance when executing the resident instruction code, and selects a way excluding the resident area during replacement operation when the resident instruction code is not executed. The cache memory device according to claim 2. 4. The cache memory device according to claim 1, wherein the predetermined resident area is a continuous line on the way selected by the way selection means. 5. The cache memory device according to claim 2, wherein the resident area setting means designates a head address for determining a resident area and a size of the area. 5. The cache memory device according to claim 2, wherein the resident area setting means designates a start address and an end address for determining a resident area. The replacement candidate control means includes setting means for determining validity / invalidity of an area setting in which an instruction code or data to be resident in the cache memory is stored, and the resident area when the setting means is deactivated 7. The cache memory device according to claim 5, wherein the resident setting by the setting unit is invalidated.